1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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9 // this list of conditions and the following disclaimer.
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16 // be used to endorse or promote products derived from this software without
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19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_
37 #define V8_MIPS_ASSEMBLER_MIPS_H_
41 #include "src/assembler.h"
42 #include "src/mips/constants-mips.h"
43 #include "src/serialize.h"
50 // 1) We would prefer to use an enum, but enum values are assignment-
51 // compatible with int, which has caused code-generation bugs.
53 // 2) We would prefer to use a class instead of a struct but we don't like
54 // the register initialization to depend on the particular initialization
55 // order (which appears to be different on OS X, Linux, and Windows for the
56 // installed versions of C++ we tried). Using a struct permits C-style
57 // "initialization". Also, the Register objects cannot be const as this
58 // forces initialization stubs in MSVC, making us dependent on initialization
61 // 3) By not using an enum, we are possibly preventing the compiler from
62 // doing certain constant folds, which may significantly reduce the
63 // code generated for some assembly instructions (because they boil down
64 // to a few constants). If this is a problem, we could change the code
65 // such that we use an enum in optimized mode, and the struct in debug
66 // mode. This way we get the compile-time error checking in debug mode
67 // and best performance in optimized code.
70 // -----------------------------------------------------------------------------
71 // Implementation of Register and FPURegister.
75 static const int kNumRegisters = v8::internal::kNumRegisters;
76 static const int kMaxNumAllocatableRegisters = 14; // v0 through t6 and cp.
77 static const int kSizeInBytes = 4;
78 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
80 #if defined(V8_TARGET_LITTLE_ENDIAN)
81 static const int kMantissaOffset = 0;
82 static const int kExponentOffset = 4;
83 #elif defined(V8_TARGET_BIG_ENDIAN)
84 static const int kMantissaOffset = 4;
85 static const int kExponentOffset = 0;
87 #error Unknown endianness
90 inline static int NumAllocatableRegisters();
92 static int ToAllocationIndex(Register reg) {
93 DCHECK((reg.code() - 2) < (kMaxNumAllocatableRegisters - 1) ||
94 reg.is(from_code(kCpRegister)));
95 return reg.is(from_code(kCpRegister)) ?
96 kMaxNumAllocatableRegisters - 1 : // Return last index for 'cp'.
97 reg.code() - 2; // zero_reg and 'at' are skipped.
100 static Register FromAllocationIndex(int index) {
101 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
102 return index == kMaxNumAllocatableRegisters - 1 ?
103 from_code(kCpRegister) : // Last index is always the 'cp' register.
104 from_code(index + 2); // zero_reg and 'at' are skipped.
107 static const char* AllocationIndexToString(int index) {
108 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
109 const char* const names[] = {
128 static Register from_code(int code) {
129 Register r = { code };
133 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
134 bool is(Register reg) const { return code_ == reg.code_; }
144 // Unfortunately we can't make this private in a struct.
148 #define REGISTER(N, C) \
149 const int kRegister_ ## N ## _Code = C; \
150 const Register N = { C }
152 REGISTER(no_reg, -1);
154 REGISTER(zero_reg, 0);
155 // at: Reserved for synthetic instructions.
157 // v0, v1: Used when returning multiple values from subroutines.
160 // a0 - a4: Used to pass non-FP parameters.
165 // t0 - t9: Can be used without reservation, act as temporary registers and are
166 // allowed to be destroyed by subroutines.
175 // s0 - s7: Subroutine register variables. Subroutines that write to these
176 // registers must restore their values before exiting so that the caller can
177 // expect the values to be preserved.
188 // k0, k1: Reserved for system calls and interrupt handlers.
193 // sp: Stack pointer.
195 // fp: Frame pointer.
197 // ra: Return address pointer.
203 int ToNumber(Register reg);
205 Register ToRegister(int num);
207 // Coprocessor register.
209 static const int kMaxNumRegisters = v8::internal::kNumFPURegisters;
211 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers
212 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to
213 // number of Double regs (64-bit regs, or FPU-reg-pairs).
215 // A few double registers are reserved: one as a scratch register and one to
218 // f30: scratch register.
219 static const int kNumReservedRegisters = 2;
220 static const int kMaxNumAllocatableRegisters = kMaxNumRegisters / 2 -
221 kNumReservedRegisters;
223 inline static int NumRegisters();
224 inline static int NumAllocatableRegisters();
225 inline static int ToAllocationIndex(FPURegister reg);
226 static const char* AllocationIndexToString(int index);
228 static FPURegister FromAllocationIndex(int index) {
229 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
230 return from_code(index * 2);
233 static FPURegister from_code(int code) {
234 FPURegister r = { code };
238 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters ; }
239 bool is(FPURegister creg) const { return code_ == creg.code_; }
240 FPURegister low() const {
241 // Find low reg of a Double-reg pair, which is the reg itself.
242 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
245 DCHECK(reg.is_valid());
248 FPURegister high() const {
249 // Find high reg of a Doubel-reg pair, which is reg + 1.
250 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
252 reg.code_ = code_ + 1;
253 DCHECK(reg.is_valid());
265 void setcode(int f) {
269 // Unfortunately we can't make this private in a struct.
273 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32
274 // 32-bit registers, f0 through f31. When used as 'double' they are used
275 // in pairs, starting with the even numbered register. So a double operation
276 // on f0 really uses f0 and f1.
277 // (Modern mips hardware also supports 32 64-bit registers, via setting
278 // (priviledged) Status Register FR bit to 1. This is used by the N32 ABI,
279 // but it is not in common use. Someday we will want to support this in v8.)
281 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers.
282 typedef FPURegister DoubleRegister;
283 typedef FPURegister FloatRegister;
285 const FPURegister no_freg = { -1 };
287 const FPURegister f0 = { 0 }; // Return value in hard float mode.
288 const FPURegister f1 = { 1 };
289 const FPURegister f2 = { 2 };
290 const FPURegister f3 = { 3 };
291 const FPURegister f4 = { 4 };
292 const FPURegister f5 = { 5 };
293 const FPURegister f6 = { 6 };
294 const FPURegister f7 = { 7 };
295 const FPURegister f8 = { 8 };
296 const FPURegister f9 = { 9 };
297 const FPURegister f10 = { 10 };
298 const FPURegister f11 = { 11 };
299 const FPURegister f12 = { 12 }; // Arg 0 in hard float mode.
300 const FPURegister f13 = { 13 };
301 const FPURegister f14 = { 14 }; // Arg 1 in hard float mode.
302 const FPURegister f15 = { 15 };
303 const FPURegister f16 = { 16 };
304 const FPURegister f17 = { 17 };
305 const FPURegister f18 = { 18 };
306 const FPURegister f19 = { 19 };
307 const FPURegister f20 = { 20 };
308 const FPURegister f21 = { 21 };
309 const FPURegister f22 = { 22 };
310 const FPURegister f23 = { 23 };
311 const FPURegister f24 = { 24 };
312 const FPURegister f25 = { 25 };
313 const FPURegister f26 = { 26 };
314 const FPURegister f27 = { 27 };
315 const FPURegister f28 = { 28 };
316 const FPURegister f29 = { 29 };
317 const FPURegister f30 = { 30 };
318 const FPURegister f31 = { 31 };
321 // cp is assumed to be a callee saved register.
322 // Defined using #define instead of "static const Register&" because Clang
323 // complains otherwise when a compilation unit that includes this header
324 // doesn't use the variables.
325 #define kRootRegister s6
327 #define kLithiumScratchReg s3
328 #define kLithiumScratchReg2 s4
329 #define kLithiumScratchDouble f30
330 #define kDoubleRegZero f28
331 // Used on mips32r6 for compare operations.
332 #define kDoubleCompareReg f31
334 // FPU (coprocessor 1) control registers.
335 // Currently only FCSR (#31) is implemented.
336 struct FPUControlRegister {
337 bool is_valid() const { return code_ == kFCSRRegister; }
338 bool is(FPUControlRegister creg) const { return code_ == creg.code_; }
347 void setcode(int f) {
351 // Unfortunately we can't make this private in a struct.
355 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
356 const FPUControlRegister FCSR = { kFCSRRegister };
358 // -----------------------------------------------------------------------------
359 // Machine instruction Operands.
361 // Class Operand represents a shifter operand in data processing instructions.
362 class Operand BASE_EMBEDDED {
365 INLINE(explicit Operand(int32_t immediate,
366 RelocInfo::Mode rmode = RelocInfo::NONE32));
367 INLINE(explicit Operand(const ExternalReference& f));
368 INLINE(explicit Operand(const char* s));
369 INLINE(explicit Operand(Object** opp));
370 INLINE(explicit Operand(Context** cpp));
371 explicit Operand(Handle<Object> handle);
372 INLINE(explicit Operand(Smi* value));
375 INLINE(explicit Operand(Register rm));
377 // Return true if this is a register operand.
378 INLINE(bool is_reg() const);
380 inline int32_t immediate() const {
385 Register rm() const { return rm_; }
389 int32_t imm32_; // Valid if rm_ == no_reg.
390 RelocInfo::Mode rmode_;
392 friend class Assembler;
393 friend class MacroAssembler;
397 // On MIPS we have only one adressing mode with base_reg + offset.
398 // Class MemOperand represents a memory operand in load and store instructions.
399 class MemOperand : public Operand {
401 // Immediate value attached to offset.
403 offset_minus_one = -1,
407 explicit MemOperand(Register rn, int32_t offset = 0);
408 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier,
409 OffsetAddend offset_addend = offset_zero);
410 int32_t offset() const { return offset_; }
412 bool OffsetIsInt16Encodable() const {
413 return is_int16(offset_);
419 friend class Assembler;
423 class Assembler : public AssemblerBase {
425 // Create an assembler. Instructions and relocation information are emitted
426 // into a buffer, with the instructions starting from the beginning and the
427 // relocation information starting from the end of the buffer. See CodeDesc
428 // for a detailed comment on the layout (globals.h).
430 // If the provided buffer is NULL, the assembler allocates and grows its own
431 // buffer, and buffer_size determines the initial buffer size. The buffer is
432 // owned by the assembler and deallocated upon destruction of the assembler.
434 // If the provided buffer is not NULL, the assembler uses the provided buffer
435 // for code generation and assumes its size to be buffer_size. If the buffer
436 // is too small, a fatal error occurs. No deallocation of the buffer is done
437 // upon destruction of the assembler.
438 Assembler(Isolate* isolate, void* buffer, int buffer_size);
439 virtual ~Assembler() { }
441 // GetCode emits any pending (non-emitted) code and fills the descriptor
442 // desc. GetCode() is idempotent; it returns the same result if no other
443 // Assembler functions are invoked in between GetCode() calls.
444 void GetCode(CodeDesc* desc);
446 // Label operations & relative jumps (PPUM Appendix D).
448 // Takes a branch opcode (cc) and a label (L) and generates
449 // either a backward branch or a forward branch and links it
450 // to the label fixup chain. Usage:
452 // Label L; // unbound label
453 // j(cc, &L); // forward branch to unbound label
454 // bind(&L); // bind label to the current pc
455 // j(cc, &L); // backward branch to bound label
456 // bind(&L); // illegal: a label may be bound only once
458 // Note: The same Label can be used for forward and backward branches
459 // but it may be bound only once.
460 void bind(Label* L); // Binds an unbound label L to current code position.
461 // Determines if Label is bound and near enough so that branch instruction
462 // can be used to reach it, instead of jump instruction.
463 bool is_near(Label* L);
465 // Returns the branch offset to the given label from the current code
466 // position. Links the label to the current position if it is still unbound.
467 // Manages the jump elimination optimization if the second parameter is true.
468 int32_t branch_offset(Label* L, bool jump_elimination_allowed);
469 int32_t branch_offset_compact(Label* L, bool jump_elimination_allowed);
470 int32_t branch_offset21(Label* L, bool jump_elimination_allowed);
471 int32_t branch_offset21_compact(Label* L, bool jump_elimination_allowed);
472 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
473 int32_t o = branch_offset(L, jump_elimination_allowed);
474 DCHECK((o & 3) == 0); // Assert the offset is aligned.
477 int32_t shifted_branch_offset_compact(Label* L,
478 bool jump_elimination_allowed) {
479 int32_t o = branch_offset_compact(L, jump_elimination_allowed);
480 DCHECK((o & 3) == 0); // Assert the offset is aligned.
483 uint32_t jump_address(Label* L);
485 // Puts a labels target address at the given position.
486 // The high 8 bits are set to zero.
487 void label_at_put(Label* L, int at_offset);
489 // Read/Modify the code target address in the branch/call instruction at pc.
490 static Address target_address_at(Address pc);
491 static void set_target_address_at(Address pc,
493 ICacheFlushMode icache_flush_mode =
494 FLUSH_ICACHE_IF_NEEDED);
495 // On MIPS there is no Constant Pool so we skip that parameter.
496 INLINE(static Address target_address_at(Address pc,
497 ConstantPoolArray* constant_pool)) {
498 return target_address_at(pc);
500 INLINE(static void set_target_address_at(Address pc,
501 ConstantPoolArray* constant_pool,
503 ICacheFlushMode icache_flush_mode =
504 FLUSH_ICACHE_IF_NEEDED)) {
505 set_target_address_at(pc, target, icache_flush_mode);
507 INLINE(static Address target_address_at(Address pc, Code* code)) {
508 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
509 return target_address_at(pc, constant_pool);
511 INLINE(static void set_target_address_at(Address pc,
514 ICacheFlushMode icache_flush_mode =
515 FLUSH_ICACHE_IF_NEEDED)) {
516 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
517 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
520 // Return the code target address at a call site from the return address
521 // of that call in the instruction stream.
522 inline static Address target_address_from_return_address(Address pc);
524 // Return the code target address of the patch debug break slot
525 inline static Address break_address_from_return_address(Address pc);
527 static void JumpLabelToJumpRegister(Address pc);
529 static void QuietNaN(HeapObject* nan);
531 // This sets the branch destination (which gets loaded at the call address).
532 // This is for calls and branches within generated code. The serializer
533 // has already deserialized the lui/ori instructions etc.
534 inline static void deserialization_set_special_target_at(
535 Address instruction_payload, Code* code, Address target) {
536 set_target_address_at(
537 instruction_payload - kInstructionsFor32BitConstant * kInstrSize,
542 // Size of an instruction.
543 static const int kInstrSize = sizeof(Instr);
545 // Difference between address of current opcode and target address offset.
546 static const int kBranchPCOffset = 4;
548 // Here we are patching the address in the LUI/ORI instruction pair.
549 // These values are used in the serialization process and must be zero for
550 // MIPS platform, as Code, Embedded Object or External-reference pointers
551 // are split across two consecutive instructions and don't exist separately
552 // in the code, so the serializer should not step forwards in memory after
553 // a target is resolved and written.
554 static const int kSpecialTargetSize = 0;
556 // Number of consecutive instructions used to store 32bit constant.
557 // Before jump-optimizations, this constant was used in
558 // RelocInfo::target_address_address() function to tell serializer address of
559 // the instruction that follows LUI/ORI instruction pair. Now, with new jump
560 // optimization, where jump-through-register instruction that usually
561 // follows LUI/ORI pair is substituted with J/JAL, this constant equals
562 // to 3 instructions (LUI+ORI+J/JAL/JR/JALR).
563 static const int kInstructionsFor32BitConstant = 3;
565 // Distance between the instruction referring to the address of the call
566 // target and the return address.
567 static const int kCallTargetAddressOffset = 4 * kInstrSize;
569 // Distance between start of patched return sequence and the emitted address
571 static const int kPatchReturnSequenceAddressOffset = 0;
573 // Distance between start of patched debug break slot and the emitted address
575 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
577 // Difference between address of current opcode and value read from pc
579 static const int kPcLoadDelta = 4;
581 static const int kPatchDebugBreakSlotReturnOffset = 4 * kInstrSize;
583 // Number of instructions used for the JS return sequence. The constant is
584 // used by the debugger to patch the JS return sequence.
585 static const int kJSReturnSequenceInstructions = 7;
586 static const int kDebugBreakSlotInstructions = 4;
587 static const int kDebugBreakSlotLength =
588 kDebugBreakSlotInstructions * kInstrSize;
591 // ---------------------------------------------------------------------------
594 // Insert the smallest number of nop instructions
595 // possible to align the pc offset to a multiple
596 // of m. m must be a power of 2 (>= 4).
598 // Aligns code to something that's optimal for a jump target for the platform.
599 void CodeTargetAlign();
601 // Different nop operations are used by the code generator to detect certain
602 // states of the generated code.
603 enum NopMarkerTypes {
607 PROPERTY_ACCESS_INLINED,
608 PROPERTY_ACCESS_INLINED_CONTEXT,
609 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
612 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED,
614 CODE_AGE_MARKER_NOP = 6,
615 CODE_AGE_SEQUENCE_NOP
618 // Type == 0 is the default non-marking nop. For mips this is a
619 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero
620 // marking, to avoid conflict with ssnop and ehb instructions.
621 void nop(unsigned int type = 0) {
623 Register nop_rt_reg = (type == 0) ? zero_reg : at;
624 sll(zero_reg, nop_rt_reg, type, true);
628 // --------Branch-and-jump-instructions----------
629 // We don't use likely variant of instructions.
630 void b(int16_t offset);
631 void b(Label* L) { b(branch_offset(L, false)>>2); }
632 void bal(int16_t offset);
633 void bal(Label* L) { bal(branch_offset(L, false)>>2); }
635 void beq(Register rs, Register rt, int16_t offset);
636 void beq(Register rs, Register rt, Label* L) {
637 beq(rs, rt, branch_offset(L, false) >> 2);
639 void bgez(Register rs, int16_t offset);
640 void bgezc(Register rt, int16_t offset);
641 void bgezc(Register rt, Label* L) {
642 bgezc(rt, branch_offset_compact(L, false)>>2);
644 void bgeuc(Register rs, Register rt, int16_t offset);
645 void bgeuc(Register rs, Register rt, Label* L) {
646 bgeuc(rs, rt, branch_offset_compact(L, false)>>2);
648 void bgec(Register rs, Register rt, int16_t offset);
649 void bgec(Register rs, Register rt, Label* L) {
650 bgec(rs, rt, branch_offset_compact(L, false)>>2);
652 void bgezal(Register rs, int16_t offset);
653 void bgezalc(Register rt, int16_t offset);
654 void bgezalc(Register rt, Label* L) {
655 bgezalc(rt, branch_offset_compact(L, false)>>2);
657 void bgezall(Register rs, int16_t offset);
658 void bgezall(Register rs, Label* L) {
659 bgezall(rs, branch_offset(L, false)>>2);
661 void bgtz(Register rs, int16_t offset);
662 void bgtzc(Register rt, int16_t offset);
663 void bgtzc(Register rt, Label* L) {
664 bgtzc(rt, branch_offset_compact(L, false)>>2);
666 void blez(Register rs, int16_t offset);
667 void blezc(Register rt, int16_t offset);
668 void blezc(Register rt, Label* L) {
669 blezc(rt, branch_offset_compact(L, false)>>2);
671 void bltz(Register rs, int16_t offset);
672 void bltzc(Register rt, int16_t offset);
673 void bltzc(Register rt, Label* L) {
674 bltzc(rt, branch_offset_compact(L, false)>>2);
676 void bltuc(Register rs, Register rt, int16_t offset);
677 void bltuc(Register rs, Register rt, Label* L) {
678 bltuc(rs, rt, branch_offset_compact(L, false)>>2);
680 void bltc(Register rs, Register rt, int16_t offset);
681 void bltc(Register rs, Register rt, Label* L) {
682 bltc(rs, rt, branch_offset_compact(L, false)>>2);
684 void bltzal(Register rs, int16_t offset);
685 void blezalc(Register rt, int16_t offset);
686 void blezalc(Register rt, Label* L) {
687 blezalc(rt, branch_offset_compact(L, false)>>2);
689 void bltzalc(Register rt, int16_t offset);
690 void bltzalc(Register rt, Label* L) {
691 bltzalc(rt, branch_offset_compact(L, false)>>2);
693 void bgtzalc(Register rt, int16_t offset);
694 void bgtzalc(Register rt, Label* L) {
695 bgtzalc(rt, branch_offset_compact(L, false)>>2);
697 void beqzalc(Register rt, int16_t offset);
698 void beqzalc(Register rt, Label* L) {
699 beqzalc(rt, branch_offset_compact(L, false)>>2);
701 void beqc(Register rs, Register rt, int16_t offset);
702 void beqc(Register rs, Register rt, Label* L) {
703 beqc(rs, rt, branch_offset_compact(L, false)>>2);
705 void beqzc(Register rs, int32_t offset);
706 void beqzc(Register rs, Label* L) {
707 beqzc(rs, branch_offset21_compact(L, false)>>2);
709 void bnezalc(Register rt, int16_t offset);
710 void bnezalc(Register rt, Label* L) {
711 bnezalc(rt, branch_offset_compact(L, false)>>2);
713 void bnec(Register rs, Register rt, int16_t offset);
714 void bnec(Register rs, Register rt, Label* L) {
715 bnec(rs, rt, branch_offset_compact(L, false)>>2);
717 void bnezc(Register rt, int32_t offset);
718 void bnezc(Register rt, Label* L) {
719 bnezc(rt, branch_offset21_compact(L, false)>>2);
721 void bne(Register rs, Register rt, int16_t offset);
722 void bne(Register rs, Register rt, Label* L) {
723 bne(rs, rt, branch_offset(L, false)>>2);
725 void bovc(Register rs, Register rt, int16_t offset);
726 void bovc(Register rs, Register rt, Label* L) {
727 bovc(rs, rt, branch_offset_compact(L, false)>>2);
729 void bnvc(Register rs, Register rt, int16_t offset);
730 void bnvc(Register rs, Register rt, Label* L) {
731 bnvc(rs, rt, branch_offset_compact(L, false)>>2);
734 // Never use the int16_t b(l)cond version with a branch offset
735 // instead of using the Label* version.
737 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits.
738 void j(int32_t target);
739 void jal(int32_t target);
740 void jalr(Register rs, Register rd = ra);
741 void jr(Register target);
742 void j_or_jr(int32_t target, Register rs);
743 void jal_or_jalr(int32_t target, Register rs);
746 // -------Data-processing-instructions---------
749 void addu(Register rd, Register rs, Register rt);
750 void subu(Register rd, Register rs, Register rt);
751 void mult(Register rs, Register rt);
752 void multu(Register rs, Register rt);
753 void div(Register rs, Register rt);
754 void divu(Register rs, Register rt);
755 void div(Register rd, Register rs, Register rt);
756 void divu(Register rd, Register rs, Register rt);
757 void mod(Register rd, Register rs, Register rt);
758 void modu(Register rd, Register rs, Register rt);
759 void mul(Register rd, Register rs, Register rt);
760 void muh(Register rd, Register rs, Register rt);
761 void mulu(Register rd, Register rs, Register rt);
762 void muhu(Register rd, Register rs, Register rt);
764 void addiu(Register rd, Register rs, int32_t j);
767 void and_(Register rd, Register rs, Register rt);
768 void or_(Register rd, Register rs, Register rt);
769 void xor_(Register rd, Register rs, Register rt);
770 void nor(Register rd, Register rs, Register rt);
772 void andi(Register rd, Register rs, int32_t j);
773 void ori(Register rd, Register rs, int32_t j);
774 void xori(Register rd, Register rs, int32_t j);
775 void lui(Register rd, int32_t j);
776 void aui(Register rs, Register rt, int32_t j);
779 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
780 // and may cause problems in normal code. coming_from_nop makes sure this
782 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
783 void sllv(Register rd, Register rt, Register rs);
784 void srl(Register rd, Register rt, uint16_t sa);
785 void srlv(Register rd, Register rt, Register rs);
786 void sra(Register rt, Register rd, uint16_t sa);
787 void srav(Register rt, Register rd, Register rs);
788 void rotr(Register rd, Register rt, uint16_t sa);
789 void rotrv(Register rd, Register rt, Register rs);
792 // ------------Memory-instructions-------------
794 void lb(Register rd, const MemOperand& rs);
795 void lbu(Register rd, const MemOperand& rs);
796 void lh(Register rd, const MemOperand& rs);
797 void lhu(Register rd, const MemOperand& rs);
798 void lw(Register rd, const MemOperand& rs);
799 void lwl(Register rd, const MemOperand& rs);
800 void lwr(Register rd, const MemOperand& rs);
801 void sb(Register rd, const MemOperand& rs);
802 void sh(Register rd, const MemOperand& rs);
803 void sw(Register rd, const MemOperand& rs);
804 void swl(Register rd, const MemOperand& rs);
805 void swr(Register rd, const MemOperand& rs);
808 // ----------------Prefetch--------------------
810 void pref(int32_t hint, const MemOperand& rs);
813 // -------------Misc-instructions--------------
815 // Break / Trap instructions.
816 void break_(uint32_t code, bool break_as_stop = false);
817 void stop(const char* msg, uint32_t code = kMaxStopCode);
818 void tge(Register rs, Register rt, uint16_t code);
819 void tgeu(Register rs, Register rt, uint16_t code);
820 void tlt(Register rs, Register rt, uint16_t code);
821 void tltu(Register rs, Register rt, uint16_t code);
822 void teq(Register rs, Register rt, uint16_t code);
823 void tne(Register rs, Register rt, uint16_t code);
825 // Move from HI/LO register.
826 void mfhi(Register rd);
827 void mflo(Register rd);
830 void slt(Register rd, Register rs, Register rt);
831 void sltu(Register rd, Register rs, Register rt);
832 void slti(Register rd, Register rs, int32_t j);
833 void sltiu(Register rd, Register rs, int32_t j);
836 void movz(Register rd, Register rs, Register rt);
837 void movn(Register rd, Register rs, Register rt);
838 void movt(Register rd, Register rs, uint16_t cc = 0);
839 void movf(Register rd, Register rs, uint16_t cc = 0);
841 void sel(SecondaryField fmt, FPURegister fd, FPURegister ft,
842 FPURegister fs, uint8_t sel);
843 void seleqz(Register rs, Register rt, Register rd);
844 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister ft,
846 void selnez(Register rs, Register rt, Register rd);
847 void selnez(SecondaryField fmt, FPURegister fd, FPURegister ft,
851 void clz(Register rd, Register rs);
852 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
853 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
855 // --------Coprocessor-instructions----------------
857 // Load, store, and move.
858 void lwc1(FPURegister fd, const MemOperand& src);
859 void ldc1(FPURegister fd, const MemOperand& src);
861 void swc1(FPURegister fs, const MemOperand& dst);
862 void sdc1(FPURegister fs, const MemOperand& dst);
864 void mtc1(Register rt, FPURegister fs);
865 void mthc1(Register rt, FPURegister fs);
867 void mfc1(Register rt, FPURegister fs);
868 void mfhc1(Register rt, FPURegister fs);
870 void ctc1(Register rt, FPUControlRegister fs);
871 void cfc1(Register rt, FPUControlRegister fs);
874 void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
875 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
876 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
877 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
878 void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
879 void abs_d(FPURegister fd, FPURegister fs);
880 void mov_d(FPURegister fd, FPURegister fs);
881 void neg_d(FPURegister fd, FPURegister fs);
882 void sqrt_d(FPURegister fd, FPURegister fs);
885 void cvt_w_s(FPURegister fd, FPURegister fs);
886 void cvt_w_d(FPURegister fd, FPURegister fs);
887 void trunc_w_s(FPURegister fd, FPURegister fs);
888 void trunc_w_d(FPURegister fd, FPURegister fs);
889 void round_w_s(FPURegister fd, FPURegister fs);
890 void round_w_d(FPURegister fd, FPURegister fs);
891 void floor_w_s(FPURegister fd, FPURegister fs);
892 void floor_w_d(FPURegister fd, FPURegister fs);
893 void ceil_w_s(FPURegister fd, FPURegister fs);
894 void ceil_w_d(FPURegister fd, FPURegister fs);
896 void cvt_l_s(FPURegister fd, FPURegister fs);
897 void cvt_l_d(FPURegister fd, FPURegister fs);
898 void trunc_l_s(FPURegister fd, FPURegister fs);
899 void trunc_l_d(FPURegister fd, FPURegister fs);
900 void round_l_s(FPURegister fd, FPURegister fs);
901 void round_l_d(FPURegister fd, FPURegister fs);
902 void floor_l_s(FPURegister fd, FPURegister fs);
903 void floor_l_d(FPURegister fd, FPURegister fs);
904 void ceil_l_s(FPURegister fd, FPURegister fs);
905 void ceil_l_d(FPURegister fd, FPURegister fs);
907 void min(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
908 void mina(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
909 void max(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
910 void maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
912 void cvt_s_w(FPURegister fd, FPURegister fs);
913 void cvt_s_l(FPURegister fd, FPURegister fs);
914 void cvt_s_d(FPURegister fd, FPURegister fs);
916 void cvt_d_w(FPURegister fd, FPURegister fs);
917 void cvt_d_l(FPURegister fd, FPURegister fs);
918 void cvt_d_s(FPURegister fd, FPURegister fs);
920 // Conditions and branches for MIPSr6.
921 void cmp(FPUCondition cond, SecondaryField fmt,
922 FPURegister fd, FPURegister ft, FPURegister fs);
924 void bc1eqz(int16_t offset, FPURegister ft);
925 void bc1eqz(Label* L, FPURegister ft) {
926 bc1eqz(branch_offset(L, false)>>2, ft);
928 void bc1nez(int16_t offset, FPURegister ft);
929 void bc1nez(Label* L, FPURegister ft) {
930 bc1nez(branch_offset(L, false)>>2, ft);
933 // Conditions and branches for non MIPSr6.
934 void c(FPUCondition cond, SecondaryField fmt,
935 FPURegister ft, FPURegister fs, uint16_t cc = 0);
937 void bc1f(int16_t offset, uint16_t cc = 0);
938 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
939 void bc1t(int16_t offset, uint16_t cc = 0);
940 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
941 void fcmp(FPURegister src1, const double src2, FPUCondition cond);
943 // Check the code size generated from label to here.
944 int SizeOfCodeGeneratedSince(Label* label) {
945 return pc_offset() - label->pos();
948 // Check the number of instructions generated from label to here.
949 int InstructionsGeneratedSince(Label* label) {
950 return SizeOfCodeGeneratedSince(label) / kInstrSize;
953 // Class for scoping postponing the trampoline pool generation.
954 class BlockTrampolinePoolScope {
956 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) {
957 assem_->StartBlockTrampolinePool();
959 ~BlockTrampolinePoolScope() {
960 assem_->EndBlockTrampolinePool();
966 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope);
969 // Class for postponing the assembly buffer growth. Typically used for
970 // sequences of instructions that must be emitted as a unit, before
971 // buffer growth (and relocation) can occur.
972 // This blocking scope is not nestable.
973 class BlockGrowBufferScope {
975 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) {
976 assem_->StartBlockGrowBuffer();
978 ~BlockGrowBufferScope() {
979 assem_->EndBlockGrowBuffer();
985 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope);
990 // Mark address of the ExitJSFrame code.
991 void RecordJSReturn();
993 // Mark address of a debug break slot.
994 void RecordDebugBreakSlot();
996 // Record the AST id of the CallIC being compiled, so that it can be placed
997 // in the relocation information.
998 void SetRecordedAstId(TypeFeedbackId ast_id) {
999 DCHECK(recorded_ast_id_.IsNone());
1000 recorded_ast_id_ = ast_id;
1003 TypeFeedbackId RecordedAstId() {
1004 DCHECK(!recorded_ast_id_.IsNone());
1005 return recorded_ast_id_;
1008 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); }
1010 // Record a comment relocation entry that can be used by a disassembler.
1011 // Use --code-comments to enable.
1012 void RecordComment(const char* msg);
1014 static int RelocateInternalReference(byte* pc, intptr_t pc_delta);
1016 // Writes a single byte or word of data in the code stream. Used for
1017 // inline tables, e.g., jump-tables.
1018 void db(uint8_t data);
1019 void dd(uint32_t data);
1021 // Emits the address of the code stub's first instruction.
1022 void emit_code_stub_address(Code* stub);
1024 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1026 // Postpone the generation of the trampoline pool for the specified number of
1028 void BlockTrampolinePoolFor(int instructions);
1030 // Check if there is less than kGap bytes available in the buffer.
1031 // If this is the case, we need to grow the buffer before emitting
1032 // an instruction or relocation information.
1033 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
1035 // Get the number of bytes available in the buffer.
1036 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1038 // Read/patch instructions.
1039 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
1040 static void instr_at_put(byte* pc, Instr instr) {
1041 *reinterpret_cast<Instr*>(pc) = instr;
1043 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
1044 void instr_at_put(int pos, Instr instr) {
1045 *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
1048 // Check if an instruction is a branch of some kind.
1049 static bool IsBranch(Instr instr);
1050 static bool IsBeq(Instr instr);
1051 static bool IsBne(Instr instr);
1053 static bool IsJump(Instr instr);
1054 static bool IsJ(Instr instr);
1055 static bool IsLui(Instr instr);
1056 static bool IsOri(Instr instr);
1058 static bool IsJal(Instr instr);
1059 static bool IsJr(Instr instr);
1060 static bool IsJalr(Instr instr);
1062 static bool IsNop(Instr instr, unsigned int type);
1063 static bool IsPop(Instr instr);
1064 static bool IsPush(Instr instr);
1065 static bool IsLwRegFpOffset(Instr instr);
1066 static bool IsSwRegFpOffset(Instr instr);
1067 static bool IsLwRegFpNegOffset(Instr instr);
1068 static bool IsSwRegFpNegOffset(Instr instr);
1070 static Register GetRtReg(Instr instr);
1071 static Register GetRsReg(Instr instr);
1072 static Register GetRdReg(Instr instr);
1074 static uint32_t GetRt(Instr instr);
1075 static uint32_t GetRtField(Instr instr);
1076 static uint32_t GetRs(Instr instr);
1077 static uint32_t GetRsField(Instr instr);
1078 static uint32_t GetRd(Instr instr);
1079 static uint32_t GetRdField(Instr instr);
1080 static uint32_t GetSa(Instr instr);
1081 static uint32_t GetSaField(Instr instr);
1082 static uint32_t GetOpcodeField(Instr instr);
1083 static uint32_t GetFunction(Instr instr);
1084 static uint32_t GetFunctionField(Instr instr);
1085 static uint32_t GetImmediate16(Instr instr);
1086 static uint32_t GetLabelConst(Instr instr);
1088 static int32_t GetBranchOffset(Instr instr);
1089 static bool IsLw(Instr instr);
1090 static int16_t GetLwOffset(Instr instr);
1091 static Instr SetLwOffset(Instr instr, int16_t offset);
1093 static bool IsSw(Instr instr);
1094 static Instr SetSwOffset(Instr instr, int16_t offset);
1095 static bool IsAddImmediate(Instr instr);
1096 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
1098 static bool IsAndImmediate(Instr instr);
1099 static bool IsEmittedConstant(Instr instr);
1101 void CheckTrampolinePool();
1103 // Allocate a constant pool of the correct size for the generated code.
1104 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1106 // Generate the constant pool for the generated code.
1107 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1110 // Relocation for a type-recording IC has the AST id added to it. This
1111 // member variable is a way to pass the information from the call site to
1112 // the relocation info.
1113 TypeFeedbackId recorded_ast_id_;
1115 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
1117 // Decode branch instruction at pos and return branch target pos.
1118 int target_at(int32_t pos);
1120 // Patch branch instruction at pos to branch to given branch target pos.
1121 void target_at_put(int32_t pos, int32_t target_pos);
1123 // Say if we need to relocate with this mode.
1124 bool MustUseReg(RelocInfo::Mode rmode);
1126 // Record reloc info for current pc_.
1127 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1129 // Block the emission of the trampoline pool before pc_offset.
1130 void BlockTrampolinePoolBefore(int pc_offset) {
1131 if (no_trampoline_pool_before_ < pc_offset)
1132 no_trampoline_pool_before_ = pc_offset;
1135 void StartBlockTrampolinePool() {
1136 trampoline_pool_blocked_nesting_++;
1139 void EndBlockTrampolinePool() {
1140 trampoline_pool_blocked_nesting_--;
1143 bool is_trampoline_pool_blocked() const {
1144 return trampoline_pool_blocked_nesting_ > 0;
1147 bool has_exception() const {
1148 return internal_trampoline_exception_;
1151 void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi);
1153 bool is_trampoline_emitted() const {
1154 return trampoline_emitted_;
1157 // Temporarily block automatic assembly buffer growth.
1158 void StartBlockGrowBuffer() {
1159 DCHECK(!block_buffer_growth_);
1160 block_buffer_growth_ = true;
1163 void EndBlockGrowBuffer() {
1164 DCHECK(block_buffer_growth_);
1165 block_buffer_growth_ = false;
1168 bool is_buffer_growth_blocked() const {
1169 return block_buffer_growth_;
1173 // Buffer size and constant pool distance are checked together at regular
1174 // intervals of kBufferCheckInterval emitted bytes.
1175 static const int kBufferCheckInterval = 1*KB/2;
1178 // The relocation writer's position is at least kGap bytes below the end of
1179 // the generated instructions. This is so that multi-instruction sequences do
1180 // not have to check for overflow. The same is true for writes of large
1181 // relocation info entries.
1182 static const int kGap = 32;
1185 // Repeated checking whether the trampoline pool should be emitted is rather
1186 // expensive. By default we only check again once a number of instructions
1187 // has been generated.
1188 static const int kCheckConstIntervalInst = 32;
1189 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
1191 int next_buffer_check_; // pc offset of next buffer check.
1193 // Emission of the trampoline pool may be blocked in some code sequences.
1194 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero.
1195 int no_trampoline_pool_before_; // Block emission before this pc offset.
1197 // Keep track of the last emitted pool to guarantee a maximal distance.
1198 int last_trampoline_pool_end_; // pc offset of the end of the last pool.
1200 // Automatic growth of the assembly buffer may be blocked for some sequences.
1201 bool block_buffer_growth_; // Block growth when true.
1203 // Relocation information generation.
1204 // Each relocation is encoded as a variable size value.
1205 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
1206 RelocInfoWriter reloc_info_writer;
1208 // The bound position, before this we cannot do instruction elimination.
1209 int last_bound_pos_;
1212 inline void CheckBuffer();
1214 inline void emit(Instr x);
1215 inline void CheckTrampolinePoolQuick();
1217 // Instruction generation.
1218 // We have 3 different kind of encoding layout on MIPS.
1219 // However due to many different types of objects encoded in the same fields
1220 // we have quite a few aliases for each mode.
1221 // Using the same structure to refer to Register and FPURegister would spare a
1222 // few aliases, but mixing both does not look clean to me.
1223 // Anyway we could surely implement this differently.
1225 void GenInstrRegister(Opcode opcode,
1230 SecondaryField func = NULLSF);
1232 void GenInstrRegister(Opcode opcode,
1237 SecondaryField func);
1239 void GenInstrRegister(Opcode opcode,
1244 SecondaryField func = NULLSF);
1246 void GenInstrRegister(Opcode opcode,
1251 SecondaryField func = NULLSF);
1253 void GenInstrRegister(Opcode opcode,
1258 SecondaryField func = NULLSF);
1260 void GenInstrRegister(Opcode opcode,
1263 FPUControlRegister fs,
1264 SecondaryField func = NULLSF);
1267 void GenInstrImmediate(Opcode opcode,
1271 void GenInstrImmediate(Opcode opcode,
1275 void GenInstrImmediate(Opcode opcode,
1281 void GenInstrJump(Opcode opcode,
1285 void LoadRegPlusOffsetToAt(const MemOperand& src);
1288 void print(Label* L);
1289 void bind_to(Label* L, int pos);
1290 void next(Label* L);
1292 // One trampoline consists of:
1293 // - space for trampoline slots,
1294 // - space for labels.
1296 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize.
1297 // Space for trampoline slots preceeds space for labels. Each label is of one
1298 // instruction size, so total amount for labels is equal to
1299 // label_count * kInstrSize.
1305 free_slot_count_ = 0;
1308 Trampoline(int start, int slot_count) {
1311 free_slot_count_ = slot_count;
1312 end_ = start + slot_count * kTrampolineSlotsSize;
1321 int trampoline_slot = kInvalidSlotPos;
1322 if (free_slot_count_ <= 0) {
1323 // We have run out of space on trampolines.
1324 // Make sure we fail in debug mode, so we become aware of each case
1325 // when this happens.
1327 // Internal exception will be caught.
1329 trampoline_slot = next_slot_;
1331 next_slot_ += kTrampolineSlotsSize;
1333 return trampoline_slot;
1340 int free_slot_count_;
1343 int32_t get_trampoline_entry(int32_t pos);
1344 int unbound_labels_count_;
1345 // If trampoline is emitted, generated code is becoming large. As this is
1346 // already a slow case which can possibly break our code generation for the
1347 // extreme case, we use this information to trigger different mode of
1348 // branch instruction generation, where we use jump instructions rather
1349 // than regular branch instructions.
1350 bool trampoline_emitted_;
1351 static const int kTrampolineSlotsSize = 4 * kInstrSize;
1352 static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
1353 static const int kInvalidSlotPos = -1;
1355 Trampoline trampoline_;
1356 bool internal_trampoline_exception_;
1358 friend class RegExpMacroAssemblerMIPS;
1359 friend class RelocInfo;
1360 friend class CodePatcher;
1361 friend class BlockTrampolinePoolScope;
1363 PositionsRecorder positions_recorder_;
1364 friend class PositionsRecorder;
1365 friend class EnsureSpace;
1369 class EnsureSpace BASE_EMBEDDED {
1371 explicit EnsureSpace(Assembler* assembler) {
1372 assembler->CheckBuffer();
1376 } } // namespace v8::internal
1378 #endif // V8_ARM_ASSEMBLER_MIPS_H_