1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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9 // this list of conditions and the following disclaimer.
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
40 #include "src/isolate.h"
41 #include "src/serialize.h"
48 // 1) We would prefer to use an enum, but enum values are assignment-
49 // compatible with int, which has caused code-generation bugs.
51 // 2) We would prefer to use a class instead of a struct but we don't like
52 // the register initialization to depend on the particular initialization
53 // order (which appears to be different on OS X, Linux, and Windows for the
54 // installed versions of C++ we tried). Using a struct permits C-style
55 // "initialization". Also, the Register objects cannot be const as this
56 // forces initialization stubs in MSVC, making us dependent on initialization
59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code.
68 static const int kMaxNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
72 static const int kNumRegisters = 8;
74 static inline const char* AllocationIndexToString(int index);
76 static inline int ToAllocationIndex(Register reg);
78 static inline Register FromAllocationIndex(int index);
80 static Register from_code(int code) {
82 DCHECK(code < kNumRegisters);
83 Register r = { code };
86 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
87 bool is(Register reg) const { return code_ == reg.code_; }
88 // eax, ebx, ecx and edx are byte registers, the rest are not.
89 bool is_byte_register() const { return code_ <= 3; }
99 // Unfortunately we can't make this private in a struct.
103 const int kRegister_eax_Code = 0;
104 const int kRegister_ecx_Code = 1;
105 const int kRegister_edx_Code = 2;
106 const int kRegister_ebx_Code = 3;
107 const int kRegister_esp_Code = 4;
108 const int kRegister_ebp_Code = 5;
109 const int kRegister_esi_Code = 6;
110 const int kRegister_edi_Code = 7;
111 const int kRegister_no_reg_Code = -1;
113 const Register eax = { kRegister_eax_Code };
114 const Register ecx = { kRegister_ecx_Code };
115 const Register edx = { kRegister_edx_Code };
116 const Register ebx = { kRegister_ebx_Code };
117 const Register esp = { kRegister_esp_Code };
118 const Register ebp = { kRegister_ebp_Code };
119 const Register esi = { kRegister_esi_Code };
120 const Register edi = { kRegister_edi_Code };
121 const Register no_reg = { kRegister_no_reg_Code };
124 inline const char* Register::AllocationIndexToString(int index) {
125 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
126 // This is the mapping of allocation indices to registers.
127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
128 return kNames[index];
132 inline int Register::ToAllocationIndex(Register reg) {
133 DCHECK(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
138 inline Register Register::FromAllocationIndex(int index) {
139 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
140 return (index >= 4) ? from_code(index + 2) : from_code(index);
145 static const int kMaxNumAllocatableRegisters = 7;
146 static const int kMaxNumRegisters = 8;
147 static int NumAllocatableRegisters() {
148 return kMaxNumAllocatableRegisters;
151 // TODO(turbofan): Proper support for float32.
152 static int NumAllocatableAliasedRegisters() {
153 return NumAllocatableRegisters();
156 static int ToAllocationIndex(XMMRegister reg) {
157 DCHECK(reg.code() != 0);
158 return reg.code() - 1;
161 static XMMRegister FromAllocationIndex(int index) {
162 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
163 return from_code(index + 1);
166 static XMMRegister from_code(int code) {
167 XMMRegister result = { code };
171 bool is_valid() const {
172 return 0 <= code_ && code_ < kMaxNumRegisters;
180 bool is(XMMRegister reg) const { return code_ == reg.code_; }
182 static const char* AllocationIndexToString(int index) {
183 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
184 const char* const names[] = {
200 typedef XMMRegister DoubleRegister;
201 typedef XMMRegister SIMD128Register;
203 const XMMRegister xmm0 = { 0 };
204 const XMMRegister xmm1 = { 1 };
205 const XMMRegister xmm2 = { 2 };
206 const XMMRegister xmm3 = { 3 };
207 const XMMRegister xmm4 = { 4 };
208 const XMMRegister xmm5 = { 5 };
209 const XMMRegister xmm6 = { 6 };
210 const XMMRegister xmm7 = { 7 };
211 const XMMRegister no_xmm_reg = { -1 };
215 // any value < 0 is considered no_condition
237 not_carry = above_equal,
239 not_zero = not_equal,
245 // Returns the equivalent of !cc.
246 // Negation of the default no_condition (-1) results in a non-default
247 // no_condition value (-2). As long as tests for no_condition check
248 // for condition < 0, this will work as expected.
249 inline Condition NegateCondition(Condition cc) {
250 return static_cast<Condition>(cc ^ 1);
254 // Commute a condition such that {a cond b == b cond' a}.
255 inline Condition CommuteCondition(Condition cc) {
272 return greater_equal;
279 // -----------------------------------------------------------------------------
280 // Machine instruction Immediates
282 class Immediate BASE_EMBEDDED {
284 inline explicit Immediate(int x);
285 inline explicit Immediate(const ExternalReference& ext);
286 inline explicit Immediate(Handle<Object> handle);
287 inline explicit Immediate(Smi* value);
288 inline explicit Immediate(Address addr);
290 static Immediate CodeRelativeOffset(Label* label) {
291 return Immediate(label);
294 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
295 bool is_int8() const {
296 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
298 bool is_int16() const {
299 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
303 inline explicit Immediate(Label* value);
306 RelocInfo::Mode rmode_;
308 friend class Operand;
309 friend class Assembler;
310 friend class MacroAssembler;
314 // -----------------------------------------------------------------------------
315 // Machine instruction Operands
322 maximal_scale_factor = times_8,
323 times_int_size = times_4,
324 times_half_pointer_size = times_2,
325 times_pointer_size = times_4,
326 times_twice_pointer_size = times_8
330 class Operand BASE_EMBEDDED {
333 INLINE(explicit Operand(Register reg));
336 INLINE(explicit Operand(XMMRegister xmm_reg));
339 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
342 INLINE(explicit Operand(Immediate imm));
345 explicit Operand(Register base, int32_t disp,
346 RelocInfo::Mode rmode = RelocInfo::NONE32);
348 // [base + index*scale + disp/r]
349 explicit Operand(Register base,
353 RelocInfo::Mode rmode = RelocInfo::NONE32);
355 // [index*scale + disp/r]
356 explicit Operand(Register index,
359 RelocInfo::Mode rmode = RelocInfo::NONE32);
361 // Offset from existing memory operand.
362 // Offset is added to existing displacement as 32-bit signed values and
363 // this must not overflow.
364 Operand(const Operand& base, int32_t offset);
366 static Operand StaticVariable(const ExternalReference& ext) {
367 return Operand(reinterpret_cast<int32_t>(ext.address()),
368 RelocInfo::EXTERNAL_REFERENCE);
371 static Operand StaticArray(Register index,
373 const ExternalReference& arr) {
374 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
375 RelocInfo::EXTERNAL_REFERENCE);
378 static Operand ForCell(Handle<Cell> cell) {
379 AllowDeferredHandleDereference embedding_raw_address;
380 return Operand(reinterpret_cast<int32_t>(cell.location()),
384 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
385 return Operand(base, imm.x_, imm.rmode_);
388 // Returns true if this Operand is a wrapper for the specified register.
389 bool is_reg(Register reg) const;
391 // Returns true if this Operand is a wrapper for one register.
392 bool is_reg_only() const;
394 // Asserts that this Operand is a wrapper for one register and returns the
396 Register reg() const;
399 // Set the ModRM byte without an encoded 'reg' register. The
400 // register is encoded later as part of the emit_operand operation.
401 inline void set_modrm(int mod, Register rm);
403 inline void set_sib(ScaleFactor scale, Register index, Register base);
404 inline void set_disp8(int8_t disp);
405 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
408 // The number of bytes in buf_.
410 // Only valid if len_ > 4.
411 RelocInfo::Mode rmode_;
413 friend class Assembler;
414 friend class MacroAssembler;
418 // -----------------------------------------------------------------------------
419 // A Displacement describes the 32bit immediate field of an instruction which
420 // may be used together with a Label in order to refer to a yet unknown code
421 // position. Displacements stored in the instruction stream are used to describe
422 // the instruction and to chain a list of instructions using the same Label.
423 // A Displacement contains 2 different fields:
425 // next field: position of next displacement in the chain (0 = end of list)
426 // type field: instruction type
428 // A next value of null (0) indicates the end of a chain (note that there can
429 // be no displacement at position zero, because there is always at least one
430 // instruction byte before the displacement).
432 // Displacement _data field layout
434 // |31.....2|1......0|
437 class Displacement BASE_EMBEDDED {
445 int data() const { return data_; }
446 Type type() const { return TypeField::decode(data_); }
447 void next(Label* L) const {
448 int n = NextField::decode(data_);
449 n > 0 ? L->link_to(n) : L->Unuse();
451 void link_to(Label* L) { init(L, type()); }
453 explicit Displacement(int data) { data_ = data; }
455 Displacement(Label* L, Type type) { init(L, type); }
458 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
459 NextField::decode(data_));
465 class TypeField: public BitField<Type, 0, 2> {};
466 class NextField: public BitField<int, 2, 32-2> {};
468 void init(Label* L, Type type);
472 class Assembler : public AssemblerBase {
474 // We check before assembling an instruction that there is sufficient
475 // space to write an instruction and its relocation information.
476 // The relocation writer's position must be kGap bytes above the end of
477 // the generated instructions. This leaves enough space for the
478 // longest possible ia32 instruction, 15 bytes, and the longest possible
479 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
480 // (There is a 15 byte limit on ia32 instruction length that rules out some
481 // otherwise valid instructions.)
482 // This allows for a single, fast space check per instruction.
483 static const int kGap = 32;
486 // Create an assembler. Instructions and relocation information are emitted
487 // into a buffer, with the instructions starting from the beginning and the
488 // relocation information starting from the end of the buffer. See CodeDesc
489 // for a detailed comment on the layout (globals.h).
491 // If the provided buffer is NULL, the assembler allocates and grows its own
492 // buffer, and buffer_size determines the initial buffer size. The buffer is
493 // owned by the assembler and deallocated upon destruction of the assembler.
495 // If the provided buffer is not NULL, the assembler uses the provided buffer
496 // for code generation and assumes its size to be buffer_size. If the buffer
497 // is too small, a fatal error occurs. No deallocation of the buffer is done
498 // upon destruction of the assembler.
499 // TODO(vitalyr): the assembler does not need an isolate.
500 Assembler(Isolate* isolate, void* buffer, int buffer_size);
501 virtual ~Assembler() { }
503 // GetCode emits any pending (non-emitted) code and fills the descriptor
504 // desc. GetCode() is idempotent; it returns the same result if no other
505 // Assembler functions are invoked in between GetCode() calls.
506 void GetCode(CodeDesc* desc);
508 // Read/Modify the code target in the branch/call instruction at pc.
509 inline static Address target_address_at(Address pc,
510 ConstantPoolArray* constant_pool);
511 inline static void set_target_address_at(Address pc,
512 ConstantPoolArray* constant_pool,
514 ICacheFlushMode icache_flush_mode =
515 FLUSH_ICACHE_IF_NEEDED);
516 static inline Address target_address_at(Address pc, Code* code) {
517 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
518 return target_address_at(pc, constant_pool);
520 static inline void set_target_address_at(Address pc,
523 ICacheFlushMode icache_flush_mode =
524 FLUSH_ICACHE_IF_NEEDED) {
525 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
526 set_target_address_at(pc, constant_pool, target);
529 // Return the code target address at a call site from the return address
530 // of that call in the instruction stream.
531 inline static Address target_address_from_return_address(Address pc);
533 // Return the code target address of the patch debug break slot
534 inline static Address break_address_from_return_address(Address pc);
536 // This sets the branch destination (which is in the instruction on x86).
537 // This is for calls and branches within generated code.
538 inline static void deserialization_set_special_target_at(
539 Address instruction_payload, Code* code, Address target) {
540 set_target_address_at(instruction_payload, code, target);
543 static const int kSpecialTargetSize = kPointerSize;
545 // Distance between the address of the code target in the call instruction
546 // and the return address
547 static const int kCallTargetAddressOffset = kPointerSize;
548 // Distance between start of patched return sequence and the emitted address
550 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
552 // Distance between start of patched debug break slot and the emitted address
554 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
556 static const int kCallInstructionLength = 5;
557 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
558 static const int kJSReturnSequenceLength = 6;
560 // The debug break slot must be able to contain a call instruction.
561 static const int kDebugBreakSlotLength = kCallInstructionLength;
563 // One byte opcode for test al, 0xXX.
564 static const byte kTestAlByte = 0xA8;
565 // One byte opcode for nop.
566 static const byte kNopByte = 0x90;
568 // One byte opcode for a short unconditional jump.
569 static const byte kJmpShortOpcode = 0xEB;
570 // One byte prefix for a short conditional jump.
571 static const byte kJccShortPrefix = 0x70;
572 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
573 static const byte kJcShortOpcode = kJccShortPrefix | carry;
574 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
575 static const byte kJzShortOpcode = kJccShortPrefix | zero;
578 // ---------------------------------------------------------------------------
581 // - function names correspond one-to-one to ia32 instruction mnemonics
582 // - unless specified otherwise, instructions operate on 32bit operands
583 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
584 // - instructions on 16bit (word) operands/registers have a trailing '_w'
585 // - naming conflicts with C++ keywords are resolved via a trailing '_'
587 // NOTE ON INTERFACE: Currently, the interface is not very consistent
588 // in the sense that some operations (e.g. mov()) can be called in more
589 // the one way to generate the same instruction: The Register argument
590 // can in some cases be replaced with an Operand(Register) argument.
591 // This should be cleaned up and made more orthogonal. The questions
592 // is: should we always use Operands instead of Registers where an
593 // Operand is possible, or should we have a Register (overloaded) form
594 // instead? We must be careful to make sure that the selected instruction
595 // is obvious from the parameters to avoid hard-to-find code generation
598 // Insert the smallest number of nop instructions
599 // possible to align the pc offset to a multiple
600 // of m. m must be a power of 2.
602 void Nop(int bytes = 1);
603 // Aligns code to something that's optimal for a jump target for the platform.
604 void CodeTargetAlign();
613 void push(const Immediate& x);
614 void push_imm32(int32_t imm32);
615 void push(Register src);
616 void push(const Operand& src);
618 void pop(Register dst);
619 void pop(const Operand& dst);
621 void enter(const Immediate& size);
625 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
626 void mov_b(Register dst, const Operand& src);
627 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
628 void mov_b(const Operand& dst, int8_t imm8);
629 void mov_b(const Operand& dst, Register src);
631 void mov_w(Register dst, const Operand& src);
632 void mov_w(const Operand& dst, Register src);
633 void mov_w(const Operand& dst, int16_t imm16);
635 void mov(Register dst, int32_t imm32);
636 void mov(Register dst, const Immediate& x);
637 void mov(Register dst, Handle<Object> handle);
638 void mov(Register dst, const Operand& src);
639 void mov(Register dst, Register src);
640 void mov(const Operand& dst, const Immediate& x);
641 void mov(const Operand& dst, Handle<Object> handle);
642 void mov(const Operand& dst, Register src);
644 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
645 void movsx_b(Register dst, const Operand& src);
647 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
648 void movsx_w(Register dst, const Operand& src);
650 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
651 void movzx_b(Register dst, const Operand& src);
653 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
654 void movzx_w(Register dst, const Operand& src);
657 void cmov(Condition cc, Register dst, Register src) {
658 cmov(cc, dst, Operand(src));
660 void cmov(Condition cc, Register dst, const Operand& src);
665 // Repetitive string instructions.
671 void xchg(Register dst, Register src);
672 void xchg(Register dst, const Operand& src);
675 void adc(Register dst, int32_t imm32);
676 void adc(Register dst, const Operand& src);
678 void add(Register dst, Register src) { add(dst, Operand(src)); }
679 void add(Register dst, const Operand& src);
680 void add(const Operand& dst, Register src);
681 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
682 void add(const Operand& dst, const Immediate& x);
684 void and_(Register dst, int32_t imm32);
685 void and_(Register dst, const Immediate& x);
686 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
687 void and_(Register dst, const Operand& src);
688 void and_(const Operand& dst, Register src);
689 void and_(const Operand& dst, const Immediate& x);
691 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
692 void cmpb(const Operand& op, int8_t imm8);
693 void cmpb(Register reg, const Operand& op);
694 void cmpb(const Operand& op, Register reg);
695 void cmpb_al(const Operand& op);
696 void cmpw_ax(const Operand& op);
697 void cmpw(const Operand& op, Immediate imm16);
698 void cmp(Register reg, int32_t imm32);
699 void cmp(Register reg, Handle<Object> handle);
700 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
701 void cmp(Register reg, const Operand& op);
702 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
703 void cmp(const Operand& op, const Immediate& imm);
704 void cmp(const Operand& op, Handle<Object> handle);
706 void dec_b(Register dst);
707 void dec_b(const Operand& dst);
709 void dec(Register dst);
710 void dec(const Operand& dst);
714 void idiv(Register src) { idiv(Operand(src)); }
715 void idiv(const Operand& src);
716 void div(Register src) { div(Operand(src)); }
717 void div(const Operand& src);
719 // Signed multiply instructions.
720 void imul(Register src); // edx:eax = eax * src.
721 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
722 void imul(Register dst, const Operand& src); // dst = dst * src.
723 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
724 void imul(Register dst, const Operand& src, int32_t imm32);
726 void inc(Register dst);
727 void inc(const Operand& dst);
729 void lea(Register dst, const Operand& src);
731 // Unsigned multiply instruction.
732 void mul(Register src); // edx:eax = eax * reg.
734 void neg(Register dst);
735 void neg(const Operand& dst);
737 void not_(Register dst);
738 void not_(const Operand& dst);
740 void or_(Register dst, int32_t imm32);
741 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
742 void or_(Register dst, const Operand& src);
743 void or_(const Operand& dst, Register src);
744 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
745 void or_(const Operand& dst, const Immediate& x);
747 void rcl(Register dst, uint8_t imm8);
748 void rcr(Register dst, uint8_t imm8);
750 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
751 void ror(const Operand& dst, uint8_t imm8);
752 void ror_cl(Register dst) { ror_cl(Operand(dst)); }
753 void ror_cl(const Operand& dst);
755 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
756 void sar(const Operand& dst, uint8_t imm8);
757 void sar_cl(Register dst) { sar_cl(Operand(dst)); }
758 void sar_cl(const Operand& dst);
760 void sbb(Register dst, const Operand& src);
762 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
763 void shld(Register dst, const Operand& src);
765 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
766 void shl(const Operand& dst, uint8_t imm8);
767 void shl_cl(Register dst) { shl_cl(Operand(dst)); }
768 void shl_cl(const Operand& dst);
770 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
771 void shrd(Register dst, const Operand& src);
773 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
774 void shr(const Operand& dst, uint8_t imm8);
775 void shr_cl(Register dst) { shr_cl(Operand(dst)); }
776 void shr_cl(const Operand& dst);
778 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
779 void sub(const Operand& dst, const Immediate& x);
780 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
781 void sub(Register dst, const Operand& src);
782 void sub(const Operand& dst, Register src);
784 void test(Register reg, const Immediate& imm);
785 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
786 void test(Register reg, const Operand& op);
787 void test_b(Register reg, const Operand& op);
788 void test(const Operand& op, const Immediate& imm);
789 void test_b(Register reg, uint8_t imm8);
790 void test_b(const Operand& op, uint8_t imm8);
792 void xor_(Register dst, int32_t imm32);
793 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
794 void xor_(Register dst, const Operand& src);
795 void xor_(const Operand& dst, Register src);
796 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
797 void xor_(const Operand& dst, const Immediate& x);
800 void bt(const Operand& dst, Register src);
801 void bts(Register dst, Register src) { bts(Operand(dst), src); }
802 void bts(const Operand& dst, Register src);
803 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
804 void bsr(Register dst, const Operand& src);
812 // Label operations & relative jumps (PPUM Appendix D)
814 // Takes a branch opcode (cc) and a label (L) and generates
815 // either a backward branch or a forward branch and links it
816 // to the label fixup chain. Usage:
818 // Label L; // unbound label
819 // j(cc, &L); // forward branch to unbound label
820 // bind(&L); // bind label to the current pc
821 // j(cc, &L); // backward branch to bound label
822 // bind(&L); // illegal: a label may be bound only once
824 // Note: The same Label can be used for forward and backward branches
825 // but it may be bound only once.
827 void bind(Label* L); // binds an unbound label L to the current code position
831 void call(byte* entry, RelocInfo::Mode rmode);
832 int CallSize(const Operand& adr);
833 void call(Register reg) { call(Operand(reg)); }
834 void call(const Operand& adr);
835 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
836 void call(Handle<Code> code,
837 RelocInfo::Mode rmode,
838 TypeFeedbackId id = TypeFeedbackId::None());
841 // unconditional jump to L
842 void jmp(Label* L, Label::Distance distance = Label::kFar);
843 void jmp(byte* entry, RelocInfo::Mode rmode);
844 void jmp(Register reg) { jmp(Operand(reg)); }
845 void jmp(const Operand& adr);
846 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
851 Label::Distance distance = Label::kFar);
852 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
853 void j(Condition cc, Handle<Code> code);
855 // Floating-point operations
864 void fld_s(const Operand& adr);
865 void fld_d(const Operand& adr);
867 void fstp_s(const Operand& adr);
868 void fst_s(const Operand& adr);
869 void fstp_d(const Operand& adr);
870 void fst_d(const Operand& adr);
872 void fild_s(const Operand& adr);
873 void fild_d(const Operand& adr);
875 void fist_s(const Operand& adr);
877 void fistp_s(const Operand& adr);
878 void fistp_d(const Operand& adr);
880 // The fisttp instructions require SSE3.
881 void fisttp_s(const Operand& adr);
882 void fisttp_d(const Operand& adr);
903 void fisub_s(const Operand& adr);
905 void faddp(int i = 1);
906 void fsubp(int i = 1);
907 void fsubrp(int i = 1);
908 void fmulp(int i = 1);
909 void fdivp(int i = 1);
913 void fxch(int i = 1);
915 void ffree(int i = 0);
930 void setcc(Condition cc, Register reg);
935 void movaps(XMMRegister dst, XMMRegister src);
936 void movlhps(XMMRegister dst, XMMRegister src);
937 void movhlps(XMMRegister dst, XMMRegister src);
938 void movups(XMMRegister dst, const Operand& src);
939 void movups(const Operand& dst, XMMRegister src);
940 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
941 void shufpd(XMMRegister dst, XMMRegister src, byte imm8);
943 void andps(XMMRegister dst, const Operand& src);
944 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
945 void xorps(XMMRegister dst, const Operand& src);
946 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
947 void orps(XMMRegister dst, const Operand& src);
948 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
950 void addps(XMMRegister dst, const Operand& src);
951 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
952 void subps(XMMRegister dst, const Operand& src);
953 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
954 void mulps(XMMRegister dst, const Operand& src);
955 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
956 void divps(XMMRegister dst, const Operand& src);
957 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
958 void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
959 void minps(XMMRegister dst, const Operand& src);
960 void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
961 void maxps(XMMRegister dst, const Operand& src);
962 void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
963 void rcpps(XMMRegister dst, const Operand& src);
964 void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
965 void rsqrtps(XMMRegister dst, const Operand& src);
966 void sqrtps(XMMRegister dst, XMMRegister src) { sqrtps(dst, Operand(src)); }
967 void sqrtps(XMMRegister dst, const Operand& src);
968 void sqrtpd(XMMRegister dst, XMMRegister src) { sqrtpd(dst, Operand(src)); }
969 void sqrtpd(XMMRegister dst, const Operand& src);
971 void addpd(XMMRegister dst, const Operand& src);
972 void addpd(XMMRegister dst, XMMRegister src) { addpd(dst, Operand(src)); }
973 void subpd(XMMRegister dst, const Operand& src);
974 void subpd(XMMRegister dst, XMMRegister src) { subpd(dst, Operand(src)); }
975 void mulpd(XMMRegister dst, const Operand& src);
976 void mulpd(XMMRegister dst, XMMRegister src) { mulpd(dst, Operand(src)); }
977 void divpd(XMMRegister dst, const Operand& src);
978 void divpd(XMMRegister dst, XMMRegister src) { divpd(dst, Operand(src)); }
979 void minpd(XMMRegister dst, XMMRegister src) { minpd(dst, Operand(src)); }
980 void minpd(XMMRegister dst, const Operand& src);
981 void maxpd(XMMRegister dst, XMMRegister src) { maxpd(dst, Operand(src)); }
982 void maxpd(XMMRegister dst, const Operand& src);
984 void cvtdq2ps(XMMRegister dst, const Operand& src);
985 void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
986 void cmpeqps(XMMRegister dst, XMMRegister src);
987 void cmpltps(XMMRegister dst, XMMRegister src);
988 void cmpleps(XMMRegister dst, XMMRegister src);
989 void cmpneqps(XMMRegister dst, XMMRegister src);
990 void cmpnltps(XMMRegister dst, XMMRegister src);
991 void cmpnleps(XMMRegister dst, XMMRegister src);
993 // SSE 2, introduced by SIMD
994 void paddd(XMMRegister dst, XMMRegister src) { paddd(dst, Operand(src)); }
995 void paddd(XMMRegister dst, const Operand& src);
996 void psubd(XMMRegister dst, XMMRegister src) { psubd(dst, Operand(src)); }
997 void psubd(XMMRegister dst, const Operand& src);
998 void pmuludq(XMMRegister dst, XMMRegister src) { pmuludq(dst, Operand(src)); }
999 void pmuludq(XMMRegister dst, const Operand& src);
1000 void punpackldq(XMMRegister dst, XMMRegister src) {
1001 punpackldq(dst, Operand(src));
1003 void punpackldq(XMMRegister dst, const Operand& src);
1004 void cvtps2dq(XMMRegister dst, XMMRegister src) {
1005 cvtps2dq(dst, Operand(src));
1007 void cvtps2dq(XMMRegister dst, const Operand& src);
1008 void cvtdq2ps(XMMRegister dst, XMMRegister src) {
1009 cvtdq2ps(dst, Operand(src));
1011 // SSE 4.1, introduced by SIMD
1012 void insertps(XMMRegister dst, XMMRegister src, byte imm8);
1013 void pmulld(XMMRegister dst, XMMRegister src) { pmulld(dst, Operand(src)); }
1014 void pmulld(XMMRegister dst, const Operand& src);
1016 // SSE2 instructions
1017 void cvttss2si(Register dst, const Operand& src);
1018 void cvttss2si(Register dst, XMMRegister src) {
1019 cvttss2si(dst, Operand(src));
1021 void cvttsd2si(Register dst, const Operand& src);
1022 void cvttsd2si(Register dst, XMMRegister src) {
1023 cvttsd2si(dst, Operand(src));
1025 void cvtsd2si(Register dst, XMMRegister src);
1027 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
1028 void cvtsi2sd(XMMRegister dst, const Operand& src);
1029 void cvtss2sd(XMMRegister dst, const Operand& src);
1030 void cvtss2sd(XMMRegister dst, XMMRegister src) {
1031 cvtss2sd(dst, Operand(src));
1033 void cvtsd2ss(XMMRegister dst, const Operand& src);
1034 void cvtsd2ss(XMMRegister dst, XMMRegister src) {
1035 cvtsd2ss(dst, Operand(src));
1037 void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); }
1038 void addsd(XMMRegister dst, const Operand& src);
1039 void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); }
1040 void subsd(XMMRegister dst, const Operand& src);
1041 void mulsd(XMMRegister dst, XMMRegister src) { mulsd(dst, Operand(src)); }
1042 void mulsd(XMMRegister dst, const Operand& src);
1043 void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); }
1044 void divsd(XMMRegister dst, const Operand& src);
1045 void xorpd(XMMRegister dst, XMMRegister src);
1046 void xorpd(XMMRegister dst, const Operand& src);
1047 void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); }
1048 void sqrtsd(XMMRegister dst, const Operand& src);
1050 void andpd(XMMRegister dst, XMMRegister src);
1051 void andpd(XMMRegister dst, const Operand& src);
1052 void orpd(XMMRegister dst, XMMRegister src);
1054 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
1055 void ucomisd(XMMRegister dst, const Operand& src);
1058 kRoundToNearest = 0x0,
1064 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1066 void movmskpd(Register dst, XMMRegister src);
1067 void movmskps(Register dst, XMMRegister src);
1069 void cmpltsd(XMMRegister dst, XMMRegister src);
1070 void pcmpeqd(XMMRegister dst, XMMRegister src);
1071 void pcmpgtd(XMMRegister dst, XMMRegister src);
1073 void movdqa(XMMRegister dst, const Operand& src);
1074 void movdqa(const Operand& dst, XMMRegister src);
1075 void movdqu(XMMRegister dst, const Operand& src);
1076 void movdqu(const Operand& dst, XMMRegister src);
1077 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
1085 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
1086 void movd(XMMRegister dst, const Operand& src);
1087 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
1088 void movd(const Operand& dst, XMMRegister src);
1089 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
1090 void movsd(XMMRegister dst, const Operand& src);
1091 void movsd(const Operand& dst, XMMRegister src);
1094 void movss(XMMRegister dst, const Operand& src);
1095 void movss(const Operand& dst, XMMRegister src);
1096 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
1097 void movq(XMMRegister dst, const Operand& src);
1098 void movq(const Operand& dst, XMMRegister src);
1099 void extractps(Register dst, XMMRegister src, byte imm8);
1101 void pand(XMMRegister dst, XMMRegister src);
1102 void pxor(XMMRegister dst, XMMRegister src);
1103 void por(XMMRegister dst, XMMRegister src);
1104 void ptest(XMMRegister dst, XMMRegister src);
1106 void pslld(XMMRegister reg, int8_t shift);
1107 void psrld(XMMRegister reg, int8_t shift);
1108 void psllq(XMMRegister reg, int8_t shift);
1109 void psllq(XMMRegister dst, XMMRegister src);
1110 void pslld(XMMRegister dst, XMMRegister src);
1111 void psrld(XMMRegister dst, XMMRegister src);
1112 void psrad(XMMRegister reg, int8_t shift);
1113 void psrad(XMMRegister dst, XMMRegister src);
1114 void psrlq(XMMRegister reg, int8_t shift);
1115 void psrlq(XMMRegister dst, XMMRegister src);
1116 void psrldq(XMMRegister dst, int8_t shift);
1117 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1118 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1119 pextrd(Operand(dst), src, offset);
1121 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1122 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1123 pinsrd(dst, Operand(src), offset);
1125 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1127 // Parallel XMM operations.
1128 void movntdqa(XMMRegister dst, const Operand& src);
1129 void movntdq(const Operand& dst, XMMRegister src);
1130 // Prefetch src position into cache level.
1131 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1133 void prefetch(const Operand& src, int level);
1134 // TODO(lrn): Need SFENCE for movnt?
1136 // Check the code size generated from label to here.
1137 int SizeOfCodeGeneratedSince(Label* label) {
1138 return pc_offset() - label->pos();
1141 // Mark address of the ExitJSFrame code.
1142 void RecordJSReturn();
1144 // Mark address of a debug break slot.
1145 void RecordDebugBreakSlot();
1147 // Record a comment relocation entry that can be used by a disassembler.
1148 // Use --code-comments to enable, or provide "force = true" flag to always
1150 void RecordComment(const char* msg, bool force = false);
1152 // Writes a single byte or word of data in the code stream. Used for
1153 // inline tables, e.g., jump-tables.
1154 void db(uint8_t data);
1155 void dd(uint32_t data);
1157 // Check if there is less than kGap bytes available in the buffer.
1158 // If this is the case, we need to grow the buffer before emitting
1159 // an instruction or relocation information.
1160 inline bool buffer_overflow() const {
1161 return pc_ >= reloc_info_writer.pos() - kGap;
1164 // Get the number of bytes available in the buffer.
1165 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1167 static bool IsNop(Address addr);
1169 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1171 int relocation_writer_size() {
1172 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1175 // Avoid overflows for displacements etc.
1176 static const int kMaximalBufferSize = 512*MB;
1178 byte byte_at(int pos) { return buffer_[pos]; }
1179 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1181 // Allocate a constant pool of the correct size for the generated code.
1182 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1184 // Generate the constant pool for the generated code.
1185 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1188 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1189 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1190 void emit_sse_operand(Register dst, XMMRegister src);
1191 void emit_sse_operand(XMMRegister dst, Register src);
1193 byte* addr_at(int pos) { return buffer_ + pos; }
1197 uint32_t long_at(int pos) {
1198 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1200 void long_at_put(int pos, uint32_t x) {
1201 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1206 inline void emit(uint32_t x);
1207 inline void emit(Handle<Object> handle);
1208 inline void emit(uint32_t x,
1209 RelocInfo::Mode rmode,
1210 TypeFeedbackId id = TypeFeedbackId::None());
1211 inline void emit(Handle<Code> code,
1212 RelocInfo::Mode rmode,
1213 TypeFeedbackId id = TypeFeedbackId::None());
1214 inline void emit(const Immediate& x);
1215 inline void emit_w(const Immediate& x);
1217 // Emit the code-object-relative offset of the label's position
1218 inline void emit_code_relative_offset(Label* label);
1220 // instruction generation
1221 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1223 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1224 // with a given destination expression and an immediate operand. It attempts
1225 // to use the shortest encoding possible.
1226 // sel specifies the /n in the modrm byte (see the Intel PRM).
1227 void emit_arith(int sel, Operand dst, const Immediate& x);
1229 void emit_operand(Register reg, const Operand& adr);
1231 void emit_farith(int b1, int b2, int i);
1234 void print(Label* L);
1235 void bind_to(Label* L, int pos);
1238 inline Displacement disp_at(Label* L);
1239 inline void disp_at_put(Label* L, Displacement disp);
1240 inline void emit_disp(Label* L, Displacement::Type type);
1241 inline void emit_near_disp(Label* L);
1243 // record reloc info for current pc_
1244 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1246 friend class CodePatcher;
1247 friend class EnsureSpace;
1250 RelocInfoWriter reloc_info_writer;
1252 PositionsRecorder positions_recorder_;
1253 friend class PositionsRecorder;
1257 // Helper class that ensures that there is enough space for generating
1258 // instructions and relocation information. The constructor makes
1259 // sure that there is enough space and (in debug mode) the destructor
1260 // checks that we did not generate too much.
1261 class EnsureSpace BASE_EMBEDDED {
1263 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1264 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1266 space_before_ = assembler_->available_space();
1272 int bytes_generated = space_before_ - assembler_->available_space();
1273 DCHECK(bytes_generated < assembler_->kGap);
1278 Assembler* assembler_;
1284 } } // namespace v8::internal
1286 #endif // V8_IA32_ASSEMBLER_IA32_H_