1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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9 // this list of conditions and the following disclaimer.
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
40 #include "src/isolate.h"
41 #include "src/serialize.h"
48 // 1) We would prefer to use an enum, but enum values are assignment-
49 // compatible with int, which has caused code-generation bugs.
51 // 2) We would prefer to use a class instead of a struct but we don't like
52 // the register initialization to depend on the particular initialization
53 // order (which appears to be different on OS X, Linux, and Windows for the
54 // installed versions of C++ we tried). Using a struct permits C-style
55 // "initialization". Also, the Register objects cannot be const as this
56 // forces initialization stubs in MSVC, making us dependent on initialization
59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code.
68 static const int kMaxNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
72 static const int kNumRegisters = 8;
74 static inline const char* AllocationIndexToString(int index);
76 static inline int ToAllocationIndex(Register reg);
78 static inline Register FromAllocationIndex(int index);
80 static Register from_code(int code) {
82 ASSERT(code < kNumRegisters);
83 Register r = { code };
86 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
87 bool is(Register reg) const { return code_ == reg.code_; }
88 // eax, ebx, ecx and edx are byte registers, the rest are not.
89 bool is_byte_register() const { return code_ <= 3; }
99 // Unfortunately we can't make this private in a struct.
103 const int kRegister_eax_Code = 0;
104 const int kRegister_ecx_Code = 1;
105 const int kRegister_edx_Code = 2;
106 const int kRegister_ebx_Code = 3;
107 const int kRegister_esp_Code = 4;
108 const int kRegister_ebp_Code = 5;
109 const int kRegister_esi_Code = 6;
110 const int kRegister_edi_Code = 7;
111 const int kRegister_no_reg_Code = -1;
113 const Register eax = { kRegister_eax_Code };
114 const Register ecx = { kRegister_ecx_Code };
115 const Register edx = { kRegister_edx_Code };
116 const Register ebx = { kRegister_ebx_Code };
117 const Register esp = { kRegister_esp_Code };
118 const Register ebp = { kRegister_ebp_Code };
119 const Register esi = { kRegister_esi_Code };
120 const Register edi = { kRegister_edi_Code };
121 const Register no_reg = { kRegister_no_reg_Code };
124 inline const char* Register::AllocationIndexToString(int index) {
125 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
126 // This is the mapping of allocation indices to registers.
127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
128 return kNames[index];
132 inline int Register::ToAllocationIndex(Register reg) {
133 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
138 inline Register Register::FromAllocationIndex(int index) {
139 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
140 return (index >= 4) ? from_code(index + 2) : from_code(index);
145 static const int kMaxNumAllocatableRegisters = 7;
146 static const int kMaxNumRegisters = 8;
147 static int NumAllocatableRegisters() {
148 return kMaxNumAllocatableRegisters;
151 static int ToAllocationIndex(XMMRegister reg) {
152 ASSERT(reg.code() != 0);
153 return reg.code() - 1;
156 static XMMRegister FromAllocationIndex(int index) {
157 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
158 return from_code(index + 1);
161 static XMMRegister from_code(int code) {
162 XMMRegister result = { code };
166 bool is_valid() const {
167 return 0 <= code_ && code_ < kMaxNumRegisters;
175 bool is(XMMRegister reg) const { return code_ == reg.code_; }
177 static const char* AllocationIndexToString(int index) {
178 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
179 const char* const names[] = {
195 typedef XMMRegister DoubleRegister;
198 const XMMRegister xmm0 = { 0 };
199 const XMMRegister xmm1 = { 1 };
200 const XMMRegister xmm2 = { 2 };
201 const XMMRegister xmm3 = { 3 };
202 const XMMRegister xmm4 = { 4 };
203 const XMMRegister xmm5 = { 5 };
204 const XMMRegister xmm6 = { 6 };
205 const XMMRegister xmm7 = { 7 };
206 const XMMRegister no_xmm_reg = { -1 };
210 // any value < 0 is considered no_condition
232 not_carry = above_equal,
234 not_zero = not_equal,
240 // Returns the equivalent of !cc.
241 // Negation of the default no_condition (-1) results in a non-default
242 // no_condition value (-2). As long as tests for no_condition check
243 // for condition < 0, this will work as expected.
244 inline Condition NegateCondition(Condition cc) {
245 return static_cast<Condition>(cc ^ 1);
249 // Commute a condition such that {a cond b == b cond' a}.
250 inline Condition CommuteCondition(Condition cc) {
267 return greater_equal;
274 // -----------------------------------------------------------------------------
275 // Machine instruction Immediates
277 class Immediate BASE_EMBEDDED {
279 inline explicit Immediate(int x);
280 inline explicit Immediate(const ExternalReference& ext);
281 inline explicit Immediate(Handle<Object> handle);
282 inline explicit Immediate(Smi* value);
283 inline explicit Immediate(Address addr);
285 static Immediate CodeRelativeOffset(Label* label) {
286 return Immediate(label);
289 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
290 bool is_int8() const {
291 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
293 bool is_int16() const {
294 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
298 inline explicit Immediate(Label* value);
301 RelocInfo::Mode rmode_;
303 friend class Assembler;
304 friend class MacroAssembler;
308 // -----------------------------------------------------------------------------
309 // Machine instruction Operands
316 times_int_size = times_4,
317 times_half_pointer_size = times_2,
318 times_pointer_size = times_4,
319 times_twice_pointer_size = times_8
323 class Operand BASE_EMBEDDED {
326 INLINE(explicit Operand(XMMRegister xmm_reg));
329 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
330 // disp only must always be relocated
333 explicit Operand(Register base, int32_t disp,
334 RelocInfo::Mode rmode = RelocInfo::NONE32);
336 // [base + index*scale + disp/r]
337 explicit Operand(Register base,
341 RelocInfo::Mode rmode = RelocInfo::NONE32);
343 // [index*scale + disp/r]
344 explicit Operand(Register index,
347 RelocInfo::Mode rmode = RelocInfo::NONE32);
349 static Operand StaticVariable(const ExternalReference& ext) {
350 return Operand(reinterpret_cast<int32_t>(ext.address()),
351 RelocInfo::EXTERNAL_REFERENCE);
354 static Operand StaticArray(Register index,
356 const ExternalReference& arr) {
357 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
358 RelocInfo::EXTERNAL_REFERENCE);
361 static Operand ForCell(Handle<Cell> cell) {
362 AllowDeferredHandleDereference embedding_raw_address;
363 return Operand(reinterpret_cast<int32_t>(cell.location()),
367 // Returns true if this Operand is a wrapper for the specified register.
368 bool is_reg(Register reg) const;
370 // Returns true if this Operand is a wrapper for one register.
371 bool is_reg_only() const;
373 // Asserts that this Operand is a wrapper for one register and returns the
375 Register reg() const;
379 INLINE(explicit Operand(Register reg));
381 // Set the ModRM byte without an encoded 'reg' register. The
382 // register is encoded later as part of the emit_operand operation.
383 inline void set_modrm(int mod, Register rm);
385 inline void set_sib(ScaleFactor scale, Register index, Register base);
386 inline void set_disp8(int8_t disp);
387 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
390 // The number of bytes in buf_.
392 // Only valid if len_ > 4.
393 RelocInfo::Mode rmode_;
395 friend class Assembler;
396 friend class MacroAssembler;
397 friend class LCodeGen;
401 // -----------------------------------------------------------------------------
402 // A Displacement describes the 32bit immediate field of an instruction which
403 // may be used together with a Label in order to refer to a yet unknown code
404 // position. Displacements stored in the instruction stream are used to describe
405 // the instruction and to chain a list of instructions using the same Label.
406 // A Displacement contains 2 different fields:
408 // next field: position of next displacement in the chain (0 = end of list)
409 // type field: instruction type
411 // A next value of null (0) indicates the end of a chain (note that there can
412 // be no displacement at position zero, because there is always at least one
413 // instruction byte before the displacement).
415 // Displacement _data field layout
417 // |31.....2|1......0|
420 class Displacement BASE_EMBEDDED {
428 int data() const { return data_; }
429 Type type() const { return TypeField::decode(data_); }
430 void next(Label* L) const {
431 int n = NextField::decode(data_);
432 n > 0 ? L->link_to(n) : L->Unuse();
434 void link_to(Label* L) { init(L, type()); }
436 explicit Displacement(int data) { data_ = data; }
438 Displacement(Label* L, Type type) { init(L, type); }
441 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
442 NextField::decode(data_));
448 class TypeField: public BitField<Type, 0, 2> {};
449 class NextField: public BitField<int, 2, 32-2> {};
451 void init(Label* L, Type type);
455 class Assembler : public AssemblerBase {
457 // We check before assembling an instruction that there is sufficient
458 // space to write an instruction and its relocation information.
459 // The relocation writer's position must be kGap bytes above the end of
460 // the generated instructions. This leaves enough space for the
461 // longest possible ia32 instruction, 15 bytes, and the longest possible
462 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
463 // (There is a 15 byte limit on ia32 instruction length that rules out some
464 // otherwise valid instructions.)
465 // This allows for a single, fast space check per instruction.
466 static const int kGap = 32;
469 // Create an assembler. Instructions and relocation information are emitted
470 // into a buffer, with the instructions starting from the beginning and the
471 // relocation information starting from the end of the buffer. See CodeDesc
472 // for a detailed comment on the layout (globals.h).
474 // If the provided buffer is NULL, the assembler allocates and grows its own
475 // buffer, and buffer_size determines the initial buffer size. The buffer is
476 // owned by the assembler and deallocated upon destruction of the assembler.
478 // If the provided buffer is not NULL, the assembler uses the provided buffer
479 // for code generation and assumes its size to be buffer_size. If the buffer
480 // is too small, a fatal error occurs. No deallocation of the buffer is done
481 // upon destruction of the assembler.
482 // TODO(vitalyr): the assembler does not need an isolate.
483 Assembler(Isolate* isolate, void* buffer, int buffer_size);
484 virtual ~Assembler() { }
486 // GetCode emits any pending (non-emitted) code and fills the descriptor
487 // desc. GetCode() is idempotent; it returns the same result if no other
488 // Assembler functions are invoked in between GetCode() calls.
489 void GetCode(CodeDesc* desc);
491 // Read/Modify the code target in the branch/call instruction at pc.
492 inline static Address target_address_at(Address pc,
493 ConstantPoolArray* constant_pool);
494 inline static void set_target_address_at(Address pc,
495 ConstantPoolArray* constant_pool,
497 ICacheFlushMode icache_flush_mode =
498 FLUSH_ICACHE_IF_NEEDED);
499 static inline Address target_address_at(Address pc, Code* code) {
500 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
501 return target_address_at(pc, constant_pool);
503 static inline void set_target_address_at(Address pc,
506 ICacheFlushMode icache_flush_mode =
507 FLUSH_ICACHE_IF_NEEDED) {
508 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
509 set_target_address_at(pc, constant_pool, target);
512 // Return the code target address at a call site from the return address
513 // of that call in the instruction stream.
514 inline static Address target_address_from_return_address(Address pc);
516 // This sets the branch destination (which is in the instruction on x86).
517 // This is for calls and branches within generated code.
518 inline static void deserialization_set_special_target_at(
519 Address instruction_payload, Code* code, Address target) {
520 set_target_address_at(instruction_payload, code, target);
523 static const int kSpecialTargetSize = kPointerSize;
525 // Distance between the address of the code target in the call instruction
526 // and the return address
527 static const int kCallTargetAddressOffset = kPointerSize;
528 // Distance between start of patched return sequence and the emitted address
530 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
532 // Distance between start of patched debug break slot and the emitted address
534 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
536 static const int kCallInstructionLength = 5;
537 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
538 static const int kJSReturnSequenceLength = 6;
540 // The debug break slot must be able to contain a call instruction.
541 static const int kDebugBreakSlotLength = kCallInstructionLength;
543 // One byte opcode for test al, 0xXX.
544 static const byte kTestAlByte = 0xA8;
545 // One byte opcode for nop.
546 static const byte kNopByte = 0x90;
548 // One byte opcode for a short unconditional jump.
549 static const byte kJmpShortOpcode = 0xEB;
550 // One byte prefix for a short conditional jump.
551 static const byte kJccShortPrefix = 0x70;
552 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
553 static const byte kJcShortOpcode = kJccShortPrefix | carry;
554 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
555 static const byte kJzShortOpcode = kJccShortPrefix | zero;
558 // ---------------------------------------------------------------------------
561 // - function names correspond one-to-one to ia32 instruction mnemonics
562 // - unless specified otherwise, instructions operate on 32bit operands
563 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
564 // - instructions on 16bit (word) operands/registers have a trailing '_w'
565 // - naming conflicts with C++ keywords are resolved via a trailing '_'
567 // NOTE ON INTERFACE: Currently, the interface is not very consistent
568 // in the sense that some operations (e.g. mov()) can be called in more
569 // the one way to generate the same instruction: The Register argument
570 // can in some cases be replaced with an Operand(Register) argument.
571 // This should be cleaned up and made more orthogonal. The questions
572 // is: should we always use Operands instead of Registers where an
573 // Operand is possible, or should we have a Register (overloaded) form
574 // instead? We must be careful to make sure that the selected instruction
575 // is obvious from the parameters to avoid hard-to-find code generation
578 // Insert the smallest number of nop instructions
579 // possible to align the pc offset to a multiple
580 // of m. m must be a power of 2.
582 void Nop(int bytes = 1);
583 // Aligns code to something that's optimal for a jump target for the platform.
584 void CodeTargetAlign();
593 void push(const Immediate& x);
594 void push_imm32(int32_t imm32);
595 void push(Register src);
596 void push(const Operand& src);
598 void pop(Register dst);
599 void pop(const Operand& dst);
601 void enter(const Immediate& size);
605 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
606 void mov_b(Register dst, const Operand& src);
607 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
608 void mov_b(const Operand& dst, int8_t imm8);
609 void mov_b(const Operand& dst, Register src);
611 void mov_w(Register dst, const Operand& src);
612 void mov_w(const Operand& dst, Register src);
613 void mov_w(const Operand& dst, int16_t imm16);
615 void mov(Register dst, int32_t imm32);
616 void mov(Register dst, const Immediate& x);
617 void mov(Register dst, Handle<Object> handle);
618 void mov(Register dst, const Operand& src);
619 void mov(Register dst, Register src);
620 void mov(const Operand& dst, const Immediate& x);
621 void mov(const Operand& dst, Handle<Object> handle);
622 void mov(const Operand& dst, Register src);
624 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
625 void movsx_b(Register dst, const Operand& src);
627 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
628 void movsx_w(Register dst, const Operand& src);
630 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
631 void movzx_b(Register dst, const Operand& src);
633 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
634 void movzx_w(Register dst, const Operand& src);
637 void cmov(Condition cc, Register dst, Register src) {
638 cmov(cc, dst, Operand(src));
640 void cmov(Condition cc, Register dst, const Operand& src);
645 // Repetitive string instructions.
650 // Exchange two registers
651 void xchg(Register dst, Register src);
654 void adc(Register dst, int32_t imm32);
655 void adc(Register dst, const Operand& src);
657 void add(Register dst, Register src) { add(dst, Operand(src)); }
658 void add(Register dst, const Operand& src);
659 void add(const Operand& dst, Register src);
660 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
661 void add(const Operand& dst, const Immediate& x);
663 void and_(Register dst, int32_t imm32);
664 void and_(Register dst, const Immediate& x);
665 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
666 void and_(Register dst, const Operand& src);
667 void and_(const Operand& dst, Register src);
668 void and_(const Operand& dst, const Immediate& x);
670 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
671 void cmpb(const Operand& op, int8_t imm8);
672 void cmpb(Register reg, const Operand& op);
673 void cmpb(const Operand& op, Register reg);
674 void cmpb_al(const Operand& op);
675 void cmpw_ax(const Operand& op);
676 void cmpw(const Operand& op, Immediate imm16);
677 void cmp(Register reg, int32_t imm32);
678 void cmp(Register reg, Handle<Object> handle);
679 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
680 void cmp(Register reg, const Operand& op);
681 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
682 void cmp(const Operand& op, const Immediate& imm);
683 void cmp(const Operand& op, Handle<Object> handle);
685 void dec_b(Register dst);
686 void dec_b(const Operand& dst);
688 void dec(Register dst);
689 void dec(const Operand& dst);
693 void idiv(Register src);
695 // Signed multiply instructions.
696 void imul(Register src); // edx:eax = eax * src.
697 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
698 void imul(Register dst, const Operand& src); // dst = dst * src.
699 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
701 void inc(Register dst);
702 void inc(const Operand& dst);
704 void lea(Register dst, const Operand& src);
706 // Unsigned multiply instruction.
707 void mul(Register src); // edx:eax = eax * reg.
709 void neg(Register dst);
711 void not_(Register dst);
713 void or_(Register dst, int32_t imm32);
714 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
715 void or_(Register dst, const Operand& src);
716 void or_(const Operand& dst, Register src);
717 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
718 void or_(const Operand& dst, const Immediate& x);
720 void rcl(Register dst, uint8_t imm8);
721 void rcr(Register dst, uint8_t imm8);
722 void ror(Register dst, uint8_t imm8);
723 void ror_cl(Register dst);
725 void sar(Register dst, uint8_t imm8);
726 void sar_cl(Register dst);
728 void sbb(Register dst, const Operand& src);
730 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
731 void shld(Register dst, const Operand& src);
733 void shl(Register dst, uint8_t imm8);
734 void shl_cl(Register dst);
736 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
737 void shrd(Register dst, const Operand& src);
739 void shr(Register dst, uint8_t imm8);
740 void shr_cl(Register dst);
742 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
743 void sub(const Operand& dst, const Immediate& x);
744 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
745 void sub(Register dst, const Operand& src);
746 void sub(const Operand& dst, Register src);
748 void test(Register reg, const Immediate& imm);
749 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
750 void test(Register reg, const Operand& op);
751 void test_b(Register reg, const Operand& op);
752 void test(const Operand& op, const Immediate& imm);
753 void test_b(Register reg, uint8_t imm8);
754 void test_b(const Operand& op, uint8_t imm8);
756 void xor_(Register dst, int32_t imm32);
757 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
758 void xor_(Register dst, const Operand& src);
759 void xor_(const Operand& dst, Register src);
760 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
761 void xor_(const Operand& dst, const Immediate& x);
764 void bt(const Operand& dst, Register src);
765 void bts(Register dst, Register src) { bts(Operand(dst), src); }
766 void bts(const Operand& dst, Register src);
767 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
768 void bsr(Register dst, const Operand& src);
776 // Label operations & relative jumps (PPUM Appendix D)
778 // Takes a branch opcode (cc) and a label (L) and generates
779 // either a backward branch or a forward branch and links it
780 // to the label fixup chain. Usage:
782 // Label L; // unbound label
783 // j(cc, &L); // forward branch to unbound label
784 // bind(&L); // bind label to the current pc
785 // j(cc, &L); // backward branch to bound label
786 // bind(&L); // illegal: a label may be bound only once
788 // Note: The same Label can be used for forward and backward branches
789 // but it may be bound only once.
791 void bind(Label* L); // binds an unbound label L to the current code position
795 void call(byte* entry, RelocInfo::Mode rmode);
796 int CallSize(const Operand& adr);
797 void call(Register reg) { call(Operand(reg)); }
798 void call(const Operand& adr);
799 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
800 void call(Handle<Code> code,
801 RelocInfo::Mode rmode,
802 TypeFeedbackId id = TypeFeedbackId::None());
805 // unconditional jump to L
806 void jmp(Label* L, Label::Distance distance = Label::kFar);
807 void jmp(byte* entry, RelocInfo::Mode rmode);
808 void jmp(Register reg) { jmp(Operand(reg)); }
809 void jmp(const Operand& adr);
810 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
815 Label::Distance distance = Label::kFar);
816 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
817 void j(Condition cc, Handle<Code> code);
819 // Floating-point operations
828 void fld_s(const Operand& adr);
829 void fld_d(const Operand& adr);
831 void fstp_s(const Operand& adr);
832 void fst_s(const Operand& adr);
833 void fstp_d(const Operand& adr);
834 void fst_d(const Operand& adr);
836 void fild_s(const Operand& adr);
837 void fild_d(const Operand& adr);
839 void fist_s(const Operand& adr);
841 void fistp_s(const Operand& adr);
842 void fistp_d(const Operand& adr);
844 // The fisttp instructions require SSE3.
845 void fisttp_s(const Operand& adr);
846 void fisttp_d(const Operand& adr);
867 void fisub_s(const Operand& adr);
869 void faddp(int i = 1);
870 void fsubp(int i = 1);
871 void fsubrp(int i = 1);
872 void fmulp(int i = 1);
873 void fdivp(int i = 1);
877 void fxch(int i = 1);
879 void ffree(int i = 0);
894 void setcc(Condition cc, Register reg);
899 void movaps(XMMRegister dst, XMMRegister src);
900 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
902 void andps(XMMRegister dst, const Operand& src);
903 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
904 void xorps(XMMRegister dst, const Operand& src);
905 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
906 void orps(XMMRegister dst, const Operand& src);
907 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
909 void addps(XMMRegister dst, const Operand& src);
910 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
911 void subps(XMMRegister dst, const Operand& src);
912 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
913 void mulps(XMMRegister dst, const Operand& src);
914 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
915 void divps(XMMRegister dst, const Operand& src);
916 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
919 void cvttss2si(Register dst, const Operand& src);
920 void cvttss2si(Register dst, XMMRegister src) {
921 cvttss2si(dst, Operand(src));
923 void cvttsd2si(Register dst, const Operand& src);
924 void cvtsd2si(Register dst, XMMRegister src);
926 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
927 void cvtsi2sd(XMMRegister dst, const Operand& src);
928 void cvtss2sd(XMMRegister dst, XMMRegister src);
929 void cvtsd2ss(XMMRegister dst, XMMRegister src);
931 void addsd(XMMRegister dst, XMMRegister src);
932 void addsd(XMMRegister dst, const Operand& src);
933 void subsd(XMMRegister dst, XMMRegister src);
934 void mulsd(XMMRegister dst, XMMRegister src);
935 void mulsd(XMMRegister dst, const Operand& src);
936 void divsd(XMMRegister dst, XMMRegister src);
937 void xorpd(XMMRegister dst, XMMRegister src);
938 void sqrtsd(XMMRegister dst, XMMRegister src);
939 void sqrtsd(XMMRegister dst, const Operand& src);
941 void andpd(XMMRegister dst, XMMRegister src);
942 void orpd(XMMRegister dst, XMMRegister src);
944 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
945 void ucomisd(XMMRegister dst, const Operand& src);
948 kRoundToNearest = 0x0,
954 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
956 void movmskpd(Register dst, XMMRegister src);
957 void movmskps(Register dst, XMMRegister src);
959 void cmpltsd(XMMRegister dst, XMMRegister src);
960 void pcmpeqd(XMMRegister dst, XMMRegister src);
962 void movdqa(XMMRegister dst, const Operand& src);
963 void movdqa(const Operand& dst, XMMRegister src);
964 void movdqu(XMMRegister dst, const Operand& src);
965 void movdqu(const Operand& dst, XMMRegister src);
966 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
974 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
975 void movd(XMMRegister dst, const Operand& src);
976 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
977 void movd(const Operand& dst, XMMRegister src);
978 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
979 void movsd(XMMRegister dst, const Operand& src);
980 void movsd(const Operand& dst, XMMRegister src);
983 void movss(XMMRegister dst, const Operand& src);
984 void movss(const Operand& dst, XMMRegister src);
985 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
986 void extractps(Register dst, XMMRegister src, byte imm8);
988 void pand(XMMRegister dst, XMMRegister src);
989 void pxor(XMMRegister dst, XMMRegister src);
990 void por(XMMRegister dst, XMMRegister src);
991 void ptest(XMMRegister dst, XMMRegister src);
993 void psllq(XMMRegister reg, int8_t shift);
994 void psllq(XMMRegister dst, XMMRegister src);
995 void psrlq(XMMRegister reg, int8_t shift);
996 void psrlq(XMMRegister dst, XMMRegister src);
997 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
998 void pextrd(Register dst, XMMRegister src, int8_t offset) {
999 pextrd(Operand(dst), src, offset);
1001 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1002 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1003 pinsrd(dst, Operand(src), offset);
1005 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1007 // Parallel XMM operations.
1008 void movntdqa(XMMRegister dst, const Operand& src);
1009 void movntdq(const Operand& dst, XMMRegister src);
1010 // Prefetch src position into cache level.
1011 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1013 void prefetch(const Operand& src, int level);
1014 // TODO(lrn): Need SFENCE for movnt?
1019 // Check the code size generated from label to here.
1020 int SizeOfCodeGeneratedSince(Label* label) {
1021 return pc_offset() - label->pos();
1024 // Mark address of the ExitJSFrame code.
1025 void RecordJSReturn();
1027 // Mark address of a debug break slot.
1028 void RecordDebugBreakSlot();
1030 // Record a comment relocation entry that can be used by a disassembler.
1031 // Use --code-comments to enable, or provide "force = true" flag to always
1033 void RecordComment(const char* msg, bool force = false);
1035 // Writes a single byte or word of data in the code stream. Used for
1036 // inline tables, e.g., jump-tables.
1037 void db(uint8_t data);
1038 void dd(uint32_t data);
1040 // Check if there is less than kGap bytes available in the buffer.
1041 // If this is the case, we need to grow the buffer before emitting
1042 // an instruction or relocation information.
1043 inline bool buffer_overflow() const {
1044 return pc_ >= reloc_info_writer.pos() - kGap;
1047 // Get the number of bytes available in the buffer.
1048 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1050 static bool IsNop(Address addr);
1052 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1054 int relocation_writer_size() {
1055 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1058 // Avoid overflows for displacements etc.
1059 static const int kMaximalBufferSize = 512*MB;
1061 byte byte_at(int pos) { return buffer_[pos]; }
1062 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1064 // Allocate a constant pool of the correct size for the generated code.
1065 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1067 // Generate the constant pool for the generated code.
1068 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1071 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1072 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1073 void emit_sse_operand(Register dst, XMMRegister src);
1074 void emit_sse_operand(XMMRegister dst, Register src);
1076 byte* addr_at(int pos) { return buffer_ + pos; }
1080 uint32_t long_at(int pos) {
1081 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1083 void long_at_put(int pos, uint32_t x) {
1084 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1089 inline void emit(uint32_t x);
1090 inline void emit(Handle<Object> handle);
1091 inline void emit(uint32_t x,
1092 RelocInfo::Mode rmode,
1093 TypeFeedbackId id = TypeFeedbackId::None());
1094 inline void emit(Handle<Code> code,
1095 RelocInfo::Mode rmode,
1096 TypeFeedbackId id = TypeFeedbackId::None());
1097 inline void emit(const Immediate& x);
1098 inline void emit_w(const Immediate& x);
1100 // Emit the code-object-relative offset of the label's position
1101 inline void emit_code_relative_offset(Label* label);
1103 // instruction generation
1104 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1106 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1107 // with a given destination expression and an immediate operand. It attempts
1108 // to use the shortest encoding possible.
1109 // sel specifies the /n in the modrm byte (see the Intel PRM).
1110 void emit_arith(int sel, Operand dst, const Immediate& x);
1112 void emit_operand(Register reg, const Operand& adr);
1114 void emit_farith(int b1, int b2, int i);
1117 void print(Label* L);
1118 void bind_to(Label* L, int pos);
1121 inline Displacement disp_at(Label* L);
1122 inline void disp_at_put(Label* L, Displacement disp);
1123 inline void emit_disp(Label* L, Displacement::Type type);
1124 inline void emit_near_disp(Label* L);
1126 // record reloc info for current pc_
1127 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1129 friend class CodePatcher;
1130 friend class EnsureSpace;
1133 RelocInfoWriter reloc_info_writer;
1135 PositionsRecorder positions_recorder_;
1136 friend class PositionsRecorder;
1140 // Helper class that ensures that there is enough space for generating
1141 // instructions and relocation information. The constructor makes
1142 // sure that there is enough space and (in debug mode) the destructor
1143 // checks that we did not generate too much.
1144 class EnsureSpace BASE_EMBEDDED {
1146 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1147 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1149 space_before_ = assembler_->available_space();
1155 int bytes_generated = space_before_ - assembler_->available_space();
1156 ASSERT(bytes_generated < assembler_->kGap);
1161 Assembler* assembler_;
1167 } } // namespace v8::internal
1169 #endif // V8_IA32_ASSEMBLER_IA32_H_