1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
40 #include "src/isolate.h"
41 #include "src/serialize.h"
48 // 1) We would prefer to use an enum, but enum values are assignment-
49 // compatible with int, which has caused code-generation bugs.
51 // 2) We would prefer to use a class instead of a struct but we don't like
52 // the register initialization to depend on the particular initialization
53 // order (which appears to be different on OS X, Linux, and Windows for the
54 // installed versions of C++ we tried). Using a struct permits C-style
55 // "initialization". Also, the Register objects cannot be const as this
56 // forces initialization stubs in MSVC, making us dependent on initialization
59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code.
68 static const int kMaxNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
72 static const int kNumRegisters = 8;
74 static inline const char* AllocationIndexToString(int index);
76 static inline int ToAllocationIndex(Register reg);
78 static inline Register FromAllocationIndex(int index);
80 static Register from_code(int code) {
82 DCHECK(code < kNumRegisters);
83 Register r = { code };
86 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
87 bool is(Register reg) const { return code_ == reg.code_; }
88 // eax, ebx, ecx and edx are byte registers, the rest are not.
89 bool is_byte_register() const { return code_ <= 3; }
99 // Unfortunately we can't make this private in a struct.
103 const int kRegister_eax_Code = 0;
104 const int kRegister_ecx_Code = 1;
105 const int kRegister_edx_Code = 2;
106 const int kRegister_ebx_Code = 3;
107 const int kRegister_esp_Code = 4;
108 const int kRegister_ebp_Code = 5;
109 const int kRegister_esi_Code = 6;
110 const int kRegister_edi_Code = 7;
111 const int kRegister_no_reg_Code = -1;
113 const Register eax = { kRegister_eax_Code };
114 const Register ecx = { kRegister_ecx_Code };
115 const Register edx = { kRegister_edx_Code };
116 const Register ebx = { kRegister_ebx_Code };
117 const Register esp = { kRegister_esp_Code };
118 const Register ebp = { kRegister_ebp_Code };
119 const Register esi = { kRegister_esi_Code };
120 const Register edi = { kRegister_edi_Code };
121 const Register no_reg = { kRegister_no_reg_Code };
124 inline const char* Register::AllocationIndexToString(int index) {
125 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
126 // This is the mapping of allocation indices to registers.
127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
128 return kNames[index];
132 inline int Register::ToAllocationIndex(Register reg) {
133 DCHECK(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
138 inline Register Register::FromAllocationIndex(int index) {
139 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
140 return (index >= 4) ? from_code(index + 2) : from_code(index);
145 static const int kMaxNumAllocatableRegisters = 7;
146 static const int kMaxNumRegisters = 8;
147 static int NumAllocatableRegisters() {
148 return kMaxNumAllocatableRegisters;
151 // TODO(turbofan): Proper support for float32.
152 static int NumAllocatableAliasedRegisters() {
153 return NumAllocatableRegisters();
156 static int ToAllocationIndex(XMMRegister reg) {
157 DCHECK(reg.code() != 0);
158 return reg.code() - 1;
161 static XMMRegister FromAllocationIndex(int index) {
162 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
163 return from_code(index + 1);
166 static XMMRegister from_code(int code) {
167 XMMRegister result = { code };
171 bool is_valid() const {
172 return 0 <= code_ && code_ < kMaxNumRegisters;
180 bool is(XMMRegister reg) const { return code_ == reg.code_; }
182 static const char* AllocationIndexToString(int index) {
183 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
184 const char* const names[] = {
200 typedef XMMRegister DoubleRegister;
203 const XMMRegister xmm0 = { 0 };
204 const XMMRegister xmm1 = { 1 };
205 const XMMRegister xmm2 = { 2 };
206 const XMMRegister xmm3 = { 3 };
207 const XMMRegister xmm4 = { 4 };
208 const XMMRegister xmm5 = { 5 };
209 const XMMRegister xmm6 = { 6 };
210 const XMMRegister xmm7 = { 7 };
211 const XMMRegister no_xmm_reg = { -1 };
215 // any value < 0 is considered no_condition
237 not_carry = above_equal,
239 not_zero = not_equal,
245 // Returns the equivalent of !cc.
246 // Negation of the default no_condition (-1) results in a non-default
247 // no_condition value (-2). As long as tests for no_condition check
248 // for condition < 0, this will work as expected.
249 inline Condition NegateCondition(Condition cc) {
250 return static_cast<Condition>(cc ^ 1);
254 // Commute a condition such that {a cond b == b cond' a}.
255 inline Condition CommuteCondition(Condition cc) {
272 return greater_equal;
279 // -----------------------------------------------------------------------------
280 // Machine instruction Immediates
282 class Immediate BASE_EMBEDDED {
284 inline explicit Immediate(int x);
285 inline explicit Immediate(const ExternalReference& ext);
286 inline explicit Immediate(Handle<Object> handle);
287 inline explicit Immediate(Smi* value);
288 inline explicit Immediate(Address addr);
290 static Immediate CodeRelativeOffset(Label* label) {
291 return Immediate(label);
294 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
295 bool is_int8() const {
296 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
298 bool is_int16() const {
299 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
303 inline explicit Immediate(Label* value);
306 RelocInfo::Mode rmode_;
308 friend class Operand;
309 friend class Assembler;
310 friend class MacroAssembler;
314 // -----------------------------------------------------------------------------
315 // Machine instruction Operands
322 times_int_size = times_4,
323 times_half_pointer_size = times_2,
324 times_pointer_size = times_4,
325 times_twice_pointer_size = times_8
329 class Operand BASE_EMBEDDED {
332 INLINE(explicit Operand(Register reg));
335 INLINE(explicit Operand(XMMRegister xmm_reg));
338 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
341 INLINE(explicit Operand(Immediate imm));
344 explicit Operand(Register base, int32_t disp,
345 RelocInfo::Mode rmode = RelocInfo::NONE32);
347 // [base + index*scale + disp/r]
348 explicit Operand(Register base,
352 RelocInfo::Mode rmode = RelocInfo::NONE32);
354 // [index*scale + disp/r]
355 explicit Operand(Register index,
358 RelocInfo::Mode rmode = RelocInfo::NONE32);
360 static Operand StaticVariable(const ExternalReference& ext) {
361 return Operand(reinterpret_cast<int32_t>(ext.address()),
362 RelocInfo::EXTERNAL_REFERENCE);
365 static Operand StaticArray(Register index,
367 const ExternalReference& arr) {
368 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
369 RelocInfo::EXTERNAL_REFERENCE);
372 static Operand ForCell(Handle<Cell> cell) {
373 AllowDeferredHandleDereference embedding_raw_address;
374 return Operand(reinterpret_cast<int32_t>(cell.location()),
378 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
379 return Operand(base, imm.x_, imm.rmode_);
382 // Returns true if this Operand is a wrapper for the specified register.
383 bool is_reg(Register reg) const;
385 // Returns true if this Operand is a wrapper for one register.
386 bool is_reg_only() const;
388 // Asserts that this Operand is a wrapper for one register and returns the
390 Register reg() const;
393 // Set the ModRM byte without an encoded 'reg' register. The
394 // register is encoded later as part of the emit_operand operation.
395 inline void set_modrm(int mod, Register rm);
397 inline void set_sib(ScaleFactor scale, Register index, Register base);
398 inline void set_disp8(int8_t disp);
399 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
402 // The number of bytes in buf_.
404 // Only valid if len_ > 4.
405 RelocInfo::Mode rmode_;
407 friend class Assembler;
408 friend class MacroAssembler;
412 // -----------------------------------------------------------------------------
413 // A Displacement describes the 32bit immediate field of an instruction which
414 // may be used together with a Label in order to refer to a yet unknown code
415 // position. Displacements stored in the instruction stream are used to describe
416 // the instruction and to chain a list of instructions using the same Label.
417 // A Displacement contains 2 different fields:
419 // next field: position of next displacement in the chain (0 = end of list)
420 // type field: instruction type
422 // A next value of null (0) indicates the end of a chain (note that there can
423 // be no displacement at position zero, because there is always at least one
424 // instruction byte before the displacement).
426 // Displacement _data field layout
428 // |31.....2|1......0|
431 class Displacement BASE_EMBEDDED {
439 int data() const { return data_; }
440 Type type() const { return TypeField::decode(data_); }
441 void next(Label* L) const {
442 int n = NextField::decode(data_);
443 n > 0 ? L->link_to(n) : L->Unuse();
445 void link_to(Label* L) { init(L, type()); }
447 explicit Displacement(int data) { data_ = data; }
449 Displacement(Label* L, Type type) { init(L, type); }
452 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
453 NextField::decode(data_));
459 class TypeField: public BitField<Type, 0, 2> {};
460 class NextField: public BitField<int, 2, 32-2> {};
462 void init(Label* L, Type type);
466 class Assembler : public AssemblerBase {
468 // We check before assembling an instruction that there is sufficient
469 // space to write an instruction and its relocation information.
470 // The relocation writer's position must be kGap bytes above the end of
471 // the generated instructions. This leaves enough space for the
472 // longest possible ia32 instruction, 15 bytes, and the longest possible
473 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
474 // (There is a 15 byte limit on ia32 instruction length that rules out some
475 // otherwise valid instructions.)
476 // This allows for a single, fast space check per instruction.
477 static const int kGap = 32;
480 // Create an assembler. Instructions and relocation information are emitted
481 // into a buffer, with the instructions starting from the beginning and the
482 // relocation information starting from the end of the buffer. See CodeDesc
483 // for a detailed comment on the layout (globals.h).
485 // If the provided buffer is NULL, the assembler allocates and grows its own
486 // buffer, and buffer_size determines the initial buffer size. The buffer is
487 // owned by the assembler and deallocated upon destruction of the assembler.
489 // If the provided buffer is not NULL, the assembler uses the provided buffer
490 // for code generation and assumes its size to be buffer_size. If the buffer
491 // is too small, a fatal error occurs. No deallocation of the buffer is done
492 // upon destruction of the assembler.
493 // TODO(vitalyr): the assembler does not need an isolate.
494 Assembler(Isolate* isolate, void* buffer, int buffer_size);
495 virtual ~Assembler() { }
497 // GetCode emits any pending (non-emitted) code and fills the descriptor
498 // desc. GetCode() is idempotent; it returns the same result if no other
499 // Assembler functions are invoked in between GetCode() calls.
500 void GetCode(CodeDesc* desc);
502 // Read/Modify the code target in the branch/call instruction at pc.
503 inline static Address target_address_at(Address pc,
504 ConstantPoolArray* constant_pool);
505 inline static void set_target_address_at(Address pc,
506 ConstantPoolArray* constant_pool,
508 ICacheFlushMode icache_flush_mode =
509 FLUSH_ICACHE_IF_NEEDED);
510 static inline Address target_address_at(Address pc, Code* code) {
511 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
512 return target_address_at(pc, constant_pool);
514 static inline void set_target_address_at(Address pc,
517 ICacheFlushMode icache_flush_mode =
518 FLUSH_ICACHE_IF_NEEDED) {
519 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
520 set_target_address_at(pc, constant_pool, target);
523 // Return the code target address at a call site from the return address
524 // of that call in the instruction stream.
525 inline static Address target_address_from_return_address(Address pc);
527 // Return the code target address of the patch debug break slot
528 inline static Address break_address_from_return_address(Address pc);
530 // This sets the branch destination (which is in the instruction on x86).
531 // This is for calls and branches within generated code.
532 inline static void deserialization_set_special_target_at(
533 Address instruction_payload, Code* code, Address target) {
534 set_target_address_at(instruction_payload, code, target);
537 static const int kSpecialTargetSize = kPointerSize;
539 // Distance between the address of the code target in the call instruction
540 // and the return address
541 static const int kCallTargetAddressOffset = kPointerSize;
542 // Distance between start of patched return sequence and the emitted address
544 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
546 // Distance between start of patched debug break slot and the emitted address
548 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
550 static const int kCallInstructionLength = 5;
551 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
552 static const int kJSReturnSequenceLength = 6;
554 // The debug break slot must be able to contain a call instruction.
555 static const int kDebugBreakSlotLength = kCallInstructionLength;
557 // One byte opcode for test al, 0xXX.
558 static const byte kTestAlByte = 0xA8;
559 // One byte opcode for nop.
560 static const byte kNopByte = 0x90;
562 // One byte opcode for a short unconditional jump.
563 static const byte kJmpShortOpcode = 0xEB;
564 // One byte prefix for a short conditional jump.
565 static const byte kJccShortPrefix = 0x70;
566 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
567 static const byte kJcShortOpcode = kJccShortPrefix | carry;
568 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
569 static const byte kJzShortOpcode = kJccShortPrefix | zero;
572 // ---------------------------------------------------------------------------
575 // - function names correspond one-to-one to ia32 instruction mnemonics
576 // - unless specified otherwise, instructions operate on 32bit operands
577 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
578 // - instructions on 16bit (word) operands/registers have a trailing '_w'
579 // - naming conflicts with C++ keywords are resolved via a trailing '_'
581 // NOTE ON INTERFACE: Currently, the interface is not very consistent
582 // in the sense that some operations (e.g. mov()) can be called in more
583 // the one way to generate the same instruction: The Register argument
584 // can in some cases be replaced with an Operand(Register) argument.
585 // This should be cleaned up and made more orthogonal. The questions
586 // is: should we always use Operands instead of Registers where an
587 // Operand is possible, or should we have a Register (overloaded) form
588 // instead? We must be careful to make sure that the selected instruction
589 // is obvious from the parameters to avoid hard-to-find code generation
592 // Insert the smallest number of nop instructions
593 // possible to align the pc offset to a multiple
594 // of m. m must be a power of 2.
596 void Nop(int bytes = 1);
597 // Aligns code to something that's optimal for a jump target for the platform.
598 void CodeTargetAlign();
607 void push(const Immediate& x);
608 void push_imm32(int32_t imm32);
609 void push(Register src);
610 void push(const Operand& src);
612 void pop(Register dst);
613 void pop(const Operand& dst);
615 void enter(const Immediate& size);
619 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
620 void mov_b(Register dst, const Operand& src);
621 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
622 void mov_b(const Operand& dst, int8_t imm8);
623 void mov_b(const Operand& dst, Register src);
625 void mov_w(Register dst, const Operand& src);
626 void mov_w(const Operand& dst, Register src);
627 void mov_w(const Operand& dst, int16_t imm16);
629 void mov(Register dst, int32_t imm32);
630 void mov(Register dst, const Immediate& x);
631 void mov(Register dst, Handle<Object> handle);
632 void mov(Register dst, const Operand& src);
633 void mov(Register dst, Register src);
634 void mov(const Operand& dst, const Immediate& x);
635 void mov(const Operand& dst, Handle<Object> handle);
636 void mov(const Operand& dst, Register src);
638 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
639 void movsx_b(Register dst, const Operand& src);
641 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
642 void movsx_w(Register dst, const Operand& src);
644 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
645 void movzx_b(Register dst, const Operand& src);
647 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
648 void movzx_w(Register dst, const Operand& src);
651 void cmov(Condition cc, Register dst, Register src) {
652 cmov(cc, dst, Operand(src));
654 void cmov(Condition cc, Register dst, const Operand& src);
659 // Repetitive string instructions.
665 void xchg(Register dst, Register src);
666 void xchg(Register dst, const Operand& src);
669 void adc(Register dst, int32_t imm32);
670 void adc(Register dst, const Operand& src);
672 void add(Register dst, Register src) { add(dst, Operand(src)); }
673 void add(Register dst, const Operand& src);
674 void add(const Operand& dst, Register src);
675 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
676 void add(const Operand& dst, const Immediate& x);
678 void and_(Register dst, int32_t imm32);
679 void and_(Register dst, const Immediate& x);
680 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
681 void and_(Register dst, const Operand& src);
682 void and_(const Operand& dst, Register src);
683 void and_(const Operand& dst, const Immediate& x);
685 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
686 void cmpb(const Operand& op, int8_t imm8);
687 void cmpb(Register reg, const Operand& op);
688 void cmpb(const Operand& op, Register reg);
689 void cmpb_al(const Operand& op);
690 void cmpw_ax(const Operand& op);
691 void cmpw(const Operand& op, Immediate imm16);
692 void cmp(Register reg, int32_t imm32);
693 void cmp(Register reg, Handle<Object> handle);
694 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
695 void cmp(Register reg, const Operand& op);
696 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
697 void cmp(const Operand& op, const Immediate& imm);
698 void cmp(const Operand& op, Handle<Object> handle);
700 void dec_b(Register dst);
701 void dec_b(const Operand& dst);
703 void dec(Register dst);
704 void dec(const Operand& dst);
708 void idiv(Register src) { idiv(Operand(src)); }
709 void idiv(const Operand& src);
710 void div(Register src) { div(Operand(src)); }
711 void div(const Operand& src);
713 // Signed multiply instructions.
714 void imul(Register src); // edx:eax = eax * src.
715 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
716 void imul(Register dst, const Operand& src); // dst = dst * src.
717 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
718 void imul(Register dst, const Operand& src, int32_t imm32);
720 void inc(Register dst);
721 void inc(const Operand& dst);
723 void lea(Register dst, const Operand& src);
725 // Unsigned multiply instruction.
726 void mul(Register src); // edx:eax = eax * reg.
728 void neg(Register dst);
729 void neg(const Operand& dst);
731 void not_(Register dst);
732 void not_(const Operand& dst);
734 void or_(Register dst, int32_t imm32);
735 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
736 void or_(Register dst, const Operand& src);
737 void or_(const Operand& dst, Register src);
738 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
739 void or_(const Operand& dst, const Immediate& x);
741 void rcl(Register dst, uint8_t imm8);
742 void rcr(Register dst, uint8_t imm8);
744 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); }
745 void ror(const Operand& dst, uint8_t imm8);
746 void ror_cl(Register dst) { ror_cl(Operand(dst)); }
747 void ror_cl(const Operand& dst);
749 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
750 void sar(const Operand& dst, uint8_t imm8);
751 void sar_cl(Register dst) { sar_cl(Operand(dst)); }
752 void sar_cl(const Operand& dst);
754 void sbb(Register dst, const Operand& src);
756 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
757 void shld(Register dst, const Operand& src);
759 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
760 void shl(const Operand& dst, uint8_t imm8);
761 void shl_cl(Register dst) { shl_cl(Operand(dst)); }
762 void shl_cl(const Operand& dst);
764 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
765 void shrd(Register dst, const Operand& src);
767 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
768 void shr(const Operand& dst, uint8_t imm8);
769 void shr_cl(Register dst) { shr_cl(Operand(dst)); }
770 void shr_cl(const Operand& dst);
772 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
773 void sub(const Operand& dst, const Immediate& x);
774 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
775 void sub(Register dst, const Operand& src);
776 void sub(const Operand& dst, Register src);
778 void test(Register reg, const Immediate& imm);
779 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
780 void test(Register reg, const Operand& op);
781 void test_b(Register reg, const Operand& op);
782 void test(const Operand& op, const Immediate& imm);
783 void test_b(Register reg, uint8_t imm8);
784 void test_b(const Operand& op, uint8_t imm8);
786 void xor_(Register dst, int32_t imm32);
787 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
788 void xor_(Register dst, const Operand& src);
789 void xor_(const Operand& dst, Register src);
790 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
791 void xor_(const Operand& dst, const Immediate& x);
794 void bt(const Operand& dst, Register src);
795 void bts(Register dst, Register src) { bts(Operand(dst), src); }
796 void bts(const Operand& dst, Register src);
797 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
798 void bsr(Register dst, const Operand& src);
806 // Label operations & relative jumps (PPUM Appendix D)
808 // Takes a branch opcode (cc) and a label (L) and generates
809 // either a backward branch or a forward branch and links it
810 // to the label fixup chain. Usage:
812 // Label L; // unbound label
813 // j(cc, &L); // forward branch to unbound label
814 // bind(&L); // bind label to the current pc
815 // j(cc, &L); // backward branch to bound label
816 // bind(&L); // illegal: a label may be bound only once
818 // Note: The same Label can be used for forward and backward branches
819 // but it may be bound only once.
821 void bind(Label* L); // binds an unbound label L to the current code position
825 void call(byte* entry, RelocInfo::Mode rmode);
826 int CallSize(const Operand& adr);
827 void call(Register reg) { call(Operand(reg)); }
828 void call(const Operand& adr);
829 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
830 void call(Handle<Code> code,
831 RelocInfo::Mode rmode,
832 TypeFeedbackId id = TypeFeedbackId::None());
835 // unconditional jump to L
836 void jmp(Label* L, Label::Distance distance = Label::kFar);
837 void jmp(byte* entry, RelocInfo::Mode rmode);
838 void jmp(Register reg) { jmp(Operand(reg)); }
839 void jmp(const Operand& adr);
840 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
845 Label::Distance distance = Label::kFar);
846 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
847 void j(Condition cc, Handle<Code> code);
849 // Floating-point operations
858 void fld_s(const Operand& adr);
859 void fld_d(const Operand& adr);
861 void fstp_s(const Operand& adr);
862 void fst_s(const Operand& adr);
863 void fstp_d(const Operand& adr);
864 void fst_d(const Operand& adr);
866 void fild_s(const Operand& adr);
867 void fild_d(const Operand& adr);
869 void fist_s(const Operand& adr);
871 void fistp_s(const Operand& adr);
872 void fistp_d(const Operand& adr);
874 // The fisttp instructions require SSE3.
875 void fisttp_s(const Operand& adr);
876 void fisttp_d(const Operand& adr);
897 void fisub_s(const Operand& adr);
899 void faddp(int i = 1);
900 void fsubp(int i = 1);
901 void fsubrp(int i = 1);
902 void fmulp(int i = 1);
903 void fdivp(int i = 1);
907 void fxch(int i = 1);
909 void ffree(int i = 0);
924 void setcc(Condition cc, Register reg);
929 void movaps(XMMRegister dst, XMMRegister src);
930 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
932 void andps(XMMRegister dst, const Operand& src);
933 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
934 void xorps(XMMRegister dst, const Operand& src);
935 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
936 void orps(XMMRegister dst, const Operand& src);
937 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
939 void addps(XMMRegister dst, const Operand& src);
940 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
941 void subps(XMMRegister dst, const Operand& src);
942 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
943 void mulps(XMMRegister dst, const Operand& src);
944 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
945 void divps(XMMRegister dst, const Operand& src);
946 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
949 void cvttss2si(Register dst, const Operand& src);
950 void cvttss2si(Register dst, XMMRegister src) {
951 cvttss2si(dst, Operand(src));
953 void cvttsd2si(Register dst, const Operand& src);
954 void cvttsd2si(Register dst, XMMRegister src) {
955 cvttsd2si(dst, Operand(src));
957 void cvtsd2si(Register dst, XMMRegister src);
959 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
960 void cvtsi2sd(XMMRegister dst, const Operand& src);
961 void cvtss2sd(XMMRegister dst, const Operand& src);
962 void cvtss2sd(XMMRegister dst, XMMRegister src) {
963 cvtss2sd(dst, Operand(src));
965 void cvtsd2ss(XMMRegister dst, const Operand& src);
966 void cvtsd2ss(XMMRegister dst, XMMRegister src) {
967 cvtsd2ss(dst, Operand(src));
969 void addsd(XMMRegister dst, XMMRegister src) { addsd(dst, Operand(src)); }
970 void addsd(XMMRegister dst, const Operand& src);
971 void subsd(XMMRegister dst, XMMRegister src) { subsd(dst, Operand(src)); }
972 void subsd(XMMRegister dst, const Operand& src);
973 void mulsd(XMMRegister dst, XMMRegister src) { mulsd(dst, Operand(src)); }
974 void mulsd(XMMRegister dst, const Operand& src);
975 void divsd(XMMRegister dst, XMMRegister src) { divsd(dst, Operand(src)); }
976 void divsd(XMMRegister dst, const Operand& src);
977 void xorpd(XMMRegister dst, XMMRegister src);
978 void sqrtsd(XMMRegister dst, XMMRegister src) { sqrtsd(dst, Operand(src)); }
979 void sqrtsd(XMMRegister dst, const Operand& src);
981 void andpd(XMMRegister dst, XMMRegister src);
982 void orpd(XMMRegister dst, XMMRegister src);
984 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
985 void ucomisd(XMMRegister dst, const Operand& src);
988 kRoundToNearest = 0x0,
994 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
996 void movmskpd(Register dst, XMMRegister src);
997 void movmskps(Register dst, XMMRegister src);
999 void cmpltsd(XMMRegister dst, XMMRegister src);
1000 void pcmpeqd(XMMRegister dst, XMMRegister src);
1002 void movdqa(XMMRegister dst, const Operand& src);
1003 void movdqa(const Operand& dst, XMMRegister src);
1004 void movdqu(XMMRegister dst, const Operand& src);
1005 void movdqu(const Operand& dst, XMMRegister src);
1006 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
1014 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
1015 void movd(XMMRegister dst, const Operand& src);
1016 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
1017 void movd(const Operand& dst, XMMRegister src);
1018 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
1019 void movsd(XMMRegister dst, const Operand& src);
1020 void movsd(const Operand& dst, XMMRegister src);
1023 void movss(XMMRegister dst, const Operand& src);
1024 void movss(const Operand& dst, XMMRegister src);
1025 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
1026 void extractps(Register dst, XMMRegister src, byte imm8);
1028 void pand(XMMRegister dst, XMMRegister src);
1029 void pxor(XMMRegister dst, XMMRegister src);
1030 void por(XMMRegister dst, XMMRegister src);
1031 void ptest(XMMRegister dst, XMMRegister src);
1033 void pslld(XMMRegister reg, int8_t shift);
1034 void psrld(XMMRegister reg, int8_t shift);
1035 void psllq(XMMRegister reg, int8_t shift);
1036 void psllq(XMMRegister dst, XMMRegister src);
1037 void psrlq(XMMRegister reg, int8_t shift);
1038 void psrlq(XMMRegister dst, XMMRegister src);
1039 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1040 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1041 pextrd(Operand(dst), src, offset);
1043 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1044 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1045 pinsrd(dst, Operand(src), offset);
1047 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1049 // Parallel XMM operations.
1050 void movntdqa(XMMRegister dst, const Operand& src);
1051 void movntdq(const Operand& dst, XMMRegister src);
1052 // Prefetch src position into cache level.
1053 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1055 void prefetch(const Operand& src, int level);
1056 // TODO(lrn): Need SFENCE for movnt?
1058 // Check the code size generated from label to here.
1059 int SizeOfCodeGeneratedSince(Label* label) {
1060 return pc_offset() - label->pos();
1063 // Mark address of the ExitJSFrame code.
1064 void RecordJSReturn();
1066 // Mark address of a debug break slot.
1067 void RecordDebugBreakSlot();
1069 // Record a comment relocation entry that can be used by a disassembler.
1070 // Use --code-comments to enable, or provide "force = true" flag to always
1072 void RecordComment(const char* msg, bool force = false);
1074 // Writes a single byte or word of data in the code stream. Used for
1075 // inline tables, e.g., jump-tables.
1076 void db(uint8_t data);
1077 void dd(uint32_t data);
1079 // Check if there is less than kGap bytes available in the buffer.
1080 // If this is the case, we need to grow the buffer before emitting
1081 // an instruction or relocation information.
1082 inline bool buffer_overflow() const {
1083 return pc_ >= reloc_info_writer.pos() - kGap;
1086 // Get the number of bytes available in the buffer.
1087 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1089 static bool IsNop(Address addr);
1091 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1093 int relocation_writer_size() {
1094 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1097 // Avoid overflows for displacements etc.
1098 static const int kMaximalBufferSize = 512*MB;
1100 byte byte_at(int pos) { return buffer_[pos]; }
1101 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1103 // Allocate a constant pool of the correct size for the generated code.
1104 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1106 // Generate the constant pool for the generated code.
1107 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1110 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1111 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1112 void emit_sse_operand(Register dst, XMMRegister src);
1113 void emit_sse_operand(XMMRegister dst, Register src);
1115 byte* addr_at(int pos) { return buffer_ + pos; }
1119 uint32_t long_at(int pos) {
1120 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1122 void long_at_put(int pos, uint32_t x) {
1123 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1128 inline void emit(uint32_t x);
1129 inline void emit(Handle<Object> handle);
1130 inline void emit(uint32_t x,
1131 RelocInfo::Mode rmode,
1132 TypeFeedbackId id = TypeFeedbackId::None());
1133 inline void emit(Handle<Code> code,
1134 RelocInfo::Mode rmode,
1135 TypeFeedbackId id = TypeFeedbackId::None());
1136 inline void emit(const Immediate& x);
1137 inline void emit_w(const Immediate& x);
1139 // Emit the code-object-relative offset of the label's position
1140 inline void emit_code_relative_offset(Label* label);
1142 // instruction generation
1143 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1145 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1146 // with a given destination expression and an immediate operand. It attempts
1147 // to use the shortest encoding possible.
1148 // sel specifies the /n in the modrm byte (see the Intel PRM).
1149 void emit_arith(int sel, Operand dst, const Immediate& x);
1151 void emit_operand(Register reg, const Operand& adr);
1153 void emit_farith(int b1, int b2, int i);
1156 void print(Label* L);
1157 void bind_to(Label* L, int pos);
1160 inline Displacement disp_at(Label* L);
1161 inline void disp_at_put(Label* L, Displacement disp);
1162 inline void emit_disp(Label* L, Displacement::Type type);
1163 inline void emit_near_disp(Label* L);
1165 // record reloc info for current pc_
1166 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1168 friend class CodePatcher;
1169 friend class EnsureSpace;
1172 RelocInfoWriter reloc_info_writer;
1174 PositionsRecorder positions_recorder_;
1175 friend class PositionsRecorder;
1179 // Helper class that ensures that there is enough space for generating
1180 // instructions and relocation information. The constructor makes
1181 // sure that there is enough space and (in debug mode) the destructor
1182 // checks that we did not generate too much.
1183 class EnsureSpace BASE_EMBEDDED {
1185 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1186 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1188 space_before_ = assembler_->available_space();
1194 int bytes_generated = space_before_ - assembler_->available_space();
1195 DCHECK(bytes_generated < assembler_->kGap);
1200 Assembler* assembler_;
1206 } } // namespace v8::internal
1208 #endif // V8_IA32_ASSEMBLER_IA32_H_