1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
39 #if V8_TARGET_ARCH_IA32
41 #include "disassembler.h"
42 #include "macro-assembler.h"
43 #include "serialize.h"
48 // -----------------------------------------------------------------------------
49 // Implementation of CpuFeatures
52 bool CpuFeatures::initialized_ = false;
54 uint64_t CpuFeatures::supported_ = 0;
55 uint64_t CpuFeatures::found_by_runtime_probing_only_ = 0;
56 uint64_t CpuFeatures::cross_compile_ = 0;
59 ExternalReference ExternalReference::cpu_features() {
60 ASSERT(CpuFeatures::initialized_);
61 return ExternalReference(&CpuFeatures::supported_);
65 int IntelDoubleRegister::NumAllocatableRegisters() {
66 if (CpuFeatures::IsSupported(SSE2)) {
67 return XMMRegister::kNumAllocatableRegisters;
69 return X87Register::kNumAllocatableRegisters;
74 int IntelDoubleRegister::NumRegisters() {
75 if (CpuFeatures::IsSupported(SSE2)) {
76 return XMMRegister::kNumRegisters;
78 return X87Register::kNumRegisters;
83 const char* IntelDoubleRegister::AllocationIndexToString(int index) {
84 if (CpuFeatures::IsSupported(SSE2)) {
85 return XMMRegister::AllocationIndexToString(index);
87 return X87Register::AllocationIndexToString(index);
92 void CpuFeatures::Probe() {
93 ASSERT(!initialized_);
94 ASSERT(supported_ == 0);
98 if (Serializer::enabled()) {
99 supported_ |= OS::CpuFeaturesImpliedByPlatform();
100 return; // No features if we might serialize.
103 uint64_t probed_features = 0;
105 if (cpu.has_sse41()) {
106 probed_features |= static_cast<uint64_t>(1) << SSE4_1;
108 if (cpu.has_sse3()) {
109 probed_features |= static_cast<uint64_t>(1) << SSE3;
111 if (cpu.has_sse2()) {
112 probed_features |= static_cast<uint64_t>(1) << SSE2;
114 if (cpu.has_cmov()) {
115 probed_features |= static_cast<uint64_t>(1) << CMOV;
118 // SAHF must be available in compat/legacy mode.
119 ASSERT(cpu.has_sahf());
120 probed_features |= static_cast<uint64_t>(1) << SAHF;
122 uint64_t platform_features = OS::CpuFeaturesImpliedByPlatform();
123 supported_ = probed_features | platform_features;
124 found_by_runtime_probing_only_ = probed_features & ~platform_features;
128 // -----------------------------------------------------------------------------
129 // Implementation of Displacement
131 void Displacement::init(Label* L, Type type) {
132 ASSERT(!L->is_bound());
134 if (L->is_linked()) {
136 ASSERT(next > 0); // Displacements must be at positions > 0
138 // Ensure that we _never_ overflow the next field.
139 ASSERT(NextField::is_valid(Assembler::kMaximalBufferSize));
140 data_ = NextField::encode(next) | TypeField::encode(type);
144 // -----------------------------------------------------------------------------
145 // Implementation of RelocInfo
148 const int RelocInfo::kApplyMask =
149 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
150 1 << RelocInfo::JS_RETURN | 1 << RelocInfo::INTERNAL_REFERENCE |
151 1 << RelocInfo::DEBUG_BREAK_SLOT | 1 << RelocInfo::CODE_AGE_SEQUENCE;
154 bool RelocInfo::IsCodedSpecially() {
155 // The deserializer needs to know whether a pointer is specially coded. Being
156 // specially coded on IA32 means that it is a relative address, as used by
157 // branch instructions. These are also the ones that need changing when a
158 // code object moves.
159 return (1 << rmode_) & kApplyMask;
163 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
164 // Patch the code at the current address with the supplied instructions.
165 for (int i = 0; i < instruction_count; i++) {
166 *(pc_ + i) = *(instructions + i);
169 // Indicate that code has changed.
170 CPU::FlushICache(pc_, instruction_count);
174 // Patch the code at the current PC with a call to the target address.
175 // Additional guard int3 instructions can be added if required.
176 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
177 // Call instruction takes up 5 bytes and int3 takes up one byte.
178 static const int kCallCodeSize = 5;
179 int code_size = kCallCodeSize + guard_bytes;
181 // Create a code patcher.
182 CodePatcher patcher(pc_, code_size);
184 // Add a label for checking the size of the code used for returning.
186 Label check_codesize;
187 patcher.masm()->bind(&check_codesize);
191 patcher.masm()->call(target, RelocInfo::NONE32);
193 // Check that the size of the code generated is as expected.
194 ASSERT_EQ(kCallCodeSize,
195 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
197 // Add the requested number of int3 instructions after the call.
198 ASSERT_GE(guard_bytes, 0);
199 for (int i = 0; i < guard_bytes; i++) {
200 patcher.masm()->int3();
205 // -----------------------------------------------------------------------------
206 // Implementation of Operand
208 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
210 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
213 if (base.is(esp)) set_sib(times_1, esp, base);
214 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
217 if (base.is(esp)) set_sib(times_1, esp, base);
222 if (base.is(esp)) set_sib(times_1, esp, base);
223 set_dispr(disp, rmode);
228 Operand::Operand(Register base,
232 RelocInfo::Mode rmode) {
233 ASSERT(!index.is(esp)); // illegal addressing mode
234 // [base + index*scale + disp/r]
235 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
236 // [base + index*scale]
238 set_sib(scale, index, base);
239 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
240 // [base + index*scale + disp8]
242 set_sib(scale, index, base);
245 // [base + index*scale + disp/r]
247 set_sib(scale, index, base);
248 set_dispr(disp, rmode);
253 Operand::Operand(Register index,
256 RelocInfo::Mode rmode) {
257 ASSERT(!index.is(esp)); // illegal addressing mode
258 // [index*scale + disp/r]
260 set_sib(scale, index, ebp);
261 set_dispr(disp, rmode);
265 bool Operand::is_reg(Register reg) const {
266 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
267 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
271 bool Operand::is_reg_only() const {
272 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
276 Register Operand::reg() const {
277 ASSERT(is_reg_only());
278 return Register::from_code(buf_[0] & 0x07);
282 // -----------------------------------------------------------------------------
283 // Implementation of Assembler.
285 // Emit a single byte. Must always be inlined.
290 #ifdef GENERATED_CODE_COVERAGE
291 static void InitCoverageLog();
294 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
295 : AssemblerBase(isolate, buffer, buffer_size),
296 positions_recorder_(this) {
297 // Clear the buffer in debug mode unless it was provided by the
298 // caller in which case we can't be sure it's okay to overwrite
299 // existing code in it; see CodePatcher::CodePatcher(...).
302 memset(buffer_, 0xCC, buffer_size_); // int3
306 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
308 #ifdef GENERATED_CODE_COVERAGE
314 void Assembler::GetCode(CodeDesc* desc) {
315 // Finalize code (at this point overflow() may be true, but the gap ensures
316 // that we are still not overlapping instructions and relocation info).
317 ASSERT(pc_ <= reloc_info_writer.pos()); // No overlap.
318 // Set up code descriptor.
319 desc->buffer = buffer_;
320 desc->buffer_size = buffer_size_;
321 desc->instr_size = pc_offset();
322 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
327 void Assembler::Align(int m) {
328 ASSERT(IsPowerOf2(m));
330 int addr = pc_offset();
331 Nop((m - (addr & mask)) & mask);
335 bool Assembler::IsNop(Address addr) {
337 while (*a == 0x66) a++;
338 if (*a == 0x90) return true;
339 if (a[0] == 0xf && a[1] == 0x1f) return true;
344 void Assembler::Nop(int bytes) {
345 EnsureSpace ensure_space(this);
347 if (!CpuFeatures::IsSupported(SSE2)) {
348 // Older CPUs that do not support SSE2 may not support multibyte NOP
350 for (; bytes > 0; bytes--) {
356 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
418 void Assembler::CodeTargetAlign() {
419 Align(16); // Preferred alignment of jump targets on ia32.
423 void Assembler::cpuid() {
424 EnsureSpace ensure_space(this);
430 void Assembler::pushad() {
431 EnsureSpace ensure_space(this);
436 void Assembler::popad() {
437 EnsureSpace ensure_space(this);
442 void Assembler::pushfd() {
443 EnsureSpace ensure_space(this);
448 void Assembler::popfd() {
449 EnsureSpace ensure_space(this);
454 void Assembler::push(const Immediate& x) {
455 EnsureSpace ensure_space(this);
466 void Assembler::push_imm32(int32_t imm32) {
467 EnsureSpace ensure_space(this);
473 void Assembler::push(Register src) {
474 EnsureSpace ensure_space(this);
475 EMIT(0x50 | src.code());
479 void Assembler::push(const Operand& src) {
480 EnsureSpace ensure_space(this);
482 emit_operand(esi, src);
486 void Assembler::pop(Register dst) {
487 ASSERT(reloc_info_writer.last_pc() != NULL);
488 EnsureSpace ensure_space(this);
489 EMIT(0x58 | dst.code());
493 void Assembler::pop(const Operand& dst) {
494 EnsureSpace ensure_space(this);
496 emit_operand(eax, dst);
500 void Assembler::enter(const Immediate& size) {
501 EnsureSpace ensure_space(this);
508 void Assembler::leave() {
509 EnsureSpace ensure_space(this);
514 void Assembler::mov_b(Register dst, const Operand& src) {
515 CHECK(dst.is_byte_register());
516 EnsureSpace ensure_space(this);
518 emit_operand(dst, src);
522 void Assembler::mov_b(const Operand& dst, int8_t imm8) {
523 EnsureSpace ensure_space(this);
525 emit_operand(eax, dst);
530 void Assembler::mov_b(const Operand& dst, Register src) {
531 CHECK(src.is_byte_register());
532 EnsureSpace ensure_space(this);
534 emit_operand(src, dst);
538 void Assembler::mov_w(Register dst, const Operand& src) {
539 EnsureSpace ensure_space(this);
542 emit_operand(dst, src);
546 void Assembler::mov_w(const Operand& dst, Register src) {
547 EnsureSpace ensure_space(this);
550 emit_operand(src, dst);
554 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
555 EnsureSpace ensure_space(this);
558 emit_operand(eax, dst);
559 EMIT(static_cast<int8_t>(imm16 & 0xff));
560 EMIT(static_cast<int8_t>(imm16 >> 8));
564 void Assembler::mov(Register dst, int32_t imm32) {
565 EnsureSpace ensure_space(this);
566 EMIT(0xB8 | dst.code());
571 void Assembler::mov(Register dst, const Immediate& x) {
572 EnsureSpace ensure_space(this);
573 EMIT(0xB8 | dst.code());
578 void Assembler::mov(Register dst, Handle<Object> handle) {
579 EnsureSpace ensure_space(this);
580 EMIT(0xB8 | dst.code());
585 void Assembler::mov(Register dst, const Operand& src) {
586 EnsureSpace ensure_space(this);
588 emit_operand(dst, src);
592 void Assembler::mov(Register dst, Register src) {
593 EnsureSpace ensure_space(this);
595 EMIT(0xC0 | src.code() << 3 | dst.code());
599 void Assembler::mov(const Operand& dst, const Immediate& x) {
600 EnsureSpace ensure_space(this);
602 emit_operand(eax, dst);
607 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
608 EnsureSpace ensure_space(this);
610 emit_operand(eax, dst);
615 void Assembler::mov(const Operand& dst, Register src) {
616 EnsureSpace ensure_space(this);
618 emit_operand(src, dst);
622 void Assembler::movsx_b(Register dst, const Operand& src) {
623 EnsureSpace ensure_space(this);
626 emit_operand(dst, src);
630 void Assembler::movsx_w(Register dst, const Operand& src) {
631 EnsureSpace ensure_space(this);
634 emit_operand(dst, src);
638 void Assembler::movzx_b(Register dst, const Operand& src) {
639 EnsureSpace ensure_space(this);
642 emit_operand(dst, src);
646 void Assembler::movzx_w(Register dst, const Operand& src) {
647 EnsureSpace ensure_space(this);
650 emit_operand(dst, src);
654 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
655 ASSERT(IsEnabled(CMOV));
656 EnsureSpace ensure_space(this);
657 // Opcode: 0f 40 + cc /r.
660 emit_operand(dst, src);
664 void Assembler::cld() {
665 EnsureSpace ensure_space(this);
670 void Assembler::rep_movs() {
671 EnsureSpace ensure_space(this);
677 void Assembler::rep_stos() {
678 EnsureSpace ensure_space(this);
684 void Assembler::stos() {
685 EnsureSpace ensure_space(this);
690 void Assembler::xchg(Register dst, Register src) {
691 EnsureSpace ensure_space(this);
692 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
693 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
696 EMIT(0xC0 | src.code() << 3 | dst.code());
701 void Assembler::adc(Register dst, int32_t imm32) {
702 EnsureSpace ensure_space(this);
703 emit_arith(2, Operand(dst), Immediate(imm32));
707 void Assembler::adc(Register dst, const Operand& src) {
708 EnsureSpace ensure_space(this);
710 emit_operand(dst, src);
714 void Assembler::add(Register dst, const Operand& src) {
715 EnsureSpace ensure_space(this);
717 emit_operand(dst, src);
721 void Assembler::add(const Operand& dst, Register src) {
722 EnsureSpace ensure_space(this);
724 emit_operand(src, dst);
728 void Assembler::add(const Operand& dst, const Immediate& x) {
729 ASSERT(reloc_info_writer.last_pc() != NULL);
730 EnsureSpace ensure_space(this);
731 emit_arith(0, dst, x);
735 void Assembler::and_(Register dst, int32_t imm32) {
736 and_(dst, Immediate(imm32));
740 void Assembler::and_(Register dst, const Immediate& x) {
741 EnsureSpace ensure_space(this);
742 emit_arith(4, Operand(dst), x);
746 void Assembler::and_(Register dst, const Operand& src) {
747 EnsureSpace ensure_space(this);
749 emit_operand(dst, src);
753 void Assembler::and_(const Operand& dst, const Immediate& x) {
754 EnsureSpace ensure_space(this);
755 emit_arith(4, dst, x);
759 void Assembler::and_(const Operand& dst, Register src) {
760 EnsureSpace ensure_space(this);
762 emit_operand(src, dst);
766 void Assembler::cmpb(const Operand& op, int8_t imm8) {
767 EnsureSpace ensure_space(this);
768 if (op.is_reg(eax)) {
772 emit_operand(edi, op); // edi == 7
778 void Assembler::cmpb(const Operand& op, Register reg) {
779 CHECK(reg.is_byte_register());
780 EnsureSpace ensure_space(this);
782 emit_operand(reg, op);
786 void Assembler::cmpb(Register reg, const Operand& op) {
787 CHECK(reg.is_byte_register());
788 EnsureSpace ensure_space(this);
790 emit_operand(reg, op);
794 void Assembler::cmpw(const Operand& op, Immediate imm16) {
795 ASSERT(imm16.is_int16());
796 EnsureSpace ensure_space(this);
799 emit_operand(edi, op);
804 void Assembler::cmp(Register reg, int32_t imm32) {
805 EnsureSpace ensure_space(this);
806 emit_arith(7, Operand(reg), Immediate(imm32));
810 void Assembler::cmp(Register reg, Handle<Object> handle) {
811 EnsureSpace ensure_space(this);
812 emit_arith(7, Operand(reg), Immediate(handle));
816 void Assembler::cmp(Register reg, const Operand& op) {
817 EnsureSpace ensure_space(this);
819 emit_operand(reg, op);
823 void Assembler::cmp(const Operand& op, const Immediate& imm) {
824 EnsureSpace ensure_space(this);
825 emit_arith(7, op, imm);
829 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
830 EnsureSpace ensure_space(this);
831 emit_arith(7, op, Immediate(handle));
835 void Assembler::cmpb_al(const Operand& op) {
836 EnsureSpace ensure_space(this);
837 EMIT(0x38); // CMP r/m8, r8
838 emit_operand(eax, op); // eax has same code as register al.
842 void Assembler::cmpw_ax(const Operand& op) {
843 EnsureSpace ensure_space(this);
845 EMIT(0x39); // CMP r/m16, r16
846 emit_operand(eax, op); // eax has same code as register ax.
850 void Assembler::dec_b(Register dst) {
851 CHECK(dst.is_byte_register());
852 EnsureSpace ensure_space(this);
854 EMIT(0xC8 | dst.code());
858 void Assembler::dec_b(const Operand& dst) {
859 EnsureSpace ensure_space(this);
861 emit_operand(ecx, dst);
865 void Assembler::dec(Register dst) {
866 EnsureSpace ensure_space(this);
867 EMIT(0x48 | dst.code());
871 void Assembler::dec(const Operand& dst) {
872 EnsureSpace ensure_space(this);
874 emit_operand(ecx, dst);
878 void Assembler::cdq() {
879 EnsureSpace ensure_space(this);
884 void Assembler::idiv(Register src) {
885 EnsureSpace ensure_space(this);
887 EMIT(0xF8 | src.code());
891 void Assembler::imul(Register reg) {
892 EnsureSpace ensure_space(this);
894 EMIT(0xE8 | reg.code());
898 void Assembler::imul(Register dst, const Operand& src) {
899 EnsureSpace ensure_space(this);
902 emit_operand(dst, src);
906 void Assembler::imul(Register dst, Register src, int32_t imm32) {
907 EnsureSpace ensure_space(this);
908 if (is_int8(imm32)) {
910 EMIT(0xC0 | dst.code() << 3 | src.code());
914 EMIT(0xC0 | dst.code() << 3 | src.code());
920 void Assembler::inc(Register dst) {
921 EnsureSpace ensure_space(this);
922 EMIT(0x40 | dst.code());
926 void Assembler::inc(const Operand& dst) {
927 EnsureSpace ensure_space(this);
929 emit_operand(eax, dst);
933 void Assembler::lea(Register dst, const Operand& src) {
934 EnsureSpace ensure_space(this);
936 emit_operand(dst, src);
940 void Assembler::mul(Register src) {
941 EnsureSpace ensure_space(this);
943 EMIT(0xE0 | src.code());
947 void Assembler::neg(Register dst) {
948 EnsureSpace ensure_space(this);
950 EMIT(0xD8 | dst.code());
954 void Assembler::not_(Register dst) {
955 EnsureSpace ensure_space(this);
957 EMIT(0xD0 | dst.code());
961 void Assembler::or_(Register dst, int32_t imm32) {
962 EnsureSpace ensure_space(this);
963 emit_arith(1, Operand(dst), Immediate(imm32));
967 void Assembler::or_(Register dst, const Operand& src) {
968 EnsureSpace ensure_space(this);
970 emit_operand(dst, src);
974 void Assembler::or_(const Operand& dst, const Immediate& x) {
975 EnsureSpace ensure_space(this);
976 emit_arith(1, dst, x);
980 void Assembler::or_(const Operand& dst, Register src) {
981 EnsureSpace ensure_space(this);
983 emit_operand(src, dst);
987 void Assembler::rcl(Register dst, uint8_t imm8) {
988 EnsureSpace ensure_space(this);
989 ASSERT(is_uint5(imm8)); // illegal shift count
992 EMIT(0xD0 | dst.code());
995 EMIT(0xD0 | dst.code());
1001 void Assembler::rcr(Register dst, uint8_t imm8) {
1002 EnsureSpace ensure_space(this);
1003 ASSERT(is_uint5(imm8)); // illegal shift count
1006 EMIT(0xD8 | dst.code());
1009 EMIT(0xD8 | dst.code());
1015 void Assembler::ror(Register dst, uint8_t imm8) {
1016 EnsureSpace ensure_space(this);
1017 ASSERT(is_uint5(imm8)); // illegal shift count
1020 EMIT(0xC8 | dst.code());
1023 EMIT(0xC8 | dst.code());
1029 void Assembler::ror_cl(Register dst) {
1030 EnsureSpace ensure_space(this);
1032 EMIT(0xC8 | dst.code());
1036 void Assembler::sar(Register dst, uint8_t imm8) {
1037 EnsureSpace ensure_space(this);
1038 ASSERT(is_uint5(imm8)); // illegal shift count
1041 EMIT(0xF8 | dst.code());
1044 EMIT(0xF8 | dst.code());
1050 void Assembler::sar_cl(Register dst) {
1051 EnsureSpace ensure_space(this);
1053 EMIT(0xF8 | dst.code());
1057 void Assembler::sbb(Register dst, const Operand& src) {
1058 EnsureSpace ensure_space(this);
1060 emit_operand(dst, src);
1064 void Assembler::shld(Register dst, const Operand& src) {
1065 EnsureSpace ensure_space(this);
1068 emit_operand(dst, src);
1072 void Assembler::shl(Register dst, uint8_t imm8) {
1073 EnsureSpace ensure_space(this);
1074 ASSERT(is_uint5(imm8)); // illegal shift count
1077 EMIT(0xE0 | dst.code());
1080 EMIT(0xE0 | dst.code());
1086 void Assembler::shl_cl(Register dst) {
1087 EnsureSpace ensure_space(this);
1089 EMIT(0xE0 | dst.code());
1093 void Assembler::shrd(Register dst, const Operand& src) {
1094 EnsureSpace ensure_space(this);
1097 emit_operand(dst, src);
1101 void Assembler::shr(Register dst, uint8_t imm8) {
1102 EnsureSpace ensure_space(this);
1103 ASSERT(is_uint5(imm8)); // illegal shift count
1106 EMIT(0xE8 | dst.code());
1109 EMIT(0xE8 | dst.code());
1115 void Assembler::shr_cl(Register dst) {
1116 EnsureSpace ensure_space(this);
1118 EMIT(0xE8 | dst.code());
1122 void Assembler::sub(const Operand& dst, const Immediate& x) {
1123 EnsureSpace ensure_space(this);
1124 emit_arith(5, dst, x);
1128 void Assembler::sub(Register dst, const Operand& src) {
1129 EnsureSpace ensure_space(this);
1131 emit_operand(dst, src);
1135 void Assembler::sub(const Operand& dst, Register src) {
1136 EnsureSpace ensure_space(this);
1138 emit_operand(src, dst);
1142 void Assembler::test(Register reg, const Immediate& imm) {
1143 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1144 test_b(reg, imm.x_);
1148 EnsureSpace ensure_space(this);
1149 // This is not using emit_arith because test doesn't support
1150 // sign-extension of 8-bit operands.
1155 EMIT(0xC0 | reg.code());
1161 void Assembler::test(Register reg, const Operand& op) {
1162 EnsureSpace ensure_space(this);
1164 emit_operand(reg, op);
1168 void Assembler::test_b(Register reg, const Operand& op) {
1169 CHECK(reg.is_byte_register());
1170 EnsureSpace ensure_space(this);
1172 emit_operand(reg, op);
1176 void Assembler::test(const Operand& op, const Immediate& imm) {
1177 if (op.is_reg_only()) {
1178 test(op.reg(), imm);
1181 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1182 return test_b(op, imm.x_);
1184 EnsureSpace ensure_space(this);
1186 emit_operand(eax, op);
1191 void Assembler::test_b(Register reg, uint8_t imm8) {
1192 EnsureSpace ensure_space(this);
1193 // Only use test against byte for registers that have a byte
1194 // variant: eax, ebx, ecx, and edx.
1198 } else if (reg.is_byte_register()) {
1199 emit_arith_b(0xF6, 0xC0, reg, imm8);
1202 EMIT(0xC0 | reg.code());
1208 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1209 if (op.is_reg_only()) {
1210 test_b(op.reg(), imm8);
1213 EnsureSpace ensure_space(this);
1215 emit_operand(eax, op);
1220 void Assembler::xor_(Register dst, int32_t imm32) {
1221 EnsureSpace ensure_space(this);
1222 emit_arith(6, Operand(dst), Immediate(imm32));
1226 void Assembler::xor_(Register dst, const Operand& src) {
1227 EnsureSpace ensure_space(this);
1229 emit_operand(dst, src);
1233 void Assembler::xor_(const Operand& dst, Register src) {
1234 EnsureSpace ensure_space(this);
1236 emit_operand(src, dst);
1240 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1241 EnsureSpace ensure_space(this);
1242 emit_arith(6, dst, x);
1246 void Assembler::bt(const Operand& dst, Register src) {
1247 EnsureSpace ensure_space(this);
1250 emit_operand(src, dst);
1254 void Assembler::bts(const Operand& dst, Register src) {
1255 EnsureSpace ensure_space(this);
1258 emit_operand(src, dst);
1262 void Assembler::hlt() {
1263 EnsureSpace ensure_space(this);
1268 void Assembler::int3() {
1269 EnsureSpace ensure_space(this);
1274 void Assembler::nop() {
1275 EnsureSpace ensure_space(this);
1280 void Assembler::ret(int imm16) {
1281 EnsureSpace ensure_space(this);
1282 ASSERT(is_uint16(imm16));
1288 EMIT((imm16 >> 8) & 0xFF);
1293 // Labels refer to positions in the (to be) generated code.
1294 // There are bound, linked, and unused labels.
1296 // Bound labels refer to known positions in the already
1297 // generated code. pos() is the position the label refers to.
1299 // Linked labels refer to unknown positions in the code
1300 // to be generated; pos() is the position of the 32bit
1301 // Displacement of the last instruction using the label.
1304 void Assembler::print(Label* L) {
1305 if (L->is_unused()) {
1306 PrintF("unused label\n");
1307 } else if (L->is_bound()) {
1308 PrintF("bound label to %d\n", L->pos());
1309 } else if (L->is_linked()) {
1311 PrintF("unbound label");
1312 while (l.is_linked()) {
1313 Displacement disp = disp_at(&l);
1314 PrintF("@ %d ", l.pos());
1320 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1325 void Assembler::bind_to(Label* L, int pos) {
1326 EnsureSpace ensure_space(this);
1327 ASSERT(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1328 while (L->is_linked()) {
1329 Displacement disp = disp_at(L);
1330 int fixup_pos = L->pos();
1331 if (disp.type() == Displacement::CODE_RELATIVE) {
1332 // Relative to Code* heap object pointer.
1333 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1335 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1336 ASSERT(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1338 // Relative address, relative to point after address.
1339 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1340 long_at_put(fixup_pos, imm32);
1344 while (L->is_near_linked()) {
1345 int fixup_pos = L->near_link_pos();
1346 int offset_to_next =
1347 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1348 ASSERT(offset_to_next <= 0);
1349 // Relative address, relative to point after address.
1350 int disp = pos - fixup_pos - sizeof(int8_t);
1351 CHECK(0 <= disp && disp <= 127);
1352 set_byte_at(fixup_pos, disp);
1353 if (offset_to_next < 0) {
1354 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1363 void Assembler::bind(Label* L) {
1364 EnsureSpace ensure_space(this);
1365 ASSERT(!L->is_bound()); // label can only be bound once
1366 bind_to(L, pc_offset());
1370 void Assembler::call(Label* L) {
1371 positions_recorder()->WriteRecordedPositions();
1372 EnsureSpace ensure_space(this);
1373 if (L->is_bound()) {
1374 const int long_size = 5;
1375 int offs = L->pos() - pc_offset();
1377 // 1110 1000 #32-bit disp.
1379 emit(offs - long_size);
1381 // 1110 1000 #32-bit disp.
1383 emit_disp(L, Displacement::OTHER);
1388 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1389 positions_recorder()->WriteRecordedPositions();
1390 EnsureSpace ensure_space(this);
1391 ASSERT(!RelocInfo::IsCodeTarget(rmode));
1393 if (RelocInfo::IsRuntimeEntry(rmode)) {
1394 emit(reinterpret_cast<uint32_t>(entry), rmode);
1396 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1401 int Assembler::CallSize(const Operand& adr) {
1402 // Call size is 1 (opcode) + adr.len_ (operand).
1403 return 1 + adr.len_;
1407 void Assembler::call(const Operand& adr) {
1408 positions_recorder()->WriteRecordedPositions();
1409 EnsureSpace ensure_space(this);
1411 emit_operand(edx, adr);
1415 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1416 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1420 void Assembler::call(Handle<Code> code,
1421 RelocInfo::Mode rmode,
1422 TypeFeedbackId ast_id) {
1423 positions_recorder()->WriteRecordedPositions();
1424 EnsureSpace ensure_space(this);
1425 ASSERT(RelocInfo::IsCodeTarget(rmode)
1426 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1428 emit(code, rmode, ast_id);
1432 void Assembler::jmp(Label* L, Label::Distance distance) {
1433 EnsureSpace ensure_space(this);
1434 if (L->is_bound()) {
1435 const int short_size = 2;
1436 const int long_size = 5;
1437 int offs = L->pos() - pc_offset();
1439 if (is_int8(offs - short_size)) {
1440 // 1110 1011 #8-bit disp.
1442 EMIT((offs - short_size) & 0xFF);
1444 // 1110 1001 #32-bit disp.
1446 emit(offs - long_size);
1448 } else if (distance == Label::kNear) {
1452 // 1110 1001 #32-bit disp.
1454 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1459 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1460 EnsureSpace ensure_space(this);
1461 ASSERT(!RelocInfo::IsCodeTarget(rmode));
1463 if (RelocInfo::IsRuntimeEntry(rmode)) {
1464 emit(reinterpret_cast<uint32_t>(entry), rmode);
1466 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1471 void Assembler::jmp(const Operand& adr) {
1472 EnsureSpace ensure_space(this);
1474 emit_operand(esp, adr);
1478 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1479 EnsureSpace ensure_space(this);
1480 ASSERT(RelocInfo::IsCodeTarget(rmode));
1486 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1487 EnsureSpace ensure_space(this);
1488 ASSERT(0 <= cc && static_cast<int>(cc) < 16);
1489 if (L->is_bound()) {
1490 const int short_size = 2;
1491 const int long_size = 6;
1492 int offs = L->pos() - pc_offset();
1494 if (is_int8(offs - short_size)) {
1495 // 0111 tttn #8-bit disp
1497 EMIT((offs - short_size) & 0xFF);
1499 // 0000 1111 1000 tttn #32-bit disp
1502 emit(offs - long_size);
1504 } else if (distance == Label::kNear) {
1508 // 0000 1111 1000 tttn #32-bit disp
1509 // Note: could eliminate cond. jumps to this jump if condition
1510 // is the same however, seems to be rather unlikely case.
1513 emit_disp(L, Displacement::OTHER);
1518 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1519 EnsureSpace ensure_space(this);
1520 ASSERT((0 <= cc) && (static_cast<int>(cc) < 16));
1521 // 0000 1111 1000 tttn #32-bit disp.
1524 if (RelocInfo::IsRuntimeEntry(rmode)) {
1525 emit(reinterpret_cast<uint32_t>(entry), rmode);
1527 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1532 void Assembler::j(Condition cc, Handle<Code> code) {
1533 EnsureSpace ensure_space(this);
1534 // 0000 1111 1000 tttn #32-bit disp
1537 emit(code, RelocInfo::CODE_TARGET);
1541 // FPU instructions.
1543 void Assembler::fld(int i) {
1544 EnsureSpace ensure_space(this);
1545 emit_farith(0xD9, 0xC0, i);
1549 void Assembler::fstp(int i) {
1550 EnsureSpace ensure_space(this);
1551 emit_farith(0xDD, 0xD8, i);
1555 void Assembler::fld1() {
1556 EnsureSpace ensure_space(this);
1562 void Assembler::fldpi() {
1563 EnsureSpace ensure_space(this);
1569 void Assembler::fldz() {
1570 EnsureSpace ensure_space(this);
1576 void Assembler::fldln2() {
1577 EnsureSpace ensure_space(this);
1583 void Assembler::fld_s(const Operand& adr) {
1584 EnsureSpace ensure_space(this);
1586 emit_operand(eax, adr);
1590 void Assembler::fld_d(const Operand& adr) {
1591 EnsureSpace ensure_space(this);
1593 emit_operand(eax, adr);
1597 void Assembler::fstp_s(const Operand& adr) {
1598 EnsureSpace ensure_space(this);
1600 emit_operand(ebx, adr);
1604 void Assembler::fst_s(const Operand& adr) {
1605 EnsureSpace ensure_space(this);
1607 emit_operand(edx, adr);
1611 void Assembler::fstp_d(const Operand& adr) {
1612 EnsureSpace ensure_space(this);
1614 emit_operand(ebx, adr);
1618 void Assembler::fst_d(const Operand& adr) {
1619 EnsureSpace ensure_space(this);
1621 emit_operand(edx, adr);
1625 void Assembler::fild_s(const Operand& adr) {
1626 EnsureSpace ensure_space(this);
1628 emit_operand(eax, adr);
1632 void Assembler::fild_d(const Operand& adr) {
1633 EnsureSpace ensure_space(this);
1635 emit_operand(ebp, adr);
1639 void Assembler::fistp_s(const Operand& adr) {
1640 EnsureSpace ensure_space(this);
1642 emit_operand(ebx, adr);
1646 void Assembler::fisttp_s(const Operand& adr) {
1647 ASSERT(IsEnabled(SSE3));
1648 EnsureSpace ensure_space(this);
1650 emit_operand(ecx, adr);
1654 void Assembler::fisttp_d(const Operand& adr) {
1655 ASSERT(IsEnabled(SSE3));
1656 EnsureSpace ensure_space(this);
1658 emit_operand(ecx, adr);
1662 void Assembler::fist_s(const Operand& adr) {
1663 EnsureSpace ensure_space(this);
1665 emit_operand(edx, adr);
1669 void Assembler::fistp_d(const Operand& adr) {
1670 EnsureSpace ensure_space(this);
1672 emit_operand(edi, adr);
1676 void Assembler::fabs() {
1677 EnsureSpace ensure_space(this);
1683 void Assembler::fchs() {
1684 EnsureSpace ensure_space(this);
1690 void Assembler::fcos() {
1691 EnsureSpace ensure_space(this);
1697 void Assembler::fsin() {
1698 EnsureSpace ensure_space(this);
1704 void Assembler::fptan() {
1705 EnsureSpace ensure_space(this);
1711 void Assembler::fyl2x() {
1712 EnsureSpace ensure_space(this);
1718 void Assembler::f2xm1() {
1719 EnsureSpace ensure_space(this);
1725 void Assembler::fscale() {
1726 EnsureSpace ensure_space(this);
1732 void Assembler::fninit() {
1733 EnsureSpace ensure_space(this);
1739 void Assembler::fadd(int i) {
1740 EnsureSpace ensure_space(this);
1741 emit_farith(0xDC, 0xC0, i);
1745 void Assembler::fadd_i(int i) {
1746 EnsureSpace ensure_space(this);
1747 emit_farith(0xD8, 0xC0, i);
1751 void Assembler::fsub(int i) {
1752 EnsureSpace ensure_space(this);
1753 emit_farith(0xDC, 0xE8, i);
1757 void Assembler::fsub_i(int i) {
1758 EnsureSpace ensure_space(this);
1759 emit_farith(0xD8, 0xE0, i);
1763 void Assembler::fisub_s(const Operand& adr) {
1764 EnsureSpace ensure_space(this);
1766 emit_operand(esp, adr);
1770 void Assembler::fmul_i(int i) {
1771 EnsureSpace ensure_space(this);
1772 emit_farith(0xD8, 0xC8, i);
1776 void Assembler::fmul(int i) {
1777 EnsureSpace ensure_space(this);
1778 emit_farith(0xDC, 0xC8, i);
1782 void Assembler::fdiv(int i) {
1783 EnsureSpace ensure_space(this);
1784 emit_farith(0xDC, 0xF8, i);
1788 void Assembler::fdiv_i(int i) {
1789 EnsureSpace ensure_space(this);
1790 emit_farith(0xD8, 0xF0, i);
1794 void Assembler::faddp(int i) {
1795 EnsureSpace ensure_space(this);
1796 emit_farith(0xDE, 0xC0, i);
1800 void Assembler::fsubp(int i) {
1801 EnsureSpace ensure_space(this);
1802 emit_farith(0xDE, 0xE8, i);
1806 void Assembler::fsubrp(int i) {
1807 EnsureSpace ensure_space(this);
1808 emit_farith(0xDE, 0xE0, i);
1812 void Assembler::fmulp(int i) {
1813 EnsureSpace ensure_space(this);
1814 emit_farith(0xDE, 0xC8, i);
1818 void Assembler::fdivp(int i) {
1819 EnsureSpace ensure_space(this);
1820 emit_farith(0xDE, 0xF8, i);
1824 void Assembler::fprem() {
1825 EnsureSpace ensure_space(this);
1831 void Assembler::fprem1() {
1832 EnsureSpace ensure_space(this);
1838 void Assembler::fxch(int i) {
1839 EnsureSpace ensure_space(this);
1840 emit_farith(0xD9, 0xC8, i);
1844 void Assembler::fincstp() {
1845 EnsureSpace ensure_space(this);
1851 void Assembler::ffree(int i) {
1852 EnsureSpace ensure_space(this);
1853 emit_farith(0xDD, 0xC0, i);
1857 void Assembler::ftst() {
1858 EnsureSpace ensure_space(this);
1864 void Assembler::fucomp(int i) {
1865 EnsureSpace ensure_space(this);
1866 emit_farith(0xDD, 0xE8, i);
1870 void Assembler::fucompp() {
1871 EnsureSpace ensure_space(this);
1877 void Assembler::fucomi(int i) {
1878 EnsureSpace ensure_space(this);
1884 void Assembler::fucomip() {
1885 EnsureSpace ensure_space(this);
1891 void Assembler::fcompp() {
1892 EnsureSpace ensure_space(this);
1898 void Assembler::fnstsw_ax() {
1899 EnsureSpace ensure_space(this);
1905 void Assembler::fwait() {
1906 EnsureSpace ensure_space(this);
1911 void Assembler::frndint() {
1912 EnsureSpace ensure_space(this);
1918 void Assembler::fnclex() {
1919 EnsureSpace ensure_space(this);
1925 void Assembler::sahf() {
1926 EnsureSpace ensure_space(this);
1931 void Assembler::setcc(Condition cc, Register reg) {
1932 ASSERT(reg.is_byte_register());
1933 EnsureSpace ensure_space(this);
1936 EMIT(0xC0 | reg.code());
1940 void Assembler::cvttss2si(Register dst, const Operand& src) {
1941 ASSERT(IsEnabled(SSE2));
1942 EnsureSpace ensure_space(this);
1946 emit_operand(dst, src);
1950 void Assembler::cvttsd2si(Register dst, const Operand& src) {
1951 ASSERT(IsEnabled(SSE2));
1952 EnsureSpace ensure_space(this);
1956 emit_operand(dst, src);
1960 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
1961 ASSERT(IsEnabled(SSE2));
1962 EnsureSpace ensure_space(this);
1966 emit_sse_operand(dst, src);
1970 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
1971 ASSERT(IsEnabled(SSE2));
1972 EnsureSpace ensure_space(this);
1976 emit_sse_operand(dst, src);
1980 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1981 ASSERT(IsEnabled(SSE2));
1982 EnsureSpace ensure_space(this);
1986 emit_sse_operand(dst, src);
1990 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1991 ASSERT(IsEnabled(SSE2));
1992 EnsureSpace ensure_space(this);
1996 emit_sse_operand(dst, src);
2000 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
2001 ASSERT(IsEnabled(SSE2));
2002 EnsureSpace ensure_space(this);
2006 emit_sse_operand(dst, src);
2010 void Assembler::addsd(XMMRegister dst, const Operand& src) {
2011 ASSERT(IsEnabled(SSE2));
2012 EnsureSpace ensure_space(this);
2016 emit_sse_operand(dst, src);
2020 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2021 ASSERT(IsEnabled(SSE2));
2022 EnsureSpace ensure_space(this);
2026 emit_sse_operand(dst, src);
2030 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2031 ASSERT(IsEnabled(SSE2));
2032 EnsureSpace ensure_space(this);
2036 emit_sse_operand(dst, src);
2040 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2041 ASSERT(IsEnabled(SSE2));
2042 EnsureSpace ensure_space(this);
2046 emit_sse_operand(dst, src);
2050 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2051 ASSERT(IsEnabled(SSE2));
2052 EnsureSpace ensure_space(this);
2056 emit_sse_operand(dst, src);
2060 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2061 ASSERT(IsEnabled(SSE2));
2062 EnsureSpace ensure_space(this);
2066 emit_sse_operand(dst, src);
2070 void Assembler::andps(XMMRegister dst, const Operand& src) {
2071 ASSERT(IsEnabled(SSE2));
2072 EnsureSpace ensure_space(this);
2075 emit_sse_operand(dst, src);
2079 void Assembler::orps(XMMRegister dst, const Operand& src) {
2080 ASSERT(IsEnabled(SSE2));
2081 EnsureSpace ensure_space(this);
2084 emit_sse_operand(dst, src);
2088 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2089 ASSERT(IsEnabled(SSE2));
2090 EnsureSpace ensure_space(this);
2093 emit_sse_operand(dst, src);
2097 void Assembler::addps(XMMRegister dst, const Operand& src) {
2098 ASSERT(IsEnabled(SSE2));
2099 EnsureSpace ensure_space(this);
2102 emit_sse_operand(dst, src);
2106 void Assembler::subps(XMMRegister dst, const Operand& src) {
2107 ASSERT(IsEnabled(SSE2));
2108 EnsureSpace ensure_space(this);
2111 emit_sse_operand(dst, src);
2115 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2116 ASSERT(IsEnabled(SSE2));
2117 EnsureSpace ensure_space(this);
2120 emit_sse_operand(dst, src);
2124 void Assembler::divps(XMMRegister dst, const Operand& src) {
2125 ASSERT(IsEnabled(SSE2));
2126 EnsureSpace ensure_space(this);
2129 emit_sse_operand(dst, src);
2133 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2134 ASSERT(IsEnabled(SSE2));
2135 EnsureSpace ensure_space(this);
2139 emit_sse_operand(dst, src);
2143 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2144 ASSERT(IsEnabled(SSE2));
2145 EnsureSpace ensure_space(this);
2149 emit_sse_operand(dst, src);
2153 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2154 ASSERT(IsEnabled(SSE2));
2155 EnsureSpace ensure_space(this);
2159 emit_sse_operand(dst, src);
2163 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2164 ASSERT(IsEnabled(SSE2));
2165 EnsureSpace ensure_space(this);
2169 emit_sse_operand(dst, src);
2173 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2174 ASSERT(IsEnabled(SSE4_1));
2175 EnsureSpace ensure_space(this);
2180 emit_sse_operand(dst, src);
2181 // Mask precision exeption.
2182 EMIT(static_cast<byte>(mode) | 0x8);
2186 void Assembler::movmskpd(Register dst, XMMRegister src) {
2187 ASSERT(IsEnabled(SSE2));
2188 EnsureSpace ensure_space(this);
2192 emit_sse_operand(dst, src);
2196 void Assembler::movmskps(Register dst, XMMRegister src) {
2197 ASSERT(IsEnabled(SSE2));
2198 EnsureSpace ensure_space(this);
2201 emit_sse_operand(dst, src);
2205 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
2206 ASSERT(IsEnabled(SSE2));
2207 EnsureSpace ensure_space(this);
2211 emit_sse_operand(dst, src);
2215 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2216 ASSERT(IsEnabled(SSE2));
2217 EnsureSpace ensure_space(this);
2221 emit_sse_operand(dst, src);
2226 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2227 ASSERT(IsEnabled(SSE2));
2228 EnsureSpace ensure_space(this);
2231 emit_sse_operand(dst, src);
2235 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2236 ASSERT(IsEnabled(SSE2));
2237 ASSERT(is_uint8(imm8));
2238 EnsureSpace ensure_space(this);
2241 emit_sse_operand(dst, src);
2246 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2247 ASSERT(IsEnabled(SSE2));
2248 EnsureSpace ensure_space(this);
2252 emit_sse_operand(src, dst);
2256 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2257 ASSERT(IsEnabled(SSE2));
2258 EnsureSpace ensure_space(this);
2262 emit_sse_operand(dst, src);
2266 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2267 ASSERT(IsEnabled(SSE2));
2268 EnsureSpace ensure_space(this);
2272 emit_sse_operand(src, dst);
2276 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2277 ASSERT(IsEnabled(SSE2));
2278 EnsureSpace ensure_space(this);
2282 emit_sse_operand(dst, src);
2286 void Assembler::movntdqa(XMMRegister dst, const Operand& src) {
2287 ASSERT(IsEnabled(SSE4_1));
2288 EnsureSpace ensure_space(this);
2293 emit_sse_operand(dst, src);
2297 void Assembler::movntdq(const Operand& dst, XMMRegister src) {
2298 ASSERT(IsEnabled(SSE2));
2299 EnsureSpace ensure_space(this);
2303 emit_sse_operand(src, dst);
2307 void Assembler::prefetch(const Operand& src, int level) {
2308 ASSERT(is_uint2(level));
2309 EnsureSpace ensure_space(this);
2312 // Emit hint number in Reg position of RegR/M.
2313 XMMRegister code = XMMRegister::from_code(level);
2314 emit_sse_operand(code, src);
2318 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2319 ASSERT(IsEnabled(SSE2));
2320 EnsureSpace ensure_space(this);
2321 EMIT(0xF2); // double
2323 EMIT(0x11); // store
2324 emit_sse_operand(src, dst);
2328 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2329 ASSERT(IsEnabled(SSE2));
2330 EnsureSpace ensure_space(this);
2331 EMIT(0xF2); // double
2334 emit_sse_operand(dst, src);
2338 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2339 ASSERT(IsEnabled(SSE2));
2340 EnsureSpace ensure_space(this);
2341 EMIT(0xF3); // float
2343 EMIT(0x11); // store
2344 emit_sse_operand(src, dst);
2348 void Assembler::movss(XMMRegister dst, const Operand& src) {
2349 ASSERT(IsEnabled(SSE2));
2350 EnsureSpace ensure_space(this);
2351 EMIT(0xF3); // float
2354 emit_sse_operand(dst, src);
2358 void Assembler::movd(XMMRegister dst, const Operand& src) {
2359 ASSERT(IsEnabled(SSE2));
2360 EnsureSpace ensure_space(this);
2364 emit_sse_operand(dst, src);
2368 void Assembler::movd(const Operand& dst, XMMRegister src) {
2369 ASSERT(IsEnabled(SSE2));
2370 EnsureSpace ensure_space(this);
2374 emit_sse_operand(src, dst);
2378 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2379 ASSERT(IsEnabled(SSE4_1));
2380 ASSERT(is_uint8(imm8));
2381 EnsureSpace ensure_space(this);
2386 emit_sse_operand(src, dst);
2391 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2392 ASSERT(IsEnabled(SSE2));
2393 EnsureSpace ensure_space(this);
2397 emit_sse_operand(dst, src);
2401 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2402 ASSERT(IsEnabled(SSE2));
2403 EnsureSpace ensure_space(this);
2407 emit_sse_operand(dst, src);
2411 void Assembler::por(XMMRegister dst, XMMRegister src) {
2412 ASSERT(IsEnabled(SSE2));
2413 EnsureSpace ensure_space(this);
2417 emit_sse_operand(dst, src);
2421 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2422 ASSERT(IsEnabled(SSE4_1));
2423 EnsureSpace ensure_space(this);
2428 emit_sse_operand(dst, src);
2432 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2433 ASSERT(IsEnabled(SSE2));
2434 EnsureSpace ensure_space(this);
2438 emit_sse_operand(esi, reg); // esi == 6
2443 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2444 ASSERT(IsEnabled(SSE2));
2445 EnsureSpace ensure_space(this);
2449 emit_sse_operand(dst, src);
2453 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2454 ASSERT(IsEnabled(SSE2));
2455 EnsureSpace ensure_space(this);
2459 emit_sse_operand(edx, reg); // edx == 2
2464 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2465 ASSERT(IsEnabled(SSE2));
2466 EnsureSpace ensure_space(this);
2470 emit_sse_operand(dst, src);
2474 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2475 ASSERT(IsEnabled(SSE2));
2476 EnsureSpace ensure_space(this);
2480 emit_sse_operand(dst, src);
2485 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2486 ASSERT(IsEnabled(SSE4_1));
2487 EnsureSpace ensure_space(this);
2492 emit_sse_operand(src, dst);
2497 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2498 ASSERT(IsEnabled(SSE4_1));
2499 EnsureSpace ensure_space(this);
2504 emit_sse_operand(dst, src);
2509 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2510 Register ireg = { reg.code() };
2511 emit_operand(ireg, adr);
2515 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2516 EMIT(0xC0 | dst.code() << 3 | src.code());
2520 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2521 EMIT(0xC0 | dst.code() << 3 | src.code());
2525 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2526 EMIT(0xC0 | (dst.code() << 3) | src.code());
2530 void Assembler::Print() {
2531 Disassembler::Decode(isolate(), stdout, buffer_, pc_);
2535 void Assembler::RecordJSReturn() {
2536 positions_recorder()->WriteRecordedPositions();
2537 EnsureSpace ensure_space(this);
2538 RecordRelocInfo(RelocInfo::JS_RETURN);
2542 void Assembler::RecordDebugBreakSlot() {
2543 positions_recorder()->WriteRecordedPositions();
2544 EnsureSpace ensure_space(this);
2545 RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT);
2549 void Assembler::RecordComment(const char* msg, bool force) {
2550 if (FLAG_code_comments || force) {
2551 EnsureSpace ensure_space(this);
2552 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
2557 void Assembler::GrowBuffer() {
2559 if (!own_buffer_) FATAL("external code buffer is too small");
2561 // Compute new buffer size.
2562 CodeDesc desc; // the new buffer
2563 if (buffer_size_ < 4*KB) {
2564 desc.buffer_size = 4*KB;
2566 desc.buffer_size = 2*buffer_size_;
2568 // Some internal data structures overflow for very large buffers,
2569 // they must ensure that kMaximalBufferSize is not too large.
2570 if ((desc.buffer_size > kMaximalBufferSize) ||
2571 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
2572 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
2575 // Set up new buffer.
2576 desc.buffer = NewArray<byte>(desc.buffer_size);
2577 desc.instr_size = pc_offset();
2578 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
2580 // Clear the buffer in debug mode. Use 'int3' instructions to make
2581 // sure to get into problems if we ever run uninitialized code.
2583 memset(desc.buffer, 0xCC, desc.buffer_size);
2587 int pc_delta = desc.buffer - buffer_;
2588 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
2589 OS::MemMove(desc.buffer, buffer_, desc.instr_size);
2590 OS::MemMove(rc_delta + reloc_info_writer.pos(),
2591 reloc_info_writer.pos(), desc.reloc_size);
2594 if (isolate()->assembler_spare_buffer() == NULL &&
2595 buffer_size_ == kMinimalBufferSize) {
2596 isolate()->set_assembler_spare_buffer(buffer_);
2598 DeleteArray(buffer_);
2600 buffer_ = desc.buffer;
2601 buffer_size_ = desc.buffer_size;
2603 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2604 reloc_info_writer.last_pc() + pc_delta);
2606 // Relocate runtime entries.
2607 for (RelocIterator it(desc); !it.done(); it.next()) {
2608 RelocInfo::Mode rmode = it.rinfo()->rmode();
2609 if (rmode == RelocInfo::INTERNAL_REFERENCE) {
2610 int32_t* p = reinterpret_cast<int32_t*>(it.rinfo()->pc());
2611 if (*p != 0) { // 0 means uninitialized.
2617 ASSERT(!overflow());
2621 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
2622 ASSERT(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2623 ASSERT(is_uint8(imm8));
2624 ASSERT((op1 & 0x01) == 0); // should be 8bit operation
2626 EMIT(op2 | dst.code());
2631 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
2632 ASSERT((0 <= sel) && (sel <= 7));
2633 Register ireg = { sel };
2635 EMIT(0x83); // using a sign-extended 8-bit immediate.
2636 emit_operand(ireg, dst);
2638 } else if (dst.is_reg(eax)) {
2639 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
2642 EMIT(0x81); // using a literal 32-bit immediate.
2643 emit_operand(ireg, dst);
2649 void Assembler::emit_operand(Register reg, const Operand& adr) {
2650 const unsigned length = adr.len_;
2653 // Emit updated ModRM byte containing the given register.
2654 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
2656 // Emit the rest of the encoded operand.
2657 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2660 // Emit relocation information if necessary.
2661 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2662 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2663 RecordRelocInfo(adr.rmode_);
2664 pc_ += sizeof(int32_t);
2669 void Assembler::emit_farith(int b1, int b2, int i) {
2670 ASSERT(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2671 ASSERT(0 <= i && i < 8); // illegal stack offset
2677 void Assembler::db(uint8_t data) {
2678 EnsureSpace ensure_space(this);
2683 void Assembler::dd(uint32_t data) {
2684 EnsureSpace ensure_space(this);
2689 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2690 ASSERT(!RelocInfo::IsNone(rmode));
2691 // Don't record external references unless the heap will be serialized.
2692 if (rmode == RelocInfo::EXTERNAL_REFERENCE) {
2694 if (!Serializer::enabled()) {
2695 Serializer::TooLateToEnableNow();
2698 if (!Serializer::enabled() && !emit_debug_code()) {
2702 RelocInfo rinfo(pc_, rmode, data, NULL);
2703 reloc_info_writer.Write(&rinfo);
2707 #ifdef GENERATED_CODE_COVERAGE
2708 static FILE* coverage_log = NULL;
2711 static void InitCoverageLog() {
2712 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
2713 if (file_name != NULL) {
2714 coverage_log = fopen(file_name, "aw+");
2719 void LogGeneratedCodeCoverage(const char* file_line) {
2720 const char* return_address = (&file_line)[-1];
2721 char* push_insn = const_cast<char*>(return_address - 12);
2722 push_insn[0] = 0xeb; // Relative branch insn.
2723 push_insn[1] = 13; // Skip over coverage insns.
2724 if (coverage_log != NULL) {
2725 fprintf(coverage_log, "%s\n", file_line);
2726 fflush(coverage_log);
2732 } } // namespace v8::internal
2734 #endif // V8_TARGET_ARCH_IA32