1 // Protocol Buffers - Google's data interchange format
2 // Copyright 2012 Google Inc. All rights reserved.
3 // http://code.google.com/p/protobuf/
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6 // modification, are permitted provided that the following conditions are
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31 // This file is an internal atomic implementation, use atomicops.h instead.
33 #ifndef GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_MIPS_GCC_H_
34 #define GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_MIPS_GCC_H_
36 #define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
42 // Atomically execute:
44 // if (*ptr == old_value)
48 // I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value".
49 // Always return the old value of "*ptr"
51 // This routine implies no memory barriers.
52 inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
56 __asm__ __volatile__(".set push\n"
59 "ll %0, %5\n" // prev = *ptr
60 "bne %0, %3, 2f\n" // if (prev != old_value) goto 2
61 "move %2, %4\n" // tmp = new_value
62 "sc %2, %1\n" // *ptr = tmp (with atomic check)
63 "beqz %2, 1b\n" // start again on atomic error
64 "nop\n" // delay slot nop
67 : "=&r" (prev), "=m" (*ptr), "=&r" (tmp)
68 : "Ir" (old_value), "r" (new_value), "m" (*ptr)
73 // Atomically store new_value into *ptr, returning the previous value held in
74 // *ptr. This routine implies no memory barriers.
75 inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
78 __asm__ __volatile__(".set push\n"
81 "ll %1, %4\n" // old = *ptr
82 "move %0, %3\n" // temp = new_value
83 "sc %0, %2\n" // *ptr = temp (with atomic check)
84 "beqz %0, 1b\n" // start again on atomic error
85 "nop\n" // delay slot nop
87 : "=&r" (temp), "=&r" (old), "=m" (*ptr)
88 : "r" (new_value), "m" (*ptr)
94 // Atomically increment *ptr by "increment". Returns the new value of
95 // *ptr with the increment applied. This routine implies no memory barriers.
96 inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
100 __asm__ __volatile__(".set push\n"
103 "ll %0, %4\n" // temp = *ptr
104 "addu %1, %0, %3\n" // temp2 = temp + increment
105 "sc %1, %2\n" // *ptr = temp2 (with atomic check)
106 "beqz %1, 1b\n" // start again on atomic error
107 "addu %1, %0, %3\n" // temp2 = temp + increment
109 : "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
110 : "Ir" (increment), "m" (*ptr)
112 // temp2 now holds the final value.
116 inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
117 Atomic32 increment) {
118 ATOMICOPS_COMPILER_BARRIER();
119 Atomic32 res = NoBarrier_AtomicIncrement(ptr, increment);
120 ATOMICOPS_COMPILER_BARRIER();
124 // "Acquire" operations
125 // ensure that no later memory access can be reordered ahead of the operation.
126 // "Release" operations ensure that no previous memory access can be reordered
127 // after the operation. "Barrier" operations have both "Acquire" and "Release"
128 // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
130 inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
132 Atomic32 new_value) {
133 ATOMICOPS_COMPILER_BARRIER();
134 Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
135 ATOMICOPS_COMPILER_BARRIER();
139 inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
141 Atomic32 new_value) {
142 ATOMICOPS_COMPILER_BARRIER();
143 Atomic32 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
144 ATOMICOPS_COMPILER_BARRIER();
148 inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
152 inline void MemoryBarrier() {
153 __asm__ __volatile__("sync" : : : "memory");
156 inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
161 inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
166 inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
170 inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
171 Atomic32 value = *ptr;
176 inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
181 #if defined(__LP64__)
182 // 64-bit versions of the atomic ops.
184 inline Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
186 Atomic64 new_value) {
188 __asm__ __volatile__(".set push\n"
191 "lld %0, %5\n" // prev = *ptr
192 "bne %0, %3, 2f\n" // if (prev != old_value) goto 2
193 "move %2, %4\n" // tmp = new_value
194 "scd %2, %1\n" // *ptr = tmp (with atomic check)
195 "beqz %2, 1b\n" // start again on atomic error
196 "nop\n" // delay slot nop
199 : "=&r" (prev), "=m" (*ptr), "=&r" (tmp)
200 : "Ir" (old_value), "r" (new_value), "m" (*ptr)
205 // Atomically store new_value into *ptr, returning the previous value held in
206 // *ptr. This routine implies no memory barriers.
207 inline Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr,
208 Atomic64 new_value) {
210 __asm__ __volatile__(".set push\n"
213 "lld %1, %4\n" // old = *ptr
214 "move %0, %3\n" // temp = new_value
215 "scd %0, %2\n" // *ptr = temp (with atomic check)
216 "beqz %0, 1b\n" // start again on atomic error
217 "nop\n" // delay slot nop
219 : "=&r" (temp), "=&r" (old), "=m" (*ptr)
220 : "r" (new_value), "m" (*ptr)
226 // Atomically increment *ptr by "increment". Returns the new value of
227 // *ptr with the increment applied. This routine implies no memory barriers.
228 inline Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr,
229 Atomic64 increment) {
230 Atomic64 temp, temp2;
232 __asm__ __volatile__(".set push\n"
235 "lld %0, %4\n" // temp = *ptr
236 "daddu %1, %0, %3\n" // temp2 = temp + increment
237 "scd %1, %2\n" // *ptr = temp2 (with atomic check)
238 "beqz %1, 1b\n" // start again on atomic error
239 "daddu %1, %0, %3\n" // temp2 = temp + increment
241 : "=&r" (temp), "=&r" (temp2), "=m" (*ptr)
242 : "Ir" (increment), "m" (*ptr)
244 // temp2 now holds the final value.
248 inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
249 Atomic64 increment) {
251 Atomic64 res = NoBarrier_AtomicIncrement(ptr, increment);
256 // "Acquire" operations
257 // ensure that no later memory access can be reordered ahead of the operation.
258 // "Release" operations ensure that no previous memory access can be reordered
259 // after the operation. "Barrier" operations have both "Acquire" and "Release"
260 // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory
262 inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
264 Atomic64 new_value) {
265 Atomic64 res = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
270 inline Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
272 Atomic64 new_value) {
274 return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
277 inline void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value) {
281 inline void Acquire_Store(volatile Atomic64* ptr, Atomic64 value) {
286 inline void Release_Store(volatile Atomic64* ptr, Atomic64 value) {
291 inline Atomic64 NoBarrier_Load(volatile const Atomic64* ptr) {
295 inline Atomic64 Acquire_Load(volatile const Atomic64* ptr) {
296 Atomic64 value = *ptr;
301 inline Atomic64 Release_Load(volatile const Atomic64* ptr) {
307 } // namespace internal
308 } // namespace protobuf
309 } // namespace google
311 #undef ATOMICOPS_COMPILER_BARRIER
313 #endif // GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_MIPS_GCC_H_