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5 * Permission is hereby granted, free of charge, to any person obtaining a
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53 * Solaris devfs interfaces
60 #include <sys/types.h>
65 #include <libdevinfo.h>
66 #include "pci_tools.h"
68 #include "pciaccess.h"
69 #include "pciaccess_private.h"
71 #define MAX_DEVICES 256
72 #define CELL_NUMS_1275 (sizeof(pci_regspec_t) / sizeof(uint_t))
75 uint8_t bytes[16 * sizeof (uint32_t)];
79 typedef struct i_devnode {
86 typedef struct nexus {
92 static nexus_t *nexus_list = NULL;
93 static int num_domains = 0;
94 static int xsvc_fd = -1;
97 * Read config space in native processor endianness. Endian-neutral
98 * processing can then take place. On big endian machines, MSB and LSB
99 * of little endian data end up switched if read as little endian.
100 * They are in correct order if read as big endian.
103 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG
105 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL
107 # error "ISA is neither __sparc nor __x86"
111 * Identify problematic southbridges. These have device id 0x5249 and
112 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well.
113 * Values are little endian, so they are reversed for SPARC.
115 * Check for these southbridges on all architectures, as the issue is a
116 * southbridge issue, independent of processor.
118 * If one of these is found during probing, skip probing other devs/funcs on
119 * the rest of the bus, since the southbridge and all devs underneath will
120 * otherwise disappear.
122 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG)
123 # define U45_SB_DEVID_VID 0xb9104952
124 # define U45_SB_CLASS_RID 0x00000406
126 # define U45_SB_DEVID_VID 0x524910b9
127 # define U45_SB_CLASS_RID 0x06040000
133 static int pci_device_solx_devfs_map_range(struct pci_device *dev,
134 struct pci_device_mapping *map);
136 static int pci_device_solx_devfs_read_rom( struct pci_device * dev,
139 static int pci_device_solx_devfs_probe( struct pci_device * dev );
141 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data,
142 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read );
144 static int pci_device_solx_devfs_write( struct pci_device * dev,
145 const void * data, pciaddr_t offset, pciaddr_t size,
146 pciaddr_t * bytes_written );
148 static int probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p,
149 struct pci_system *pci_sys);
151 static int do_probe(nexus_t *nexus, struct pci_system *pci_sys);
153 static int probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg);
155 static void pci_system_solx_devfs_destroy( void );
157 static int get_config_header(int fd, uint8_t bus_no, uint8_t dev_no,
158 uint8_t func_no, pci_conf_hdr_t *config_hdr_p);
160 int pci_system_solx_devfs_create( void );
162 static const struct pci_system_methods solx_devfs_methods = {
163 .destroy = pci_system_solx_devfs_destroy,
164 .destroy_device = NULL,
165 .read_rom = pci_device_solx_devfs_read_rom,
166 .probe = pci_device_solx_devfs_probe,
167 .map_range = pci_device_solx_devfs_map_range,
168 .unmap_range = pci_device_generic_unmap_range,
170 .read = pci_device_solx_devfs_read,
171 .write = pci_device_solx_devfs_write,
173 .fill_capabilities = pci_fill_capabilities_generic
177 find_nexus_for_domain( int domain )
181 for (nexus = nexus_list ; nexus != NULL ; nexus = nexus->next) {
182 if (nexus->domain == domain) {
189 #define GET_CONFIG_VAL_8(offset) (config_hdr.bytes[offset])
190 #define GET_CONFIG_VAL_16(offset) \
191 (uint16_t) (GET_CONFIG_VAL_8(offset) + (GET_CONFIG_VAL_8(offset+1) << 8))
192 #define GET_CONFIG_VAL_32(offset) \
193 (uint32_t) (GET_CONFIG_VAL_8(offset) + \
194 (GET_CONFIG_VAL_8(offset+1) << 8) + \
195 (GET_CONFIG_VAL_8(offset+2) << 16) + \
196 (GET_CONFIG_VAL_8(offset+3) << 24))
199 * Release all the resources
203 pci_system_solx_devfs_destroy( void )
206 * The memory allocated for pci_sys & devices in create routines
207 * will be freed in pci_system_cleanup.
208 * Need to free system-specific allocations here.
210 nexus_t *nexus, *next;
212 for (nexus = nexus_list ; nexus != NULL ; nexus = next) {
226 * Attempt to access PCI subsystem using Solaris's devfs interface.
230 pci_system_solx_devfs_create( void )
236 if (nexus_list != NULL) {
241 * Only allow MAX_DEVICES exists
242 * I will fix it later to get
243 * the total devices first
245 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) {
246 pci_sys->methods = &solx_devfs_methods;
248 if ((pci_sys->devices =
249 calloc(MAX_DEVICES, sizeof (struct pci_device_private)))
252 if ((di_node = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
254 (void) fprintf(stderr, "di_init() failed: %s\n",
257 (void) di_walk_minor(di_node, DDI_NT_REGACC, 0, pci_sys,
270 if (pci_sys != NULL) {
271 free(pci_sys->devices);
281 * Retrieve first 16 dwords of device's config header, except for the first
282 * dword. First 16 dwords are defined by the PCI specification.
285 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
286 pci_conf_hdr_t *config_hdr_p)
288 pcitool_reg_t cfg_prg;
292 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */
294 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
295 cfg_prg.bus_no = bus_no;
296 cfg_prg.dev_no = dev_no;
297 cfg_prg.func_no = func_no;
299 cfg_prg.user_version = PCITOOL_USER_VERSION;
301 /* Get dwords 1-15 of config space. They must be read as uint32_t. */
302 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) {
303 cfg_prg.offset += sizeof (uint32_t);
304 if ((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
307 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data;
315 * Probe device's functions. Modifies many fields in the prg_p.
318 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys)
320 pci_conf_hdr_t config_hdr;
321 boolean_t multi_function_device;
323 int8_t first_func = 0;
324 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT;
326 struct pci_device * pci_base;
329 * Loop through at least func=first_func. Continue looping through
330 * functions if there are no errors and the device is a multi-function
333 * (Note, if first_func == 0, header will show whether multifunction
334 * device and set multi_function_device. If first_func != 0, then we
335 * will force the loop as the user wants a specific function to be
338 for (func = first_func, multi_function_device = B_FALSE;
339 ((func <= last_func) &&
340 ((func == first_func) || (multi_function_device)));
342 prg_p->func_no = func;
345 * Four things can happen here:
347 * 1) ioctl comes back as EFAULT and prg_p->status is
348 * PCITOOL_INVALID_ADDRESS. There is no device at this location.
350 * 2) ioctl comes back successful and the data comes back as
351 * zero. Config space is mapped but no device responded.
353 * 3) ioctl comes back successful and the data comes back as
354 * non-zero. We've found a device.
356 * 4) Some other error occurs in an ioctl.
359 prg_p->status = PCITOOL_SUCCESS;
362 prg_p->user_version = PCITOOL_USER_VERSION;
365 if (((rval = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) ||
366 (prg_p->data == 0xffffffff)) {
369 * Accept errno == EINVAL along with status of
370 * PCITOOL_OUT_OF_RANGE because some systems
371 * don't implement the full range of config space.
372 * Leave the loop quietly in this case.
374 if ((errno == EINVAL) ||
375 (prg_p->status == PCITOOL_OUT_OF_RANGE)) {
380 * Exit silently with ENXIO as this means that there are
381 * no devices under the pci root nexus.
383 else if ((errno == ENXIO) &&
384 (prg_p->status == PCITOOL_IO_ERROR)) {
389 * Expect errno == EFAULT along with status of
390 * PCITOOL_INVALID_ADDRESS because there won't be
391 * devices at each stop. Quit on any other error.
393 else if (((errno != EFAULT) ||
394 (prg_p->status != PCITOOL_INVALID_ADDRESS)) &&
395 (prg_p->data != 0xffffffff)) {
400 * If no function at this location,
401 * just advance to the next function.
408 * Data came back as 0.
409 * Treat as unresponsive device and check next device.
411 } else if (prg_p->data == 0) {
413 break; /* Func loop. */
415 /* Found something. */
417 config_hdr.dwords[0] = (uint32_t)prg_p->data;
419 /* Get the rest of the PCI header. */
420 if ((rval = get_config_header(nexus->fd, prg_p->bus_no,
421 prg_p->dev_no, prg_p->func_no,
422 &config_hdr)) != 0) {
427 * Special case for the type of Southbridge found on
428 * Ultra-45 and other sun4u fire workstations.
430 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) &&
431 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) {
437 * Found one device with bus number, device number and
441 pci_base = &pci_sys->devices[pci_sys->num_devices].base;
444 * Domain is peer bus??
446 pci_base->domain = nexus->domain;
447 pci_base->bus = prg_p->bus_no;
448 pci_base->dev = prg_p->dev_no;
449 pci_base->func = func;
452 * for the format of device_class, see struct pci_device;
455 pci_base->device_class =
456 (GET_CONFIG_VAL_8(PCI_CONF_BASCLASS) << 16) |
457 (GET_CONFIG_VAL_8(PCI_CONF_SUBCLASS) << 8) |
458 GET_CONFIG_VAL_8(PCI_CONF_PROGCLASS);
460 pci_base->revision = GET_CONFIG_VAL_8(PCI_CONF_REVID);
461 pci_base->vendor_id = GET_CONFIG_VAL_16(PCI_CONF_VENID);
462 pci_base->device_id = GET_CONFIG_VAL_16(PCI_CONF_DEVID);
463 pci_base->subvendor_id = GET_CONFIG_VAL_16(PCI_CONF_SUBVENID);
464 pci_base->subdevice_id = GET_CONFIG_VAL_16(PCI_CONF_SUBSYSID);
466 pci_sys->devices[pci_sys->num_devices].header_type
467 = GET_CONFIG_VAL_8(PCI_CONF_HEADER);
470 fprintf(stderr, "busno = %x, devno = %x, funcno = %x\n",
471 prg_p->bus_no, prg_p->dev_no, func);
474 pci_sys->num_devices++;
477 * Accommodate devices which state their
478 * multi-functionality only in their function 0 config
479 * space. Note multi-functionality throughout probing
480 * of all of this device's functions.
482 if (config_hdr.bytes[PCI_CONF_HEADER] & PCI_HEADER_MULTI) {
483 multi_function_device = B_TRUE;
492 * This function is called from di_walk_minor() when any PROBE is processed
495 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg)
497 struct pci_system *pci_sys = (struct pci_system *) arg;
501 char nexus_path[MAXPATHLEN];
503 nexus = calloc(1, sizeof(nexus_t));
505 (void) fprintf(stderr, "Error allocating memory for nexus: %s\n",
507 return DI_WALK_TERMINATE;
510 nexus_name = di_devfs_minor_path(minor);
511 if (nexus_name == NULL) {
512 (void) fprintf(stderr, "Error getting nexus path: %s\n",
515 return (DI_WALK_CONTINUE);
518 snprintf(nexus_path, sizeof(nexus_path), "/devices%s", nexus_name);
519 di_devfs_path_free(nexus_name);
521 if ((fd = open(nexus_path, O_RDWR)) >= 0) {
523 nexus->domain = num_domains++;
524 if ((do_probe(nexus, pci_sys) != 0) && (errno != ENXIO)) {
525 (void) fprintf(stderr, "Error probing node %s: %s\n",
526 nexus_path, strerror(errno));
530 nexus->next = nexus_list;
534 (void) fprintf(stderr, "Error opening %s: %s\n",
535 nexus_path, strerror(errno));
539 return DI_WALK_CONTINUE;
545 * Probe a given nexus config space for devices.
547 * fd is the file descriptor of the nexus.
548 * input_args contains commandline options as specified by the user.
551 do_probe(nexus_t *nexus, struct pci_system *pci_sys)
556 uint32_t last_bus = PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT;
557 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;
558 uint8_t first_bus = 0;
559 uint8_t first_dev = 0;
562 prg.barnum = 0; /* Config space. */
564 /* Must read in 4-byte quantities. */
565 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
570 * Loop through all valid bus / dev / func combinations to check for
571 * all devices, with the following exceptions:
573 * When nothing is found at function 0 of a bus / dev combination, skip
574 * the other functions of that bus / dev combination.
576 * When a found device's function 0 is probed and it is determined that
577 * it is not a multifunction device, skip probing of that device's
580 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) {
581 prg.bus_no = (uint8_t)bus;
583 for (dev = first_dev; ((dev <= last_dev) && (rval == 0)); dev++) {
585 rval = probe_dev(nexus, &prg, pci_sys);
589 * Ultra-45 southbridge workaround:
590 * ECANCELED tells to skip to the next bus.
592 if (rval == ECANCELED) {
596 if (pci_sys->num_devices > MAX_DEVICES) {
597 (void) fprintf(stderr, "pci devices reach maximum number\n");
604 find_target_node(di_node_t node, void *arg)
608 uint32_t busno, funcno, devno;
609 i_devnode_t *devnode;
610 void *prop = DI_PROP_NIL;
613 devnode = (i_devnode_t *)arg;
616 * Test the property functions, only for testing
619 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid);
620 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) {
621 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop));
623 if (!strcmp(di_prop_name(prop), "reg")) {
624 len = di_prop_ints(prop, ®buf);
626 for (i = 0; i < len; i++) {
627 fprintf(stderr, "0x%0x.", regbuf[i]);
629 fprintf(stderr, "\n");
631 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid);
634 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg", ®buf);
638 fprintf(stderr, "error = %x\n", errno);
639 fprintf(stderr, "can not find assigned-address\n");
641 return (DI_WALK_CONTINUE);
644 busno = PCI_REG_BUS_G(regbuf[0]);
645 devno = PCI_REG_DEV_G(regbuf[0]);
646 funcno = PCI_REG_FUNC_G(regbuf[0]);
648 if ((busno == devnode->bus) &&
649 (devno == devnode->dev) &&
650 (funcno == devnode->func)) {
651 devnode->node = node;
653 return (DI_WALK_TERMINATE);
656 return (DI_WALK_CONTINUE);
663 pci_device_solx_devfs_probe( struct pci_device * dev )
675 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
676 args.node = DI_NODE_NIL;
679 struct pci_device_private *priv =
680 (struct pci_device_private *) dev;
682 dev->vendor_id = (uint16_t)config[0] + ((uint16_t)config[1] << 8);
683 dev->device_id = (uint16_t)config[2] + ((uint16_t)config[3] << 8);
684 dev->device_class = (uint32_t)config[9] +
685 ((uint32_t)config[10] << 8) +
686 ((uint16_t)config[11] << 16);
689 * device class code is already there.
690 * see probe_dev function.
692 dev->revision = config[8];
693 dev->subvendor_id = (uint16_t)config[44] + ((uint16_t)config[45] << 8);
694 dev->subdevice_id = (uint16_t)config[46] + ((uint16_t)config[47] << 8);
695 dev->irq = config[60];
697 priv->header_type = config[14];
699 * starting to find if it is MEM/MEM64/IO
702 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
704 (void) fprintf(stderr, "di_init failed: %s\n", strerror(errno));
708 args.func = dev->func;
709 (void) di_walk_node(rnode, DI_WALK_CLDFIRST,
710 (void *)&args, find_target_node);
714 if (args.node != DI_NODE_NIL) {
716 * It will succeed for sure, because it was
717 * successfully called in find_target_node
719 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node,
720 "assigned-addresses",
730 * how to find the size of rom???
731 * if the device has expansion rom,
732 * it must be listed in the last
733 * cells because solaris find probe
734 * the base address from offset 0x10
735 * to 0x30h. So only check the last
738 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275];
739 if (PCI_REG_REG_G(reg->pci_phys_hi) == PCI_CONF_ROM) {
741 * rom can only be 32 bits
743 dev->rom_size = reg->pci_size_low;
744 len = len - CELL_NUMS_1275;
748 * size default to 64K and base address
751 dev->rom_size = 0x10000;
755 * solaris has its own BAR index. To be sure that
756 * Xorg has the same BAR number as solaris. ????
758 for (i = 0; i < len; i = i + CELL_NUMS_1275) {
759 int ent = i/CELL_NUMS_1275;
761 reg = (pci_regspec_t *)®buf[i];
764 * non relocatable resource is excluded
765 * such like 0xa0000, 0x3b0. If it is met,
766 * the loop is broken;
768 if (!PCI_REG_REG_G(reg->pci_phys_hi))
771 if (reg->pci_phys_hi & PCI_PREFETCH_B) {
772 dev->regions[ent].is_prefetchable = 1;
775 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
777 dev->regions[ent].is_IO = 1;
782 dev->regions[ent].is_64 = 1;
787 * We split the shift count 32 into two 16 to
788 * avoid the complaining of the compiler
790 dev->regions[ent].base_addr = reg->pci_phys_low +
791 ((reg->pci_phys_mid << 16) << 16);
792 dev->regions[ent].size = reg->pci_size_low +
793 ((reg->pci_size_hi << 16) << 16);
800 * Solaris version: read the VGA ROM data
803 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer )
806 struct pci_device_mapping prom = {
808 .size = dev->rom_size,
812 err = pci_device_solx_devfs_map_range(dev, &prom);
814 (void) bcopy(prom.memory, buffer, dev->rom_size);
816 if (munmap(prom.memory, dev->rom_size) == -1) {
824 * solaris version: Read the configurations space of the devices
827 pci_device_solx_devfs_read( struct pci_device * dev, void * data,
828 pciaddr_t offset, pciaddr_t size,
829 pciaddr_t * bytes_read )
831 pcitool_reg_t cfg_prg;
834 nexus_t *nexus = find_nexus_for_domain(dev->domain);
838 if ( nexus == NULL ) {
842 cfg_prg.offset = offset;
843 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
844 cfg_prg.bus_no = dev->bus;
845 cfg_prg.dev_no = dev->dev;
846 cfg_prg.func_no = dev->func;
848 cfg_prg.user_version = PCITOOL_USER_VERSION;
850 for (i = 0; i < size; i += PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1))
852 cfg_prg.offset = offset + i;
854 if ((err = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
855 fprintf(stderr, "read bdf<%x,%x,%x,%llx> config space failure\n",
860 fprintf(stderr, "Failure cause = %x\n", err);
864 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data;
866 * DWORDS Offset or bytes Offset ??
878 pci_device_solx_devfs_write( struct pci_device * dev, const void * data,
879 pciaddr_t offset, pciaddr_t size,
880 pciaddr_t * bytes_written )
882 pcitool_reg_t cfg_prg;
885 nexus_t *nexus = find_nexus_for_domain(dev->domain);
887 if ( bytes_written != NULL ) {
891 if ( nexus == NULL ) {
895 cfg_prg.offset = offset;
898 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
901 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN;
904 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
907 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN;
912 cfg_prg.bus_no = dev->bus;
913 cfg_prg.dev_no = dev->dev;
914 cfg_prg.func_no = dev->func;
916 cfg_prg.user_version = PCITOOL_USER_VERSION;
917 cfg_prg.data = *((uint64_t *)data);
920 * Check if this device is bridge device.
921 * If it is, it is also a nexus node???
922 * It seems that there is no explicit
923 * PCI nexus device for X86, so not applicable
924 * from pcitool_bus_reg_ops in pci_tools.c
926 cmd = PCITOOL_DEVICE_SET_REG;
928 if ((err = ioctl(nexus->fd, cmd, &cfg_prg)) != 0) {
931 *bytes_written = size;
938 * Map a memory region for a device using /dev/xsvc.
940 * \param dev Device whose memory region is to be mapped.
941 * \param map Parameters of the mapping that is to be created.
944 * Zero on success or an \c errno value on failure.
947 pci_device_solx_devfs_map_range(struct pci_device *dev,
948 struct pci_device_mapping *map)
950 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
951 ? (PROT_READ | PROT_WRITE) : PROT_READ;
955 * Still used xsvc to do the user space mapping
958 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
960 (void) fprintf(stderr, "can not open /dev/xsvc: %s\n",
966 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd, map->base);
967 if (map->memory == MAP_FAILED) {
970 (void) fprintf(stderr, "map rom region =%llx failed: %s\n",
971 map->base, strerror(errno));