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5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
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53 * Solaris devfs interfaces
60 #include <sys/types.h>
68 #include <libdevinfo.h>
69 #include "pci_tools.h"
71 #include "pciaccess.h"
72 #include "pciaccess_private.h"
74 #define MAX_DEVICES 256
75 #define CELL_NUMS_1275 (sizeof(pci_regspec_t)/sizeof(uint_t))
77 uint8_t bytes[16 * sizeof (uint32_t)];
81 typedef struct i_devnode {
88 typedef struct nexus {
94 static nexus_t *nexus_list = NULL;
95 static int num_domains = 0;
96 static int xsvc_fd = -1;
98 * Read config space in native processor endianness. Endian-neutral
99 * processing can then take place. On big endian machines, MSB and LSB
100 * of little endian data end up switched if read as little endian.
101 * They are in correct order if read as big endian.
104 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG
106 #define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL
108 #error "ISA is neither __sparc nor __x86"
112 * Identify problematic southbridges. These have device id 0x5249 and
113 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well.
114 * Values are little endian, so they are reversed for SPARC.
116 * Check for these southbridges on all architectures, as the issue is a
117 * southbridge issue, independent of processor.
119 * If one of these is found during probing, skip probing other devs/funcs on
120 * the rest of the bus, since the southbridge and all devs underneath will
121 * otherwise disappear.
123 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG)
124 #define U45_SB_DEVID_VID 0xb9104952
125 #define U45_SB_CLASS_RID 0x00000406
127 #define U45_SB_DEVID_VID 0x524910b9
128 #define U45_SB_CLASS_RID 0x06040000
134 static int pci_device_solx_devfs_map_range(struct pci_device *dev,
135 struct pci_device_mapping *map);
137 static int pci_device_solx_devfs_read_rom( struct pci_device * dev,
140 static int pci_device_solx_devfs_probe( struct pci_device * dev );
142 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data,
143 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read );
145 static int pci_device_solx_devfs_write( struct pci_device * dev,
146 const void * data, pciaddr_t offset, pciaddr_t size,
147 pciaddr_t * bytes_written );
150 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys);
153 do_probe(nexus_t *nexus, struct pci_system *pci_sys);
156 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg);
159 pci_system_solx_devfs_destroy( void );
162 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
163 pci_conf_hdr_t *config_hdr_p);
166 pci_system_solx_devfs_create( void );
171 static const struct pci_system_methods solx_devfs_methods = {
172 .destroy = pci_system_solx_devfs_destroy,
173 .destroy_device = NULL,
174 .read_rom = pci_device_solx_devfs_read_rom,
175 .probe = pci_device_solx_devfs_probe,
176 .map_range = pci_device_solx_devfs_map_range,
177 .unmap_range = pci_device_generic_unmap_range,
179 .read = pci_device_solx_devfs_read,
180 .write = pci_device_solx_devfs_write,
182 .fill_capabilities = pci_fill_capabilities_generic
186 find_nexus_for_domain( int domain )
190 for (nexus = nexus_list ; nexus != NULL ; nexus = nexus->next) {
191 if (nexus->domain == domain) {
199 get_config_hdr_value(pci_conf_hdr_t *config_hdr_p, uint16_t offset,
205 value = (value << 8) + config_hdr_p->bytes[offset + size];
211 #define GET_CONFIG_VAL_8(offset) \
212 (config_hdr.bytes[offset])
213 #define GET_CONFIG_VAL_16(offset) \
214 (uint16_t)get_config_hdr_value(&config_hdr, offset, 2)
215 #define GET_CONFIG_VAL_32(offset) \
216 (uint32_t)get_config_hdr_value(&config_hdr, offset, 4)
219 * Release all the resources
223 pci_system_solx_devfs_destroy( void )
226 * the memory allocated in create routines
227 * will be freed in pci_system_init
228 * It is more reasonable to free them here
230 nexus_t *nexus, *next;
231 for (nexus = nexus_list ; nexus != NULL ; nexus = next) {
246 * Attempt to access PCI subsystem using Solaris's devfs interface.
250 pci_system_solx_devfs_create( void )
256 if (nexus_list != NULL) {
261 * Only allow MAX_DEVICES exists
262 * I will fix it later to get
263 * the total devices first
265 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) {
266 pci_sys->methods = &solx_devfs_methods;
267 if ((pci_sys->devices =
268 calloc(MAX_DEVICES, sizeof (struct pci_device_private)))
270 if ((di_node = di_init("/", DINFOCPYALL))
273 (void) fprintf(stderr,
274 "di_init() failed: %s\n",
277 (void) di_walk_minor(di_node, DDI_NT_REGACC,
291 if (pci_sys != NULL) {
292 free(pci_sys->devices);
302 * Retrieve first 16 dwords of device's config header, except for the first
303 * dword. First 16 dwords are defined by the PCI specification.
306 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
307 pci_conf_hdr_t *config_hdr_p)
309 pcitool_reg_t cfg_prg;
313 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */
315 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
316 cfg_prg.bus_no = bus_no;
317 cfg_prg.dev_no = dev_no;
318 cfg_prg.func_no = func_no;
320 cfg_prg.user_version = PCITOOL_USER_VERSION;
322 /* Get dwords 1-15 of config space. They must be read as uint32_t. */
323 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) {
324 cfg_prg.offset += sizeof (uint32_t);
326 ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
329 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data;
337 * Probe device's functions. Modifies many fields in the prg_p.
340 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys)
342 pci_conf_hdr_t config_hdr;
343 boolean_t multi_function_device;
345 int8_t first_func = 0;
346 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT;
348 struct pci_device *pci_base;
351 * Loop through at least func=first_func. Continue looping through
352 * functions if there are no errors and the device is a multi-function
355 * (Note, if first_func == 0, header will show whether multifunction
356 * device and set multi_function_device. If first_func != 0, then we
357 * will force the loop as the user wants a specific function to be
360 for (func = first_func, multi_function_device = B_FALSE;
361 ((func <= last_func) &&
362 ((func == first_func) || (multi_function_device)));
364 prg_p->func_no = func;
367 * Four things can happen here:
369 * 1) ioctl comes back as EFAULT and prg_p->status is
370 * PCITOOL_INVALID_ADDRESS. There is no device at this
373 * 2) ioctl comes back successful and the data comes back as
374 * zero. Config space is mapped but no device responded.
376 * 3) ioctl comes back successful and the data comes back as
377 * non-zero. We've found a device.
379 * 4) Some other error occurs in an ioctl.
382 prg_p->status = PCITOOL_SUCCESS;
385 prg_p->user_version = PCITOOL_USER_VERSION;
386 if (((rval = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) ||
387 (prg_p->data == 0xffffffff)) {
390 * Accept errno == EINVAL along with status of
391 * PCITOOL_OUT_OF_RANGE because some systems
392 * don't implement the full range of config space.
393 * Leave the loop quietly in this case.
395 if ((errno == EINVAL) ||
396 (prg_p->status == PCITOOL_OUT_OF_RANGE)) {
401 * Exit silently with ENXIO as this means that there are
402 * no devices under the pci root nexus.
404 else if ((errno == ENXIO) &&
405 (prg_p->status == PCITOOL_IO_ERROR)) {
410 * Expect errno == EFAULT along with status of
411 * PCITOOL_INVALID_ADDRESS because there won't be
412 * devices at each stop. Quit on any other error.
414 else if (((errno != EFAULT) ||
415 (prg_p->status != PCITOOL_INVALID_ADDRESS)) &&
416 (prg_p->data != 0xffffffff)) {
421 * If no function at this location,
422 * just advance to the next function.
429 * Data came back as 0.
430 * Treat as unresponsive device and check next device.
432 } else if (prg_p->data == 0) {
434 break; /* Func loop. */
436 /* Found something. */
438 config_hdr.dwords[0] = (uint32_t)prg_p->data;
440 /* Get the rest of the PCI header. */
441 if ((rval = get_config_header(nexus->fd, prg_p->bus_no,
442 prg_p->dev_no, prg_p->func_no, &config_hdr)) !=
448 * Special case for the type of Southbridge found on
449 * Ultra-45 and other sun4u fire workstations.
451 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) &&
452 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) {
458 * Found one device with bus number, device number and
463 &pci_sys->devices[pci_sys->num_devices].base;
466 * Domain is peer bus??
468 pci_base->domain = nexus->domain;
469 pci_base->bus = prg_p->bus_no;
470 pci_base->dev = prg_p->dev_no;
471 pci_base->func = func;
473 * for the format of device_class, see struct pci_device;
475 pci_base->device_class =
476 (GET_CONFIG_VAL_8(PCI_CONF_BASCLASS) << 16) |
477 (GET_CONFIG_VAL_8(PCI_CONF_SUBCLASS) << 8) |
478 GET_CONFIG_VAL_8(PCI_CONF_PROGCLASS);
480 GET_CONFIG_VAL_8(PCI_CONF_REVID);
481 pci_base->vendor_id =
482 GET_CONFIG_VAL_16(PCI_CONF_VENID);
483 pci_base->device_id =
484 GET_CONFIG_VAL_16(PCI_CONF_DEVID);
485 pci_base->subvendor_id =
486 GET_CONFIG_VAL_16(PCI_CONF_SUBVENID);
487 pci_base->subdevice_id =
488 GET_CONFIG_VAL_16(PCI_CONF_SUBSYSID);
490 pci_sys->devices[pci_sys->num_devices].header_type =
491 GET_CONFIG_VAL_8(PCI_CONF_HEADER);
493 fprintf(stderr, "busno = %x, devno = %x, funcno = %x\n",
494 prg_p->bus_no, prg_p->dev_no, func);
497 pci_sys->num_devices++;
500 * Accommodate devices which state their
501 * multi-functionality only in their function 0 config
502 * space. Note multi-functionality throughout probing
503 * of all of this device's functions.
505 if (config_hdr.bytes[PCI_CONF_HEADER] &
507 multi_function_device = B_TRUE;
516 * This function is called from di_walk_minor() when any PROBE is processed
519 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg)
521 struct pci_system *pci_sys = (struct pci_system *) arg;
525 char nexus_path[MAXPATHLEN];
527 nexus = calloc(1, sizeof(nexus_t));
529 (void) fprintf(stderr,
530 "Error allocating memory for nexus: %s\n",
532 return DI_WALK_TERMINATE;
535 nexus_name = di_devfs_minor_path(minor);
536 if (nexus_name == NULL) {
537 (void) fprintf(stderr, "Error getting nexus path: %s\n",
540 return (DI_WALK_CONTINUE);
543 snprintf(nexus_path, sizeof(nexus_path), "/devices%s", nexus_name);
545 if ((fd = open(nexus_path, O_RDWR)) >= 0) {
547 nexus->domain = num_domains++;
548 if ((do_probe(nexus, pci_sys) != 0) && (errno != ENXIO)) {
549 (void) fprintf(stderr, "Error probing node %s: %s\n",
550 nexus_path, strerror(errno));
554 nexus->next = nexus_list;
558 (void) fprintf(stderr, "Error opening %s: %s\n",
559 nexus_path, strerror(errno));
562 di_devfs_path_free(nexus_name);
564 return DI_WALK_CONTINUE;
570 * Probe a given nexus config space for devices.
572 * fd is the file descriptor of the nexus.
573 * input_args contains commandline options as specified by the user.
576 do_probe(nexus_t *nexus, struct pci_system *pci_sys)
581 uint32_t last_bus = PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT;
582 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;
583 uint8_t first_bus = 0;
584 uint8_t first_dev = 0;
587 prg.barnum = 0; /* Config space. */
589 /* Must read in 4-byte quantities. */
590 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
595 * Loop through all valid bus / dev / func combinations to check for
596 * all devices, with the following exceptions:
598 * When nothing is found at function 0 of a bus / dev combination, skip
599 * the other functions of that bus / dev combination.
601 * When a found device's function 0 is probed and it is determined that
602 * it is not a multifunction device, skip probing of that device's
605 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) {
606 prg.bus_no = (uint8_t)bus;
607 for (dev = first_dev;
608 ((dev <= last_dev) && (rval == 0)); dev++) {
610 rval = probe_dev(nexus, &prg, pci_sys);
614 * Ultra-45 southbridge workaround:
615 * ECANCELED tells to skip to the next bus.
617 if (rval == ECANCELED) {
621 if (pci_sys->num_devices > MAX_DEVICES) {
622 (void) fprintf(stderr, "pci devices reach maximum number\n");
629 find_target_node(di_node_t node, void *arg)
633 uint32_t busno, funcno, devno;
634 i_devnode_t *devnode;
635 void *prop = DI_PROP_NIL;
638 devnode = (i_devnode_t *)arg;
641 * Test the property functions, only for testing
644 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid);
645 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) {
646 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop));
648 if (!strcmp(di_prop_name(prop), "reg")) {
649 len = di_prop_ints(prop, ®buf);
651 for (i = 0; i < len; i++) {
652 fprintf(stderr, "0x%0x.", regbuf[i]);
654 fprintf(stderr, "\n");
656 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid);
659 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg",
664 fprintf(stderr, "error = %x\n", errno);
665 fprintf(stderr, "can not find assigned-address\n");
667 return (DI_WALK_CONTINUE);
669 busno = PCI_REG_BUS_G(regbuf[0]);
670 devno = PCI_REG_DEV_G(regbuf[0]);
671 funcno = PCI_REG_FUNC_G(regbuf[0]);
673 if ((busno == devnode->bus) &&
674 (devno == devnode->dev) &&
675 (funcno == devnode->func)) {
676 devnode->node = node;
678 return (DI_WALK_TERMINATE);
681 return (DI_WALK_CONTINUE);
688 pci_device_solx_devfs_probe( struct pci_device * dev )
700 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
701 args.node = DI_NODE_NIL;
703 struct pci_device_private *priv =
704 (struct pci_device_private *) dev;
707 (uint16_t)config[0] + ((uint16_t)config[1] << 8);
709 (uint16_t)config[2] + ((uint16_t)config[3] << 8);
710 dev->device_class = (uint32_t)config[9] +
711 ((uint32_t)config[10] << 8) +
712 ((uint16_t)config[11] << 16);
714 * device class code is already there.
715 * see probe_dev function.
717 dev->revision = config[8];
719 (uint16_t)config[44] + ((uint16_t)config[45] << 8);
721 (uint16_t)config[46] + ((uint16_t)config[47] << 8);
722 dev->irq = config[60];
724 priv->header_type = config[14];
726 * starting to find if it is MEM/MEM64/IO
729 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
730 (void) fprintf(stderr, "di_init failed: %s\n",
736 args.func = dev->func;
737 (void) di_walk_node(rnode, DI_WALK_CLDFIRST,
738 (void *)&args, find_target_node);
742 if (args.node != DI_NODE_NIL) {
744 * It will success for sure, because it was
745 * successfully called in find_target_node
747 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node,
748 "assigned-addresses",
758 * how to find the size of rom???
759 * if the device has expansion rom,
760 * it must be listed in the last
761 * cells because solaris find probe
762 * the base address from offset 0x10
763 * to 0x30h. So only check the last
766 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275];
767 if (PCI_REG_REG_G(reg->pci_phys_hi) ==
770 * rom can only be 32 bits
772 dev->rom_size = reg->pci_size_low;
773 len = len - CELL_NUMS_1275;
777 * size default to 64K and base address
780 dev->rom_size = 0x10000;
784 * solaris has its own BAR index. To be sure that
785 * Xorg has the same BAR number as solaris. ????
787 for (i = 0; i < len; i = i + CELL_NUMS_1275) {
788 int ent = i/CELL_NUMS_1275;
790 reg = (pci_regspec_t *)®buf[i];
793 * non relocatable resource is excluded
794 * such like 0xa0000, 0x3b0. If it is met,
795 * the loop is broken;
797 if (!PCI_REG_REG_G(reg->pci_phys_hi))
801 if (reg->pci_phys_hi & PCI_PREFETCH_B) {
802 dev->regions[ent].is_prefetchable = 1;
805 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
807 dev->regions[ent].is_IO = 1;
812 dev->regions[ent].is_64 = 1;
816 * We split the shift count 32 into two 16 to
817 * avoid the complaining of the compiler
819 dev->regions[ent].base_addr = reg->pci_phys_low +
820 ((reg->pci_phys_mid << 16) << 16);
821 dev->regions[ent].size = reg->pci_size_low +
822 ((reg->pci_size_hi << 16) << 16);
830 * Solaris version: read the ROM data
833 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer )
835 void *prom = MAP_FAILED;
838 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
839 (void) fprintf(stderr, "can not open xsvc driver\n");
845 prom = mmap(NULL, dev->rom_size,
846 PROT_READ, MAP_SHARED,
849 if (prom == MAP_FAILED) {
850 (void) fprintf(stderr, "map rom base =0xC0000 failed");
853 (void) bcopy(prom, buffer, dev->rom_size);
857 * Still used xsvc to do the user space mapping
864 * solaris version: Read the configurations space of the devices
867 pci_device_solx_devfs_read( struct pci_device * dev, void * data,
868 pciaddr_t offset, pciaddr_t size,
869 pciaddr_t * bytes_read )
871 pcitool_reg_t cfg_prg;
874 nexus_t *nexus = find_nexus_for_domain(dev->domain);
878 if ( nexus == NULL ) {
882 cfg_prg.offset = offset;
883 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
884 cfg_prg.bus_no = dev->bus;
885 cfg_prg.dev_no = dev->dev;
886 cfg_prg.func_no = dev->func;
888 cfg_prg.user_version = PCITOOL_USER_VERSION;
890 for (i = 0; i < size; i = i + PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1)) {
892 cfg_prg.offset = offset + i;
893 if ((err = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG,
895 fprintf(stderr, "read bdf<%x,%x,%x,%llx> config space failure\n",
900 fprintf(stderr, "Failure cause = %x\n", err);
904 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data;
906 * DWORDS Offset or bytes Offset ??
918 pci_device_solx_devfs_write( struct pci_device * dev, const void * data,
919 pciaddr_t offset, pciaddr_t size,
920 pciaddr_t * bytes_written )
922 pcitool_reg_t cfg_prg;
925 nexus_t *nexus = find_nexus_for_domain(dev->domain);
927 if ( bytes_written != NULL ) {
931 if ( nexus == NULL ) {
935 cfg_prg.offset = offset;
938 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
941 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN;
944 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
947 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN;
953 cfg_prg.bus_no = dev->bus;
954 cfg_prg.dev_no = dev->dev;
955 cfg_prg.func_no = dev->func;
957 cfg_prg.user_version = PCITOOL_USER_VERSION;
958 cfg_prg.data = *((uint64_t *)data);
960 * Check if this device is bridge device.
961 * If it is, it is also a nexus node???
962 * It seems that there is no explicit
963 * PCI nexus device for X86, so not applicable
964 * from pcitool_bus_reg_ops in pci_tools.c
966 cmd = PCITOOL_DEVICE_SET_REG;
968 if ((err = ioctl(nexus->fd, cmd, &cfg_prg)) != 0) {
971 *bytes_written = size;
978 * Map a memory region for a device using /dev/xsvc.
980 * \param dev Device whose memory region is to be mapped.
981 * \param map Parameters of the mapping that is to be created.
984 * Zero on success or an \c errno value on failure.
987 pci_device_solx_devfs_map_range(struct pci_device *dev,
988 struct pci_device_mapping *map)
990 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
991 ? (PROT_READ | PROT_WRITE) : PROT_READ;
996 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
997 (void) fprintf(stderr, "can not open xsvc driver\n");
1002 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd,
1004 if (map->memory == MAP_FAILED) {
1007 (void) fprintf(stderr, "map rom region =%llx failed",