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5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
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53 * Solaris devfs interfaces
60 #include <sys/types.h>
65 #include <libdevinfo.h>
66 #include "pci_tools.h"
68 #include "pciaccess.h"
69 #include "pciaccess_private.h"
73 #define MAX_DEVICES 256
74 #define CELL_NUMS_1275 (sizeof(pci_regspec_t) / sizeof(uint_t))
77 uint8_t bytes[16 * sizeof (uint32_t)];
81 typedef struct i_devnode {
88 typedef struct nexus {
92 char *path; /* for errors/debugging; fd is all we need */
96 static nexus_t *nexus_list = NULL;
97 static int xsvc_fd = -1;
100 * Read config space in native processor endianness. Endian-neutral
101 * processing can then take place. On big endian machines, MSB and LSB
102 * of little endian data end up switched if read as little endian.
103 * They are in correct order if read as big endian.
106 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_BIG
108 # define NATIVE_ENDIAN PCITOOL_ACC_ATTR_ENDN_LTL
110 # error "ISA is neither __sparc nor __x86"
114 * Identify problematic southbridges. These have device id 0x5249 and
115 * vendor id 0x10b9. Check for revision ID 0 and class code 060400 as well.
116 * Values are little endian, so they are reversed for SPARC.
118 * Check for these southbridges on all architectures, as the issue is a
119 * southbridge issue, independent of processor.
121 * If one of these is found during probing, skip probing other devs/funcs on
122 * the rest of the bus, since the southbridge and all devs underneath will
123 * otherwise disappear.
125 #if (NATIVE_ENDIAN == PCITOOL_ACC_ATTR_ENDN_BIG)
126 # define U45_SB_DEVID_VID 0xb9104952
127 # define U45_SB_CLASS_RID 0x00000406
129 # define U45_SB_DEVID_VID 0x524910b9
130 # define U45_SB_CLASS_RID 0x06040000
133 static int pci_device_solx_devfs_map_range(struct pci_device *dev,
134 struct pci_device_mapping *map);
136 static int pci_device_solx_devfs_read_rom( struct pci_device * dev,
139 static int pci_device_solx_devfs_probe( struct pci_device * dev );
141 static int pci_device_solx_devfs_read( struct pci_device * dev, void * data,
142 pciaddr_t offset, pciaddr_t size, pciaddr_t * bytes_read );
144 static int pci_device_solx_devfs_write( struct pci_device * dev,
145 const void * data, pciaddr_t offset, pciaddr_t size,
146 pciaddr_t * bytes_written );
148 static int probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p,
149 struct pci_system *pci_sys);
151 static int do_probe(nexus_t *nexus, struct pci_system *pci_sys);
153 static int probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg);
155 static void pci_system_solx_devfs_destroy( void );
157 static int get_config_header(int fd, uint8_t bus_no, uint8_t dev_no,
158 uint8_t func_no, pci_conf_hdr_t *config_hdr_p);
160 int pci_system_solx_devfs_create( void );
162 static const struct pci_system_methods solx_devfs_methods = {
163 .destroy = pci_system_solx_devfs_destroy,
164 .destroy_device = NULL,
165 .read_rom = pci_device_solx_devfs_read_rom,
166 .probe = pci_device_solx_devfs_probe,
167 .map_range = pci_device_solx_devfs_map_range,
168 .unmap_range = pci_device_generic_unmap_range,
170 .read = pci_device_solx_devfs_read,
171 .write = pci_device_solx_devfs_write,
173 .fill_capabilities = pci_fill_capabilities_generic
177 find_nexus_for_bus( int bus )
181 for (nexus = nexus_list ; nexus != NULL ; nexus = nexus->next) {
182 if ((bus >= nexus->first_bus) && (bus <= nexus->last_bus)) {
189 #define GET_CONFIG_VAL_8(offset) (config_hdr.bytes[offset])
190 #define GET_CONFIG_VAL_16(offset) \
191 (uint16_t) (GET_CONFIG_VAL_8(offset) + (GET_CONFIG_VAL_8(offset+1) << 8))
192 #define GET_CONFIG_VAL_32(offset) \
193 (uint32_t) (GET_CONFIG_VAL_8(offset) + \
194 (GET_CONFIG_VAL_8(offset+1) << 8) + \
195 (GET_CONFIG_VAL_8(offset+2) << 16) + \
196 (GET_CONFIG_VAL_8(offset+3) << 24))
199 * Release all the resources
203 pci_system_solx_devfs_destroy( void )
206 * The memory allocated for pci_sys & devices in create routines
207 * will be freed in pci_system_cleanup.
208 * Need to free system-specific allocations here.
210 nexus_t *nexus, *next;
212 for (nexus = nexus_list ; nexus != NULL ; nexus = next) {
227 * Attempt to access PCI subsystem using Solaris's devfs interface.
231 pci_system_solx_devfs_create( void )
237 if (nexus_list != NULL) {
242 * Only allow MAX_DEVICES exists
243 * I will fix it later to get
244 * the total devices first
246 if ((pci_sys = calloc(1, sizeof (struct pci_system))) != NULL) {
247 pci_sys->methods = &solx_devfs_methods;
249 if ((pci_sys->devices =
250 calloc(MAX_DEVICES, sizeof (struct pci_device_private)))
253 if ((di_node = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
255 (void) fprintf(stderr, "di_init() failed: %s\n",
258 (void) di_walk_minor(di_node, DDI_NT_REGACC, 0, pci_sys,
271 if (pci_sys != NULL) {
272 free(pci_sys->devices);
282 * Retrieve first 16 dwords of device's config header, except for the first
283 * dword. First 16 dwords are defined by the PCI specification.
286 get_config_header(int fd, uint8_t bus_no, uint8_t dev_no, uint8_t func_no,
287 pci_conf_hdr_t *config_hdr_p)
289 pcitool_reg_t cfg_prg;
293 /* Prepare a local pcitool_reg_t so as to not disturb the caller's. */
295 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
296 cfg_prg.bus_no = bus_no;
297 cfg_prg.dev_no = dev_no;
298 cfg_prg.func_no = func_no;
300 cfg_prg.user_version = PCITOOL_USER_VERSION;
302 /* Get dwords 1-15 of config space. They must be read as uint32_t. */
303 for (i = 1; i < (sizeof (pci_conf_hdr_t) / sizeof (uint32_t)); i++) {
304 cfg_prg.offset += sizeof (uint32_t);
305 if ((rval = ioctl(fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
308 config_hdr_p->dwords[i] = (uint32_t)cfg_prg.data;
316 * Probe device's functions. Modifies many fields in the prg_p.
319 probe_dev(nexus_t *nexus, pcitool_reg_t *prg_p, struct pci_system *pci_sys)
321 pci_conf_hdr_t config_hdr;
322 boolean_t multi_function_device;
324 int8_t first_func = 0;
325 int8_t last_func = PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT;
327 struct pci_device * pci_base;
330 * Loop through at least func=first_func. Continue looping through
331 * functions if there are no errors and the device is a multi-function
334 * (Note, if first_func == 0, header will show whether multifunction
335 * device and set multi_function_device. If first_func != 0, then we
336 * will force the loop as the user wants a specific function to be
339 for (func = first_func, multi_function_device = B_FALSE;
340 ((func <= last_func) &&
341 ((func == first_func) || (multi_function_device)));
343 prg_p->func_no = func;
346 * Four things can happen here:
348 * 1) ioctl comes back as EFAULT and prg_p->status is
349 * PCITOOL_INVALID_ADDRESS. There is no device at this location.
351 * 2) ioctl comes back successful and the data comes back as
352 * zero. Config space is mapped but no device responded.
354 * 3) ioctl comes back successful and the data comes back as
355 * non-zero. We've found a device.
357 * 4) Some other error occurs in an ioctl.
360 prg_p->status = PCITOOL_SUCCESS;
363 prg_p->user_version = PCITOOL_USER_VERSION;
366 if (((rval = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, prg_p)) != 0) ||
367 (prg_p->data == 0xffffffff)) {
370 * Accept errno == EINVAL along with status of
371 * PCITOOL_OUT_OF_RANGE because some systems
372 * don't implement the full range of config space.
373 * Leave the loop quietly in this case.
375 if ((errno == EINVAL) ||
376 (prg_p->status == PCITOOL_OUT_OF_RANGE)) {
381 * Exit silently with ENXIO as this means that there are
382 * no devices under the pci root nexus.
384 else if ((errno == ENXIO) &&
385 (prg_p->status == PCITOOL_IO_ERROR)) {
390 * Expect errno == EFAULT along with status of
391 * PCITOOL_INVALID_ADDRESS because there won't be
392 * devices at each stop. Quit on any other error.
394 else if (((errno != EFAULT) ||
395 (prg_p->status != PCITOOL_INVALID_ADDRESS)) &&
396 (prg_p->data != 0xffffffff)) {
401 * If no function at this location,
402 * just advance to the next function.
409 * Data came back as 0.
410 * Treat as unresponsive device and check next device.
412 } else if (prg_p->data == 0) {
414 break; /* Func loop. */
416 /* Found something. */
418 config_hdr.dwords[0] = (uint32_t)prg_p->data;
420 /* Get the rest of the PCI header. */
421 if ((rval = get_config_header(nexus->fd, prg_p->bus_no,
422 prg_p->dev_no, prg_p->func_no,
423 &config_hdr)) != 0) {
428 * Special case for the type of Southbridge found on
429 * Ultra-45 and other sun4u fire workstations.
431 if ((config_hdr.dwords[0] == U45_SB_DEVID_VID) &&
432 (config_hdr.dwords[2] == U45_SB_CLASS_RID)) {
438 * Found one device with bus number, device number and
442 pci_base = &pci_sys->devices[pci_sys->num_devices].base;
445 * Domain is peer bus??
447 pci_base->domain = 0;
448 pci_base->bus = prg_p->bus_no;
449 pci_base->dev = prg_p->dev_no;
450 pci_base->func = func;
453 * for the format of device_class, see struct pci_device;
456 pci_base->device_class =
457 (GET_CONFIG_VAL_8(PCI_CONF_BASCLASS) << 16) |
458 (GET_CONFIG_VAL_8(PCI_CONF_SUBCLASS) << 8) |
459 GET_CONFIG_VAL_8(PCI_CONF_PROGCLASS);
461 pci_base->revision = GET_CONFIG_VAL_8(PCI_CONF_REVID);
462 pci_base->vendor_id = GET_CONFIG_VAL_16(PCI_CONF_VENID);
463 pci_base->device_id = GET_CONFIG_VAL_16(PCI_CONF_DEVID);
464 pci_base->subvendor_id = GET_CONFIG_VAL_16(PCI_CONF_SUBVENID);
465 pci_base->subdevice_id = GET_CONFIG_VAL_16(PCI_CONF_SUBSYSID);
467 pci_sys->devices[pci_sys->num_devices].header_type
468 = GET_CONFIG_VAL_8(PCI_CONF_HEADER);
472 "nexus = %s, busno = %x, devno = %x, funcno = %x\n",
473 nexus->path, prg_p->bus_no, prg_p->dev_no, func);
476 if (pci_sys->num_devices < (MAX_DEVICES - 1)) {
477 pci_sys->num_devices++;
479 (void) fprintf(stderr,
480 "Maximum number of PCI devices found,"
481 " discarding additional devices\n");
486 * Accommodate devices which state their
487 * multi-functionality only in their function 0 config
488 * space. Note multi-functionality throughout probing
489 * of all of this device's functions.
491 if (config_hdr.bytes[PCI_CONF_HEADER] & PCI_HEADER_MULTI) {
492 multi_function_device = B_TRUE;
501 * This function is called from di_walk_minor() when any PROBE is processed
504 probe_nexus_node(di_node_t di_node, di_minor_t minor, void *arg)
506 struct pci_system *pci_sys = (struct pci_system *) arg;
510 char nexus_path[MAXPATHLEN];
517 int first_bus = 0, last_bus = PCI_REG_BUS_G(PCI_REG_BUS_M);
520 nexus_name = di_devfs_minor_path(minor);
521 fprintf(stderr, "-- device name: %s\n", nexus_name);
524 for (prop = di_prop_next(di_node, NULL); prop != NULL;
525 prop = di_prop_next(di_node, prop)) {
527 const char *prop_name = di_prop_name(prop);
530 fprintf(stderr, " property: %s\n", prop_name);
533 if (strcmp(prop_name, "device_type") == 0) {
534 numval = di_prop_strings(prop, &strings);
535 if (numval != 1 || strncmp(strings, "pci", 3) != 0) {
536 /* not a PCI node, bail */
537 return (DI_WALK_CONTINUE);
541 else if (strcmp(prop_name, "class-code") == 0) {
542 /* not a root bus node, bail */
543 return (DI_WALK_CONTINUE);
545 else if (strcmp(prop_name, "bus-range") == 0) {
546 numval = di_prop_ints(prop, &ints);
554 #ifdef __x86 /* sparc pci nodes don't have the device_type set */
556 return (DI_WALK_CONTINUE);
559 /* we have a PCI root bus node. */
560 nexus = calloc(1, sizeof(nexus_t));
562 (void) fprintf(stderr, "Error allocating memory for nexus: %s\n",
564 return (DI_WALK_TERMINATE);
566 nexus->first_bus = first_bus;
567 nexus->last_bus = last_bus;
569 nexus_name = di_devfs_minor_path(minor);
570 if (nexus_name == NULL) {
571 (void) fprintf(stderr, "Error getting nexus path: %s\n",
574 return (DI_WALK_CONTINUE);
577 snprintf(nexus_path, sizeof(nexus_path), "/devices%s", nexus_name);
578 di_devfs_path_free(nexus_name);
581 fprintf(stderr, "nexus = %s, bus-range = %d - %d\n",
582 nexus_path, first_bus, last_bus);
585 if ((fd = open(nexus_path, O_RDWR)) >= 0) {
587 nexus->path = strdup(nexus_path);
588 if ((do_probe(nexus, pci_sys) != 0) && (errno != ENXIO)) {
589 (void) fprintf(stderr, "Error probing node %s: %s\n",
590 nexus_path, strerror(errno));
595 nexus->next = nexus_list;
599 (void) fprintf(stderr, "Error opening %s: %s\n",
600 nexus_path, strerror(errno));
604 return DI_WALK_CONTINUE;
610 * Probe a given nexus config space for devices.
612 * fd is the file descriptor of the nexus.
613 * input_args contains commandline options as specified by the user.
616 do_probe(nexus_t *nexus, struct pci_system *pci_sys)
621 uint32_t last_bus = nexus->last_bus;
622 uint8_t last_dev = PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT;
623 uint8_t first_bus = nexus->first_bus;
624 uint8_t first_dev = 0;
627 prg.barnum = 0; /* Config space. */
629 /* Must read in 4-byte quantities. */
630 prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
635 * Loop through all valid bus / dev / func combinations to check for
636 * all devices, with the following exceptions:
638 * When nothing is found at function 0 of a bus / dev combination, skip
639 * the other functions of that bus / dev combination.
641 * When a found device's function 0 is probed and it is determined that
642 * it is not a multifunction device, skip probing of that device's
645 for (bus = first_bus; ((bus <= last_bus) && (rval == 0)); bus++) {
646 prg.bus_no = (uint8_t)bus;
648 for (dev = first_dev; ((dev <= last_dev) && (rval == 0)); dev++) {
650 rval = probe_dev(nexus, &prg, pci_sys);
654 * Ultra-45 southbridge workaround:
655 * ECANCELED tells to skip to the next bus.
657 if (rval == ECANCELED) {
666 find_target_node(di_node_t node, void *arg)
670 uint32_t busno, funcno, devno;
671 i_devnode_t *devnode = (i_devnode_t *)arg;
674 * Test the property functions, only for testing
677 void *prop = DI_PROP_NIL;
679 (void) fprintf(stderr, "start of node 0x%x\n", node->nodeid);
680 while ((prop = di_prop_hw_next(node, prop)) != DI_PROP_NIL) {
682 (void) fprintf(stderr, "name=%s: ", di_prop_name(prop));
684 if (!strcmp(di_prop_name(prop), "reg")) {
685 len = di_prop_ints(prop, ®buf);
687 for (i = 0; i < len; i++) {
688 fprintf(stderr, "0x%0x.", regbuf[i]);
690 fprintf(stderr, "\n");
692 (void) fprintf(stderr, "end of node 0x%x\n", node->nodeid);
695 len = di_prop_lookup_ints(DDI_DEV_T_ANY, node, "reg", ®buf);
699 fprintf(stderr, "error = %x\n", errno);
700 fprintf(stderr, "can not find assigned-address\n");
702 return (DI_WALK_CONTINUE);
705 busno = PCI_REG_BUS_G(regbuf[0]);
706 devno = PCI_REG_DEV_G(regbuf[0]);
707 funcno = PCI_REG_FUNC_G(regbuf[0]);
709 if ((busno == devnode->bus) &&
710 (devno == devnode->dev) &&
711 (funcno == devnode->func)) {
712 devnode->node = node;
714 return (DI_WALK_TERMINATE);
717 return (DI_WALK_CONTINUE);
724 pci_device_solx_devfs_probe( struct pci_device * dev )
728 di_node_t rnode = DI_NODE_NIL;
729 i_devnode_t args = { 0, 0, 0, DI_NODE_NIL };
737 err = pci_device_solx_devfs_read( dev, config, 0, 256, & bytes );
740 struct pci_device_private *priv =
741 (struct pci_device_private *) dev;
743 dev->vendor_id = (uint16_t)config[0] + ((uint16_t)config[1] << 8);
744 dev->device_id = (uint16_t)config[2] + ((uint16_t)config[3] << 8);
745 dev->device_class = (uint32_t)config[9] +
746 ((uint32_t)config[10] << 8) +
747 ((uint16_t)config[11] << 16);
750 * device class code is already there.
751 * see probe_dev function.
753 dev->revision = config[8];
754 dev->subvendor_id = (uint16_t)config[44] + ((uint16_t)config[45] << 8);
755 dev->subdevice_id = (uint16_t)config[46] + ((uint16_t)config[47] << 8);
756 dev->irq = config[60];
758 priv->header_type = config[14];
760 * starting to find if it is MEM/MEM64/IO
763 if ((rnode = di_init("/", DINFOCPYALL)) == DI_NODE_NIL) {
765 (void) fprintf(stderr, "di_init failed: %s\n", strerror(errno));
769 args.func = dev->func;
770 (void) di_walk_node(rnode, DI_WALK_CLDFIRST,
771 (void *)&args, find_target_node);
774 if (args.node != DI_NODE_NIL) {
776 * It will succeed for sure, because it was
777 * successfully called in find_target_node
779 len = di_prop_lookup_ints(DDI_DEV_T_ANY, args.node,
780 "assigned-addresses",
790 * how to find the size of rom???
791 * if the device has expansion rom,
792 * it must be listed in the last
793 * cells because solaris find probe
794 * the base address from offset 0x10
795 * to 0x30h. So only check the last
798 reg = (pci_regspec_t *)®buf[len - CELL_NUMS_1275];
799 if (PCI_REG_REG_G(reg->pci_phys_hi) == PCI_CONF_ROM) {
801 * rom can only be 32 bits
803 dev->rom_size = reg->pci_size_low;
804 len = len - CELL_NUMS_1275;
808 * size default to 64K and base address
811 dev->rom_size = 0x10000;
815 * Solaris has its own BAR index.
816 * Linux give two region slot for 64 bit address.
818 for (i = 0; i < len; i = i + CELL_NUMS_1275) {
820 reg = (pci_regspec_t *)®buf[i];
821 ent = reg->pci_phys_hi & 0xff;
825 ent = (ent - PCI_CONF_BASE0) >> 2;
827 fprintf(stderr, "error ent = %d\n", ent);
832 * non relocatable resource is excluded
833 * such like 0xa0000, 0x3b0. If it is met,
834 * the loop is broken;
836 if (!PCI_REG_REG_G(reg->pci_phys_hi))
839 if (reg->pci_phys_hi & PCI_PREFETCH_B) {
840 dev->regions[ent].is_prefetchable = 1;
845 * We split the shift count 32 into two 16 to
846 * avoid the complaining of the compiler
848 dev->regions[ent].base_addr = reg->pci_phys_low +
849 ((reg->pci_phys_mid << 16) << 16);
850 dev->regions[ent].size = reg->pci_size_low +
851 ((reg->pci_size_hi << 16) << 16);
853 switch (reg->pci_phys_hi & PCI_REG_ADDR_M) {
855 dev->regions[ent].is_IO = 1;
860 dev->regions[ent].is_64 = 1;
862 * Skip one slot for 64 bit address
869 if (rnode != DI_NODE_NIL) {
876 * Solaris version: read the VGA ROM data
879 pci_device_solx_devfs_read_rom( struct pci_device * dev, void * buffer )
882 struct pci_device_mapping prom = {
884 .size = dev->rom_size,
888 err = pci_device_solx_devfs_map_range(dev, &prom);
890 (void) bcopy(prom.memory, buffer, dev->rom_size);
892 if (munmap(prom.memory, dev->rom_size) == -1) {
900 * solaris version: Read the configurations space of the devices
903 pci_device_solx_devfs_read( struct pci_device * dev, void * data,
904 pciaddr_t offset, pciaddr_t size,
905 pciaddr_t * bytes_read )
907 pcitool_reg_t cfg_prg;
910 nexus_t *nexus = find_nexus_for_bus(dev->bus);
914 if ( nexus == NULL ) {
918 cfg_prg.offset = offset;
919 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
920 cfg_prg.bus_no = dev->bus;
921 cfg_prg.dev_no = dev->dev;
922 cfg_prg.func_no = dev->func;
924 cfg_prg.user_version = PCITOOL_USER_VERSION;
926 for (i = 0; i < size; i += PCITOOL_ACC_ATTR_SIZE(PCITOOL_ACC_ATTR_SIZE_1))
928 cfg_prg.offset = offset + i;
930 if ((err = ioctl(nexus->fd, PCITOOL_DEVICE_GET_REG, &cfg_prg)) != 0) {
931 fprintf(stderr, "read bdf<%s,%x,%x,%x,%llx> config space failure\n",
937 fprintf(stderr, "Failure cause = %x\n", err);
941 ((uint8_t *)data)[i] = (uint8_t)cfg_prg.data;
943 * DWORDS Offset or bytes Offset ??
955 pci_device_solx_devfs_write( struct pci_device * dev, const void * data,
956 pciaddr_t offset, pciaddr_t size,
957 pciaddr_t * bytes_written )
959 pcitool_reg_t cfg_prg;
962 nexus_t *nexus = find_nexus_for_bus(dev->bus);
964 if ( bytes_written != NULL ) {
968 if ( nexus == NULL ) {
972 cfg_prg.offset = offset;
975 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_1 + NATIVE_ENDIAN;
978 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_2 + NATIVE_ENDIAN;
981 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_4 + NATIVE_ENDIAN;
984 cfg_prg.acc_attr = PCITOOL_ACC_ATTR_SIZE_8 + NATIVE_ENDIAN;
989 cfg_prg.bus_no = dev->bus;
990 cfg_prg.dev_no = dev->dev;
991 cfg_prg.func_no = dev->func;
993 cfg_prg.user_version = PCITOOL_USER_VERSION;
994 cfg_prg.data = *((uint64_t *)data);
997 * Check if this device is bridge device.
998 * If it is, it is also a nexus node???
999 * It seems that there is no explicit
1000 * PCI nexus device for X86, so not applicable
1001 * from pcitool_bus_reg_ops in pci_tools.c
1003 cmd = PCITOOL_DEVICE_SET_REG;
1005 if ((err = ioctl(nexus->fd, cmd, &cfg_prg)) != 0) {
1008 *bytes_written = size;
1015 * Map a memory region for a device using /dev/xsvc.
1017 * \param dev Device whose memory region is to be mapped.
1018 * \param map Parameters of the mapping that is to be created.
1021 * Zero on success or an \c errno value on failure.
1024 pci_device_solx_devfs_map_range(struct pci_device *dev,
1025 struct pci_device_mapping *map)
1027 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
1028 ? (PROT_READ | PROT_WRITE) : PROT_READ;
1032 * Still used xsvc to do the user space mapping
1035 if ((xsvc_fd = open("/dev/xsvc", O_RDWR)) < 0) {
1037 (void) fprintf(stderr, "can not open /dev/xsvc: %s\n",
1043 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, xsvc_fd, map->base);
1044 if (map->memory == MAP_FAILED) {
1047 (void) fprintf(stderr, "map rom region =%llx failed: %s\n",
1048 map->base, strerror(errno));