src/shaders/vme/vme.inc

   1 /*
   2  * Copyright © <2010>, Intel Corporation.
   3  *
   4  * This program is licensed under the terms and conditions of the
   5  * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
   6  * http://www.opensource.org/licenses/eclipse-1.0.php.
   7  *
   8  */
   9 // Modual name: ME_header.inc
  10 //
  11 // Global symbols define
  12 //
  13
  14 /*
  15  * Constant
  16  */
  17 define(`VME_MESSAGE_TYPE_INTER',        `1')
  18 define(`VME_MESSAGE_TYPE_INTRA',        `2')
  19 define(`VME_MESSAGE_TYPE_MIXED',        `3')
  20
  21 define(`BLOCK_32X1',                    `0x0000001F')
  22 define(`BLOCK_4X16',                    `0x000F0003')
  23
  24 define(`LUMA_INTRA_16x16_DISABLE',      `0x1')
  25 define(`LUMA_INTRA_8x8_DISABLE',        `0x2')
  26 define(`LUMA_INTRA_4x4_DISABLE',        `0x4')
  27
  28 define(`INTRA_PRED_AVAIL_FLAG_AE',      `0x60')
  29 define(`INTRA_PRED_AVAIL_FLAG_B',       `0x10')
  30 define(`INTRA_PRED_AVAIL_FLAG_C',       `0x8')
  31 define(`INTRA_PRED_AVAIL_FLAG_D',       `0x4')
  32
  33 define(`BIND_IDX_VME',                  `0')
  34 define(`BIND_IDX_VME_REF0',             `1')
  35 define(`BIND_IDX_VME_REF1',             `2')
  36 define(`BIND_IDX_OUTPUT',               `3')
  37 define(`BIND_IDX_INEP',                 `4')
  38
  39 define(`SUB_PEL_MODE_INTEGER',          `0x00000000')
  40 define(`SUB_PEL_MODE_HALF',             `0x00001000')
  41 define(`SUB_PEL_MODE_QUARTER',          `0x00003000')
  42
  43 define(`INTER_SAD_NONE',                `0x00000000')
  44 define(`INTER_SAD_HAAR',                `0x00200000')
  45
  46 define(`INTRA_SAD_NONE',                `0x00000000')
  47 define(`INTRA_SAD_HAAR',                `0x00800000')
  48
  49 define(`INTER_PART_MASK',               `0x7E000000')
  50
  51 define(`REF_REGION_SIZE',               `0x2830:UW')
  52
  53 define(`BI_SUB_MB_PART_MASK',           `0x0c000000')
  54 define(`MAX_NUM_MV',                    `0x00000020')
  55 define(`SEARCH_PATH_LEN',               `0x00003F3F')
  56
  57 define(`INTRA_PREDICTORE_MODE',         `0x11111111:UD')
  58
  59 #ifdef DEV_SNB
  60
  61 define(`OBW_CACHE_TYPE',                `5')
  62
  63 #else
  64
  65 define(`OBW_CACHE_TYPE',                `10')
  66
  67 #endif
  68
  69 define(`OBW_MESSAGE_TYPE',              `8')
  70
  71 define(`OBW_BIND_IDX',                  `BIND_IDX_OUTPUT')
  72
  73 define(`OBW_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
  74 define(`OBW_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
  75 define(`OBW_CONTROL_2',                 `2')    /* 2 OWords */
  76 define(`OBW_CONTROL_3',                 `3')    /* 4 OWords */
  77
  78 #ifdef DEV_SNB
  79
  80 define(`OBW_WRITE_COMMIT_CATEGORY',     `1')    /* write commit on Sandybrige */
  81
  82 #else
  83
  84 define(`OBW_WRITE_COMMIT_CATEGORY',     `0')    /* category on Ivybridge */
  85
  86 #endif
  87
  88
  89 define(`OBW_HEADER_PRESENT',            `1')
  90
  91 /* GRF registers
  92  * r0 header
  93  * r1~r4 constant buffer (reserved)
  94  * r5 inline data
  95  * r6~r11 reserved
  96  * r12 write back of VME message
  97  * r13 write back of Oword Block Write
  98  */
  99 /*
 100  * GRF 0 -- header
 101  */
 102 define(`thread_id_ub',          `r0.20<0,1,0>:UB')  /* thread id in payload */
 103
 104 /*
 105  * GRF 1~4 -- Constant Buffer (reserved)
 106  */
 107
 108 /*
 109  * GRF 5 -- inline data
 110  */
 111 define(`inline_reg0',           `r5')
 112 define(`w_in_mb_uw',            `inline_reg0.2')
 113 define(`orig_xy_ub',            `inline_reg0.0')
 114 define(`orig_x_ub',             `inline_reg0.0')    /* in macroblock */
 115 define(`orig_y_ub',             `inline_reg0.1')
 116 define(`transform_8x8_ub',      `inline_reg0.4')
 117 define(`num_macroblocks',       `inline_reg0.6')
 118
 119 /*
 120  * GRF 6~11 -- reserved
 121  */
 122
 123 /*
 124  * GRF 12~15 -- write back for VME message
 125  */
 126 define(`vme_wb',                `r12')
 127 define(`vme_wb0',               `r12')
 128 define(`vme_wb1',               `r13')
 129 define(`vme_wb2',               `r14')
 130 define(`vme_wb3',               `r15')
 131
 132 #ifdef DEV_SNB
 133 /*
 134  * GRF 16 -- write back for Oword Block Write message with write commit bit
 135  */
 136 define(`obw_wb',                `r16')
 137 define(`obw_wb_length',         `1')
 138
 139 #else
 140
 141 /*
 142  * GRF 16 -- reserved
 143  */
 144 define(`obw_wb',                `null<1>:W')
 145 define(`obw_wb_length',         `0')
 146
 147 #endif
 148
 149 /*
 150  * GRF 18~21 -- Intra Neighbor Edge Pixels
 151  */
 152 define(`INEP_ROW',              `r18')
 153 define(`INEP_COL0',             `r20')
 154 define(`INEP_COL1',             `r21')
 155
 156 /*
 157  * temporary registers
 158  */
 159 define(`tmp_reg0',              `r32')
 160 define(`read0_header',          `tmp_reg0')
 161 define(`tmp_reg1',              `r33')
 162 define(`read1_header',          `tmp_reg1')
 163 define(`tmp_reg2',              `r34')
 164 define(`vme_m0',                `tmp_reg2')
 165 define(`tmp_reg3',              `r35')
 166 define(`vme_m1',                `tmp_reg3')
 167 define(`intra_flag',            `vme_m1.28')
 168 define(`intra_part_mask_ub',    `vme_m1.28')
 169 define(`mb_intra_struct_ub',    `vme_m1.29')
 170 define(`tmp_reg4',              `r36')
 171 define(`obw_m0',                `tmp_reg4')
 172 define(`tmp_reg5',              `r37')
 173 define(`obw_m1',                `tmp_reg5')
 174 define(`tmp_reg6',              `r38')
 175 define(`tmp_x_w',               `tmp_reg6.0')
 176
 177 /*
 178  * MRF registers
 179  */
 180 #ifdef DEV_SNB
 181
 182 define(`msg_ind',               `0')
 183 define(`msg_reg0',              `m0')               /* m0 */
 184 define(`msg_reg1',              `m1')               /* m1 */
 185 define(`msg_reg2',              `m2')               /* m2 */
 186 define(`msg_reg3',              `m3')               /* m3 */
 187 define(`msg_reg4',              `m4')               /* m4 */
 188
 189 #else
 190
 191 define(`msg_ind',               `64')
 192 define(`msg_reg0',              `g64')
 193 define(`msg_reg1',              `g65')
 194 define(`msg_reg2',              `g66')
 195 define(`msg_reg3',              `g67')
 196 define(`msg_reg4',              `g68')
 197
 198 #endif
 199
 200 /*
 201  * VME message payload
 202  */
 203
 204 #ifdef DEV_SNB
 205
 206 define(`vme_msg_length',        `4')
 207 define(`vme_inter_wb_length',   `4')
 208
 209 #else
 210
 211 define(`vme_msg_length',        `5')
 212 define(`vme_inter_wb_length',   `6')
 213
 214 #endif
 215
 216 define(`vme_intra_wb_length',   `1')
 217
 218 define(`vme_msg_ind',           `msg_ind')
 219 define(`vme_msg_0',             `msg_reg0')
 220 define(`vme_msg_1',             `msg_reg1')
 221 define(`vme_msg_2',             `msg_reg2')
 222
 223 #ifdef DEV_SNB
 224
 225 define(`vme_msg_3',             `vme_msg_2')
 226 define(`vme_msg_4',             `msg_reg3')
 227
 228 #else
 229
 230 define(`vme_msg_3',             `msg_reg3')
 231 define(`vme_msg_4',             `msg_reg4')
 232
 233 #endif
 234