src/shaders/vme/gen6_vme_header.inc

   1 /*
   2  * Copyright © <2010>, Intel Corporation.
   3  *
   4  * This program is licensed under the terms and conditions of the
   5  * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
   6  * http://www.opensource.org/licenses/eclipse-1.0.php.
   7  *
   8  */
   9 // Modual name: ME_header.inc
  10 //
  11 // Global symbols define
  12 //
  13
  14 /*
  15  * Constant
  16  */
  17 define(`VME_MESSAGE_TYPE_INTER',        `1')
  18 define(`VME_MESSAGE_TYPE_INTRA',        `2')
  19 define(`VME_MESSAGE_TYPE_MIXED',        `3')
  20
  21 define(`BLOCK_32X1',                    `0x0000001F')
  22 define(`BLOCK_4X16',                    `0x000F0003')
  23
  24 define(`LUMA_INTRA_16x16_DISABLE',      `0x1')
  25 define(`LUMA_INTRA_8x8_DISABLE',        `0x2')
  26 define(`LUMA_INTRA_4x4_DISABLE',        `0x4')
  27
  28 define(`INTRA_PRED_AVAIL_FLAG_AE',      `0x60')
  29 define(`INTRA_PRED_AVAIL_FLAG_B',       `0x10')
  30 define(`INTRA_PRED_AVAIL_FLAG_C',       `0x8')
  31 define(`INTRA_PRED_AVAIL_FLAG_D',       `0x4')
  32
  33 define(`BIND_IDX_VME',                  `0')
  34 define(`BIND_IDX_VME_REF0',             `1')
  35 define(`BIND_IDX_VME_REF1',             `2')
  36 define(`BIND_IDX_OUTPUT',               `3')
  37 define(`BIND_IDX_INEP',                 `4')
  38
  39 define(`SUB_PEL_MODE_INTEGER',          `0x00000000')
  40 define(`SUB_PEL_MODE_HALF',             `0x00001000')
  41 define(`SUB_PEL_MODE_QUARTER',          `0x00003000')
  42
  43 define(`INTER_SAD_NONE',                `0x00000000')
  44 define(`INTER_SAD_HAAR',                `0x00200000')
  45
  46 define(`INTRA_SAD_NONE',                `0x00000000')
  47 define(`INTRA_SAD_HAAR',                `0x00800000')
  48
  49 define(`INTER_PART_MASK',               `0x7E000000')
  50
  51 define(`REF_REGION_SIZE',               `0x2830:UW')
  52
  53 define(`BI_SUB_MB_PART_MASK',           `0x0c000000')
  54 define(`MAX_NUM_MV',                    `0x00000020')
  55 define(`SEARCH_PATH_LEN',               `0x00003F3F')
  56
  57 define(`INTRA_PREDICTORE_MODE',         `0x11111111:UD')
  58
  59 define(`OBW_CACHE_TYPE',                `5')
  60
  61 define(`OBW_MESSAGE_TYPE',              `8')
  62
  63 define(`OBW_BIND_IDX',                  `BIND_IDX_OUTPUT')
  64
  65 define(`OBW_CONTROL_0',                 `0')    /* 1 OWord, low 128 bits */
  66 define(`OBW_CONTROL_1',                 `1')    /* 1 OWord, high 128 bits */
  67 define(`OBW_CONTROL_2',                 `2')    /* 2 OWords */
  68 define(`OBW_CONTROL_3',                 `3')    /* 4 OWords */
  69
  70 define(`OBW_WRITE_COMMIT_CATEGORY',     `1')    /* write commit on Sandybrige */
  71
  72 define(`OBW_HEADER_PRESENT',            `1')
  73
  74 /* GRF registers
  75  * r0 header
  76  * r1~r4 constant buffer (reserved)
  77  * r5 inline data
  78  * r6~r11 reserved
  79  * r12 write back of VME message
  80  * r13 write back of Oword Block Write
  81  */
  82 /*
  83  * GRF 0 -- header
  84  */
  85 define(`thread_id_ub',          `r0.20<0,1,0>:UB')  /* thread id in payload */
  86
  87 /*
  88  * GRF 1~4 -- Constant Buffer (reserved)
  89  */
  90
  91 /*
  92  * GRF 5 -- inline data
  93  */
  94 define(`inline_reg0',           `r5')
  95 define(`w_in_mb_uw',            `inline_reg0.2')
  96 define(`orig_xy_ub',            `inline_reg0.0')
  97 define(`orig_x_ub',             `inline_reg0.0')    /* in macroblock */
  98 define(`orig_y_ub',             `inline_reg0.1')
  99 define(`transform_8x8_ub',      `inline_reg0.4')
 100
 101 /*
 102  * GRF 6~11 -- reserved
 103  */
 104
 105 /*
 106  * GRF 12~15 -- write back for VME message
 107  */
 108 define(`vme_wb',                `r12')
 109 define(`vme_wb0',               `r12')
 110 define(`vme_wb1',               `r13')
 111 define(`vme_wb2',               `r14')
 112 define(`vme_wb3',               `r15')
 113
 114 /*
 115  * GRF 16 -- write back for Oword Block Write message with write commit bit
 116  */
 117 define(`obw_wb',                `r16')
 118 define(`obw_wb_length',         `1')
 119
 120 /*
 121  * GRF 18~21 -- Intra Neighbor Edge Pixels
 122  */
 123 define(`INEP_ROW',              `r18')
 124 define(`INEP_COL0',             `r20')
 125 define(`INEP_COL1',             `r21')
 126
 127 /*
 128  * temporary registers
 129  */
 130 define(`tmp_reg0',              `r32')
 131 define(`tmp_reg1',              `r33')
 132 define(`intra_part_mask_ub',    `tmp_reg1.28')
 133 define(`mb_intra_struct_ub',    `tmp_reg1.29')
 134 define(`tmp_reg2',              `r34')
 135 define(`tmp_x_w',               `tmp_reg2.0')
 136 define(`tmp_reg3',              `r35')
 137
 138 /*
 139  * MRF registers
 140  */
 141 define(`msg_ind',               `0')
 142 define(`msg_reg0',              `m0')               /* m0 */
 143 define(`msg_reg1',              `m1')               /* m1 */
 144 define(`msg_reg2',              `m2')               /* m2 */
 145 define(`msg_reg3',              `m3')               /* m3 */
 146 define(`msg_reg4',              `m4')               /* m4 */
 147
 148 /*
 149  * VME message payload
 150  */
 151 define(`vme_msg_length',        `4')
 152 define(`vme_intra_wb_length',   `1')
 153 define(`vme_inter_wb_length',   `4')
 154 define(`vme_msg_ind',           `msg_ind')
 155 define(`vme_msg_0',             `msg_reg0')
 156 define(`vme_msg_1',             `msg_reg1')
 157 define(`vme_msg_2',             `msg_reg2')
 158 define(`vme_msg_3',             `vme_msg_2')
 159 define(`vme_msg_4',             `msg_reg3')
 160
 161