2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Xiang Haihao <haihao.xiang@intel.com>
27 define(`BIND_IDX_VME', `0')
28 define(`BIND_IDX_VME_REF0', `1')
29 define(`BIND_IDX_VME_REF1', `2')
30 define(`BIND_IDX_OUTPUT', `3')
31 define(`BIND_IDX_INEP', `4')
32 define(`BIND_IDX_VME_BATCHBUFFER', `5')
36 define(`OBW_CACHE_TYPE', `5')
40 define(`OBW_CACHE_TYPE', `10')
44 define(`OBW_MESSAGE_TYPE', `8')
46 define(`OBW_BIND_IDX', `BIND_IDX_VME_BATCHBUFFER')
48 define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */
49 define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */
50 define(`OBW_CONTROL_2', `2') /* 2 OWords */
51 define(`OBW_CONTROL_3', `3') /* 4 OWords */
52 define(`OBW_CONTROL_4', `4') /* 8 OWords */
56 define(`OBW_WRITE_COMMIT_CATEGORY', `1') /* write commit on Sandybrige */
60 define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */
64 define(`OBW_HEADER_PRESENT', `1')
66 define(`CMD_MEDIA_OBJECT', `0x71000006:UD')
67 define(`MI_BATCH_BUFFER_END', `0x05000000:UD')
69 define(`NUM_MACROBLOCKS_PER_COMMAND', `512')
73 * r1~r4 constant buffer (reserved)
76 * r8~r15 temporary registers
77 * r16 media object command
79 * r18 write back of Oword Block Write
84 define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */
87 * GRF 1~4 -- Constant Buffer (reserved)
91 * GRF 5 -- inline data
93 define(`inline_reg0', `r5')
94 define(`total_mbs', `inline_reg0.0') /* the number of macroblocks in a picture */
95 define(`transform_8x8_ub', `inline_reg0.4') /* transform_8x8 flag */
96 define(`mtype_ub', `inline_reg0.5') /* 0: INTRA, 1: INTER */
97 define(`width_in_mb', `inline_reg0.6') /* the picture width in macroblocks */
100 * GRF 8~15 -- temporary registers
102 define(`tmp_reg0', `r8')
103 define(`obw_header', `tmp_reg0')
104 define(`tmp_reg1', `r9')
105 define(`count', `tmp_reg1.0')
106 define(`remainder_cmds', `tmp_reg1.4')
107 define(`width_per_row', `tmp_reg1.8')
108 define(`tmp_reg2', `r10')
109 define(`quotient', `tmp_reg2')
110 define(`tmp_reg3', `r11')
111 define(`remainder', `tmp_reg3')
112 define(`tmp_reg4', `r12')
113 define(`tmp_reg5', `r13')
114 define(`tmp_reg6', `r14')
115 define(`tmp_reg7', `r15')
120 define(`media_object_ud', `r16.0')
121 define(`media_object0_ud', `r16.0')
122 define(`media_object1_ud', `r16.4')
123 define(`media_object2_ud', `r16.8')
124 define(`media_object3_ud', `r16.12')
125 define(`media_object4_ud', `r16.16')
126 define(`media_object5_ud', `r16.20')
127 define(`media_object6_ud', `r16.24')
128 define(`media_object6_xy', `r16.24')
129 define(`media_object6_x', `r16.24')
130 define(`media_object6_y', `r16.25')
131 define(`media_object6_width', `r16.26')
132 define(`media_object7_ud', `r16.28')
133 define(`media_object7_flag', `r16.28')
134 define(`media_object7_num_mbs', `r16.30')
137 * GRF 18 write back for Oword Block Write message
142 define(`obw_wb', `r18')
143 define(`obw_wb_length', `1')
148 * write commit is removed on Ivybridge
150 define(`obw_wb', `null<1>:W')
151 define(`obw_wb_length', `0')
156 * Message Payload registers
160 define(`msg_ind', `0')
161 define(`msg_reg0', `m0')
162 define(`msg_reg1', `m1')
163 define(`msg_reg2', `m2')
164 define(`msg_reg3', `m3')
165 define(`msg_reg4', `m4')
166 define(`msg_reg5', `m5')
167 define(`msg_reg6', `m6')
168 define(`msg_reg7', `m7')
169 define(`msg_reg8', `m8')
173 define(`msg_ind', `64')
174 define(`msg_reg0', `g64')
175 define(`msg_reg1', `g65')
176 define(`msg_reg2', `g66')
177 define(`msg_reg3', `g67')
178 define(`msg_reg4', `g68')
179 define(`msg_reg5', `g69')
180 define(`msg_reg6', `g70')
181 define(`msg_reg7', `g71')
182 define(`msg_reg8', `g72')