2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 define(`data_port_msg_2_0', `g64')
29 define(`data_port_msg_2_1', `g65')
30 define(`data_port_msg_2_ind', `64')
32 mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable};
33 mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable};
36 * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel,
37 * g70-g71 for Blue and g72-g73 for Alpha channel
39 define(`slot_r_00', `g66')
40 define(`slot_r_01', `g67')
41 define(`slot_g_00', `g68')
42 define(`slot_g_01', `g69')
43 define(`slot_b_00', `g70')
44 define(`slot_b_01', `g71')
45 define(`slot_a_00', `g72')
46 define(`slot_a_01', `g73')
48 mov (8) slot_r_00<1>F src_sample_r_01<1>F { align1 mask_disable };
49 mov (8) slot_r_01<1>F src_sample_r_23<1>F { align1 mask_disable };
51 mov (8) slot_g_00<1>F src_sample_g_01<1>F { align1 mask_disable };
52 mov (8) slot_g_01<1>F src_sample_g_23<1>F { align1 mask_disable };
54 mov (8) slot_b_00<1>F src_sample_b_01<1>F { align1 mask_disable };
55 mov (8) slot_b_01<1>F src_sample_b_23<1>F { align1 mask_disable };
57 mov (8) slot_a_00<1>F src_sample_a_01<1>F { align1 mask_disable };
58 mov (8) slot_a_01<1>F src_sample_a_23<1>F { align1 mask_disable };
65 0, /* binding table index */
66 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */
67 12, /* render target write */
68 0, /* ignore for Ivybridge */
69 1 /* header present */