2 * Copyright 2000-2011 Intel Corporation All Rights Reserved
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
8 * http://www.apache.org/licenses/LICENSE-2.0
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
16 * Zhao Yakui <yakui.zhao@intel.com>
21 // Module name: common.inc
23 // Common header file for all Video-Processing kernels
26 .default_execution_size (16)
27 .default_register_type :ub
32 //========== Common constants ==========
35 //========== Macros ==========
38 //Fast Jump, For more details see "Set_Layer_N.asm"
41 //========== Defines ====================
43 //========== Static Parameters (Common To All) ==========
49 // e.g. byte0 byte1 byte2
53 //Color Pipe (IECP) parameters
61 // e.g. byte0 byte1 byte2
66 //========== Inline parameters (Common To All) ===========
69 //============== Binding Index Table===========
70 //Common between DNDI and DNUV
73 //================= Common Message Descriptor =====
74 // Message descriptor for thread spawning
75 // Message Descriptors
76 // = 000 0001 (min message len 1 ) 0,0000 (resp len 0 -add later)
78 // 0001(Spawn a root thread),0001 (Root thread spawn thread)
80 // Thread Spawner Message Descriptor
83 // Message descriptor for atomic operation add
84 // Message Descriptors
85 // = 000 0110 (min message len 6 ) 0,0000 (resp len 0 -add later)
86 // 1(header present)001,10(typed atomic operation)0(return enabled)0(slot group, low 8 bits),0111 (AOP_Add)
87 // 0000,0000 (Binding table index, added later)
90 // Atomic Operation Add Message Descriptor
93 // Message descriptor for dataport media write
94 // Message Descriptors
95 // = 000 0001 (min message len 1 - add later) 00000 (resp len 0)
96 // 1 (header present 1) 0 1010 (media block write) 000000
97 // 00000000 (binding table index - set later)
101 // Message Length defines
104 // Response Length defines
107 // Block Width and Height Size defines
110 // Extended Message Descriptors
113 // Common message descriptors:
116 //===================== Math Function Control ===================================
119 //============ Message Registers ===============
120 // buf4 starts from r28
123 //#define mMSGHDR_EOT r43 // Dummy Message Register for EOT
126 .declare mubMSGPAYLOAD Base=r30 ElementSize=1 SrcRegion=<16;16,1> Type=ub
127 .declare muwMSGPAYLOAD Base=r30 ElementSize=2 SrcRegion=<16;16,1> Type=uw
128 .declare mudMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=ud
129 .declare mfMSGPAYLOAD Base=r30 ElementSize=4 SrcRegion=<8;8,1> Type=f
131 //=================== End of thread instruction ===========================
134 //=====================Pointers Used=====================================
137 //=======================================================================
141 // Define temp space for any usages
147 // temp space for rotation
149 .declare fROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f
151 .declare udROBUF Base=r9.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud
153 .declare uwROBUF Base=r9.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw
155 .declare ubROBUF Base=r9.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub
157 .declare ub4ROBUF Base=r9.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub
163 // Module name: Save_AVS_RGBX.asm
165 // Save packed ARGB 444 frame data block of size 16x16
167 // To save 16x16 block (64x16 byte layout for ARGB8888) we need 4 send instructions with 32x8 in each
172 // the 4 32x8 block send is used
176 // Module name: Save.inc
181 // Description: Includes all definitions explicit to Fast Composite.
189 //========== GRF partition ==========
190 // r0 header : r0 (1 GRF)
191 // Static parameters : r1 - r6 (6 GRFS)
192 // Inline parameters : r7 - r8 (2 GRFs)
193 // MSGSRC : r27 (1 GRF)
194 //===================================
197 //========== Static Parameters (Explicit To Fast Composite) ==========
202 .declare udCSC_CURBE Base=r1.0 ElementSize=4 Type=ud
219 // 0: 0-degree, 1: 90, 2: 180, 3: 270-degree, clockwise.
221 .declare ubCOLOR_PIXEL_VAL Base=r2.20 ElementSize=1 SrcRegion=<0;1,0> DstRegion=<1> Type=ub
224 //Normalised Ratio of Horizontal step size with main video for all layers
227 //Normalised Ratio of Horizontal step size with main video for all layers becomes
228 //Normalised Horizontal step size for all layers in VP_Setup.asm
232 //Normalised Vertical step size for all layers
236 //Normalised Vertical Frame Origin for all layers
240 //Normalised Horizontal Frame Origin for all layers
243 //========== Inline Parameters (Explicit To Fast Composite) ==========
249 //====================== Binding table (Explicit To Fast Composite)=========================================
252 //Used by Interlaced Scaling Kernels
255 //========== Sampler State Table Index (Explicit To Fast Composite)==========
256 //Sampler Index for AVS/IEF messages
259 //Sampler Index for SIMD16 sampler messages
262 //=============================================================================
264 .declare fBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f
265 .declare fBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f
266 .declare fBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f
267 .declare fBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f
268 .declare fBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f
269 .declare fBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=f
271 .declare udBUFFER_0 Base=r64.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud
272 .declare udBUFFER_1 Base=r80.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud
273 .declare udBUFFER_2 Base=r96.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud
274 .declare udBUFFER_3 Base=r112.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud
275 .declare udBUFFER_4 Base=r28.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud
276 .declare udBUFFER_5 Base=r46.0 ElementSize=4 SrcRegion=<8;8,1> DstRegion=<1> Type=ud
278 .declare uwBUFFER_0 Base=r64.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw
279 .declare uwBUFFER_1 Base=r80.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw
280 .declare uwBUFFER_2 Base=r96.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw
281 .declare uwBUFFER_3 Base=r112.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw
282 .declare uwBUFFER_4 Base=r28.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw
283 .declare uwBUFFER_5 Base=r46.0 ElementSize=2 SrcRegion=<16;16,1> DstRegion=<1> Type=uw
285 .declare ubBUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub
286 .declare ubBUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub
287 .declare ubBUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub
288 .declare ubBUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub
289 .declare ubBUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub
290 .declare ubBUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<16;16,1> DstRegion=<1> Type=ub
292 .declare ub4BUFFER_0 Base=r64.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub
293 .declare ub4BUFFER_1 Base=r80.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub
294 .declare ub4BUFFER_2 Base=r96.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub
295 .declare ub4BUFFER_3 Base=r112.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub
296 .declare ub4BUFFER_4 Base=r28.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub
297 .declare ub4BUFFER_5 Base=r46.0 ElementSize=1 SrcRegion=<32;8,4> DstRegion=<4> Type=ub
299 //Pointer to mask reg
305 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use
306 // NODDCLR, NODDCHK flags. -rT
309 .declare udCSC_COEFF_0 Base=r18.0 ElementSize=4 Type=ud // 1 GRF
314 .declare udCSC_COEFF_1 Base=r19.0 ElementSize=4 Type=ud // 1 GRF
319 .declare uwALPHA_MASK_REG_TEMP Base=r20.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF
323 .declare uwALPHA_MASK_REG Base=r21.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw // 1 GRF
328 //Always keep Cannel Pointers and Offsets in same GRF, so that we can use
329 // NODDCLR, NODDCHK flags. -rT
332 //Keep fORIGIN_X_NLAS, fY_OFFSET_2ND_BLOCK, fSTEP_X_NLAS, pMSGDSC_COPY, ubCONST_ALPHA_COPY as
333 //sub registers of same GRF to enable using NODDCLR NODDCHK. -rT
350 //defines to generate LABELS during compile time.
353 //Msg payload buffers; upto 4 full-size messages can be written
356 .declare mudMSGPAYLOAD0 Base=r29.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud
357 .declare mudMSGPAYLOAD1 Base=r38.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud
358 .declare mudMSGPAYLOAD2 Base=r47.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud
359 .declare mudMSGPAYLOAD3 Base=r56.0 ElementSize=4 SrcRegion=<8;8,1> Type=ud
361 .declare muwMSGPAYLOAD0 Base=r29.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw
362 .declare muwMSGPAYLOAD1 Base=r38.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw
363 .declare muwMSGPAYLOAD2 Base=r47.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw
364 .declare muwMSGPAYLOAD3 Base=r56.0 ElementSize=2 SrcRegion=<16;16,1> Type=uw
366 .declare mubMSGPAYLOAD0 Base=r29.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
367 .declare mubMSGPAYLOAD1 Base=r38.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
368 .declare mubMSGPAYLOAD2 Base=r47.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
369 .declare mubMSGPAYLOAD3 Base=r56.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
370 .declare mubMSGPAYLOAD4 Base=r32.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
371 .declare mubMSGPAYLOAD5 Base=r41.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
372 .declare mubMSGPAYLOAD6 Base=r50.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
373 .declare mubMSGPAYLOAD7 Base=r59.0 ElementSize=1 SrcRegion=<16;16,1> Type=ub
376 // the r17 register (nTEMP0) is originally defined from "Common.inc"
377 // instead of re-defining a nTEMP0 here, we use "SAVE_RGB" suffix for its naming
379 .declare uwTemp0 Base=r17.0 ElementSize=2 Type=uw
385 // At the save module we have all 8 address sub-registers available.
386 // So we will use PING-PONG type of scheme to save the data using
387 // pointers pBUF_CHNL_TOP_8x4 and pBUF_CHNL_BOT_8x4. This will help
388 // reduce dependency. - rT
390 //Internal LAYOUT:(RRGGBBAA)
391 //Assign buffer channel order for Buffer 0123 in the order RGBA a0.3>A, a0.2>B, a0.1>G, a0.0>R
392 // R = 0, G= 4, B = 8, A = 12.
393 mov (4) acc0.0<1>:w 0x62EA:v
394 add (4) acc0.0<1>:w acc0<4;4,1>:w 70:uw
395 shl (4) r22.0<1>:w acc0<4;4,1>:w 5:uw
398 // This means that it should be BGRA(B is the LSB) or RGBA
399 // the internal format is always RGBA(MSB-A-B-G-R).
400 and.nz.f0.0 null<1>:w r2.3<0;1,0>:uw 0x01:w
402 //wBUFF_CHNL_PTR points to either buffer 0 or buffer 4.
403 //Add appropriate offsets to get pointers for all buffers (1,2,3 or 5).
404 //Offsets are zero for buffer 0 and buffer 4.
405 add (4) a0.0:uw r22.0<4;4,1>:w 0:uw
408 (f0.0) mov (1) uwTemp0<1> a0.0:uw
409 (f0.0) mov (1) a0.0:uw a0.2:uw
410 (f0.0) mov (1) a0.2:uw uwTemp0<0;1,0>
412 shl (1) r27.0<1>:d r7.0<0;1,0>:w 2:w { NoDDClr } // H. block origin need to be quadrupled
413 mov (1) r27.1<1>:d r7.1<0;1,0>:w { NoDDClr, NoDDChk } // Block origin (1st quadrant)
414 mov (1) r27.2<1>:ud 0x7001F:ud { NoDDChk } // Block width and height (64x4)
416 mov (4) a0.4:uw a0.0<4;4,1>:uw
418 mov (8) r28<1>:ud r27<8;8,1>:ud
419 mov (8) r37<1>:ud r27<8;8,1>:ud
420 mov (8) r46<1>:ud r27<8;8,1>:ud
421 mov (8) r55<1>:ud r27<8;8,1>:ud
423 mov (8) r31<1>:ud r27<8;8,1>:ud
424 mov (8) r40<1>:ud r27<8;8,1>:ud
425 mov (8) r49<1>:ud r27<8;8,1>:ud
426 mov (8) r58<1>:ud r27<8;8,1>:ud
429 //for block 1(The right part of buffer 0 and buffer 1)
430 add (1) r37.0<1>:d r27.0<0;1,0>:d 32:d
432 //for block 2(the left part of buffer 2 and buffer 3)
433 add (1) r46.1<1>:d r27.1<0;1,0>:d 8:d
435 //for block 3(the right part of buffer 2 and buffer 3)
436 add (1) r55.1<1>:d r27.1<0;1,0>:d 8:d
437 add (1) r55.0<1>:d r27.0<0;1,0>:d 32:d
439 // write Buf_0 to 1st quarter of four horizontal output blocks
441 // Please note the scattered order of NODDCLR, NODDCHK flags. Since the sub-registers
442 // of destination reg are not updated at one place and hence even flags are scattered. -rT
444 /* for block 0 the left part of buffer 0 and 1 */
445 mov (8) mubMSGPAYLOAD0(0, 0)<4> r[a0.0, 1]<16;8,2>:ub
446 mov (8) mubMSGPAYLOAD0(0, 1)<4> r[a0.1, 1]<16;8,2>:ub
447 mov (8) mubMSGPAYLOAD0(0, 2)<4> r[a0.2, 1]<16;8,2>:ub
448 mov (8) mubMSGPAYLOAD0(0, 3)<4> r2.31:ub
450 mov (8) mubMSGPAYLOAD0(1, 0)<4> r[a0.0, 33]<16;8,2>:ub
451 mov (8) mubMSGPAYLOAD0(1, 1)<4> r[a0.1, 33]<16;8,2>:ub
452 mov (8) mubMSGPAYLOAD0(1, 2)<4> r[a0.2, 33]<16;8,2>:ub
453 mov (8) mubMSGPAYLOAD0(1, 3)<4> r2.31:ub
455 mov (8) mubMSGPAYLOAD1(0, 0)<4> r[a0.0, 17]<16;8,2>:ub
456 mov (8) mubMSGPAYLOAD1(0, 1)<4> r[a0.1, 17]<16;8,2>:ub
457 mov (8) mubMSGPAYLOAD1(0, 2)<4> r[a0.2, 17]<16;8,2>:ub
458 mov (8) mubMSGPAYLOAD1(0, 3)<4> r2.31:ub
460 mov (8) mubMSGPAYLOAD1(1, 0)<4> r[a0.0, 49]<16;8,2>:ub
461 mov (8) mubMSGPAYLOAD1(1, 1)<4> r[a0.1, 49]<16;8,2>:ub
462 mov (8) mubMSGPAYLOAD1(1, 2)<4> r[a0.2, 49]<16;8,2>:ub
463 mov (8) mubMSGPAYLOAD1(1, 3)<4> r2.31:ub
465 add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw
467 mov (8) mubMSGPAYLOAD0(2, 0)<4> r[a0.0, 1]<16;8,2>:ub
468 mov (8) mubMSGPAYLOAD0(2, 1)<4> r[a0.1, 1]<16;8,2>:ub
469 mov (8) mubMSGPAYLOAD0(2, 2)<4> r[a0.2, 1]<16;8,2>:ub
470 mov (8) mubMSGPAYLOAD0(2, 3)<4> r2.31:ub
472 mov (8) mubMSGPAYLOAD0(3, 0)<4> r[a0.0, 33]<16;8,2>:ub
473 mov (8) mubMSGPAYLOAD0(3, 1)<4> r[a0.1, 33]<16;8,2>:ub
474 mov (8) mubMSGPAYLOAD0(3, 2)<4> r[a0.2, 33]<16;8,2>:ub
475 mov (8) mubMSGPAYLOAD0(3, 3)<4> r2.31:ub
477 mov (8) mubMSGPAYLOAD1(2, 0)<4> r[a0.0, 17]<16;8,2>:ub
478 mov (8) mubMSGPAYLOAD1(2, 1)<4> r[a0.1, 17]<16;8,2>:ub
479 mov (8) mubMSGPAYLOAD1(2, 2)<4> r[a0.2, 17]<16;8,2>:ub
480 mov (8) mubMSGPAYLOAD1(2, 3)<4> r2.31:ub
482 mov (8) mubMSGPAYLOAD1(3, 0)<4> r[a0.0, 49]<16;8,2>:ub
483 mov (8) mubMSGPAYLOAD1(3, 1)<4> r[a0.1, 49]<16;8,2>:ub
484 mov (8) mubMSGPAYLOAD1(3, 2)<4> r[a0.2, 49]<16;8,2>:ub
485 mov (8) mubMSGPAYLOAD1(3, 3)<4> r2.31:ub
487 add (4) a0.0:uw a0.4<4;4,1>:uw 512:uw
488 mov (8) mubMSGPAYLOAD0(4, 0)<4> r[a0.0, 1]<16;8,2>:ub
489 mov (8) mubMSGPAYLOAD0(4, 1)<4> r[a0.1, 1]<16;8,2>:ub
490 mov (8) mubMSGPAYLOAD0(4, 2)<4> r[a0.2, 1]<16;8,2>:ub
491 mov (8) mubMSGPAYLOAD0(4, 3)<4> r2.31:ub
493 mov (8) mubMSGPAYLOAD0(5, 0)<4> r[a0.0, 33]<16;8,2>:ub
494 mov (8) mubMSGPAYLOAD0(5, 1)<4> r[a0.1, 33]<16;8,2>:ub
495 mov (8) mubMSGPAYLOAD0(5, 2)<4> r[a0.2, 33]<16;8,2>:ub
496 mov (8) mubMSGPAYLOAD0(5, 3)<4> r2.31:ub
498 mov (8) mubMSGPAYLOAD1(4, 0)<4> r[a0.0, 17]<16;8,2>:ub
499 mov (8) mubMSGPAYLOAD1(4, 1)<4> r[a0.1, 17]<16;8,2>:ub
500 mov (8) mubMSGPAYLOAD1(4, 2)<4> r[a0.2, 17]<16;8,2>:ub
501 mov (8) mubMSGPAYLOAD1(4, 3)<4> r2.31:ub
503 mov (8) mubMSGPAYLOAD1(5, 0)<4> r[a0.0, 49]<16;8,2>:ub
504 mov (8) mubMSGPAYLOAD1(5, 1)<4> r[a0.1, 49]<16;8,2>:ub
505 mov (8) mubMSGPAYLOAD1(5, 2)<4> r[a0.2, 49]<16;8,2>:ub
506 mov (8) mubMSGPAYLOAD1(5, 3)<4> r2.31:ub
508 add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw
509 mov (8) mubMSGPAYLOAD0(6, 0)<4> r[a0.0, 1]<16;8,2>:ub
510 mov (8) mubMSGPAYLOAD0(6, 1)<4> r[a0.1, 1]<16;8,2>:ub
511 mov (8) mubMSGPAYLOAD0(6, 2)<4> r[a0.2, 1]<16;8,2>:ub
512 mov (8) mubMSGPAYLOAD0(6, 3)<4> r2.31:ub
514 mov (8) mubMSGPAYLOAD0(7, 0)<4> r[a0.0, 33]<16;8,2>:ub
515 mov (8) mubMSGPAYLOAD0(7, 1)<4> r[a0.1, 33]<16;8,2>:ub
516 mov (8) mubMSGPAYLOAD0(7, 2)<4> r[a0.2, 33]<16;8,2>:ub
517 mov (8) mubMSGPAYLOAD0(7, 3)<4> r2.31:ub
519 mov (8) mubMSGPAYLOAD1(6, 0)<4> r[a0.0, 17]<16;8,2>:ub
520 mov (8) mubMSGPAYLOAD1(6, 1)<4> r[a0.1, 17]<16;8,2>:ub
521 mov (8) mubMSGPAYLOAD1(6, 2)<4> r[a0.2, 17]<16;8,2>:ub
522 mov (8) mubMSGPAYLOAD1(6, 3)<4> r2.31:ub
524 mov (8) mubMSGPAYLOAD1(7, 0)<4> r[a0.0, 49]<16;8,2>:ub
525 mov (8) mubMSGPAYLOAD1(7, 1)<4> r[a0.1, 49]<16;8,2>:ub
526 mov (8) mubMSGPAYLOAD1(7, 2)<4> r[a0.2, 49]<16;8,2>:ub
527 mov (8) mubMSGPAYLOAD1(7, 3)<4> r2.31:ub
529 send (16) null<1>:d r28 0x5 0x120A8018:ud
530 send (16) null<1>:d r37 0x5 0x120A8018:ud
532 //for the block 2 and 3
533 add (4) a0.0:uw a0.4<4;4,1>:uw 1024:uw
534 mov (8) mubMSGPAYLOAD2(0, 0)<4> r[a0.0, 1]<16;8,2>:ub
535 mov (8) mubMSGPAYLOAD2(0, 1)<4> r[a0.1, 1]<16;8,2>:ub
536 mov (8) mubMSGPAYLOAD2(0, 2)<4> r[a0.2, 1]<16;8,2>:ub
537 mov (8) mubMSGPAYLOAD2(0, 3)<4> r2.31:ub
539 mov (8) mubMSGPAYLOAD2(1, 0)<4> r[a0.0, 33]<16;8,2>:ub
540 mov (8) mubMSGPAYLOAD2(1, 1)<4> r[a0.1, 33]<16;8,2>:ub
541 mov (8) mubMSGPAYLOAD2(1, 2)<4> r[a0.2, 33]<16;8,2>:ub
542 mov (8) mubMSGPAYLOAD2(1, 3)<4> r2.31:ub
544 mov (8) mubMSGPAYLOAD3(0, 0)<4> r[a0.0, 17]<16;8,2>:ub
545 mov (8) mubMSGPAYLOAD3(0, 1)<4> r[a0.1, 17]<16;8,2>:ub
546 mov (8) mubMSGPAYLOAD3(0, 2)<4> r[a0.2, 17]<16;8,2>:ub
547 mov (8) mubMSGPAYLOAD3(0, 3)<4> r2.31:ub
549 mov (8) mubMSGPAYLOAD3(1, 0)<4> r[a0.0, 33]<16;8,2>:ub
550 mov (8) mubMSGPAYLOAD3(1, 1)<4> r[a0.1, 33]<16;8,2>:ub
551 mov (8) mubMSGPAYLOAD3(1, 2)<4> r[a0.2, 33]<16;8,2>:ub
552 mov (8) mubMSGPAYLOAD3(1, 3)<4> r2.31:ub
554 add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw
555 mov (8) mubMSGPAYLOAD2(2, 0)<4> r[a0.0, 1]<16;8,2>:ub
556 mov (8) mubMSGPAYLOAD2(2, 1)<4> r[a0.1, 1]<16;8,2>:ub
557 mov (8) mubMSGPAYLOAD2(2, 2)<4> r[a0.2, 1]<16;8,2>:ub
558 mov (8) mubMSGPAYLOAD2(2, 3)<4> r2.31:ub
560 mov (8) mubMSGPAYLOAD2(3, 0)<4> r[a0.0, 33]<16;8,2>:ub
561 mov (8) mubMSGPAYLOAD2(3, 1)<4> r[a0.1, 33]<16;8,2>:ub
562 mov (8) mubMSGPAYLOAD2(3, 2)<4> r[a0.2, 33]<16;8,2>:ub
563 mov (8) mubMSGPAYLOAD2(3, 3)<4> r2.31:ub
565 mov (8) mubMSGPAYLOAD3(2, 0)<4> r[a0.0, 17]<16;8,2>:ub
566 mov (8) mubMSGPAYLOAD3(2, 1)<4> r[a0.1, 17]<16;8,2>:ub
567 mov (8) mubMSGPAYLOAD3(2, 2)<4> r[a0.2, 17]<16;8,2>:ub
568 mov (8) mubMSGPAYLOAD3(2, 3)<4> r2.31:ub
570 mov (8) mubMSGPAYLOAD3(3, 0)<4> r[a0.0, 49]<16;8,2>:ub
571 mov (8) mubMSGPAYLOAD3(3, 1)<4> r[a0.1, 49]<16;8,2>:ub
572 mov (8) mubMSGPAYLOAD3(3, 2)<4> r[a0.2, 49]<16;8,2>:ub
573 mov (8) mubMSGPAYLOAD3(3, 3)<4> r2.31:ub
575 add (4) a0.0:uw a0.4<4;4,1>:uw 1536:uw
576 mov (8) mubMSGPAYLOAD2(4, 0)<4> r[a0.0, 1]<16;8,2>:ub
577 mov (8) mubMSGPAYLOAD2(4, 1)<4> r[a0.1, 1]<16;8,2>:ub
578 mov (8) mubMSGPAYLOAD2(4, 2)<4> r[a0.2, 1]<16;8,2>:ub
579 mov (8) mubMSGPAYLOAD2(4, 3)<4> r2.31:ub
581 mov (8) mubMSGPAYLOAD2(5, 0)<4> r[a0.0, 33]<16;8,2>:ub
582 mov (8) mubMSGPAYLOAD2(5, 1)<4> r[a0.1, 33]<16;8,2>:ub
583 mov (8) mubMSGPAYLOAD2(5, 2)<4> r[a0.2, 33]<16;8,2>:ub
584 mov (8) mubMSGPAYLOAD2(5, 3)<4> r2.31:ub
586 mov (8) mubMSGPAYLOAD3(4, 0)<4> r[a0.0, 17]<16;8,2>:ub
587 mov (8) mubMSGPAYLOAD3(4, 1)<4> r[a0.1, 17]<16;8,2>:ub
588 mov (8) mubMSGPAYLOAD3(4, 2)<4> r[a0.2, 17]<16;8,2>:ub
589 mov (8) mubMSGPAYLOAD3(4, 3)<4> r2.31:ub
591 mov (8) mubMSGPAYLOAD3(5, 0)<4> r[a0.0, 49]<16;8,2>:ub
592 mov (8) mubMSGPAYLOAD3(5, 1)<4> r[a0.1, 49]<16;8,2>:ub
593 mov (8) mubMSGPAYLOAD3(5, 2)<4> r[a0.2, 49]<16;8,2>:ub
594 mov (8) mubMSGPAYLOAD3(5, 3)<4> r2.31:ub
596 add (4) a0.0:uw a0.0<4;4,1>:uw 64:uw
597 mov (8) mubMSGPAYLOAD2(6, 0)<4> r[a0.0, 1]<16;8,2>:ub
598 mov (8) mubMSGPAYLOAD2(6, 1)<4> r[a0.1, 1]<16;8,2>:ub
599 mov (8) mubMSGPAYLOAD2(6, 2)<4> r[a0.2, 1]<16;8,2>:ub
600 mov (8) mubMSGPAYLOAD2(6, 3)<4> r2.31:ub
602 mov (8) mubMSGPAYLOAD2(7, 0)<4> r[a0.0, 33]<16;8,2>:ub
603 mov (8) mubMSGPAYLOAD2(7, 1)<4> r[a0.1, 33]<16;8,2>:ub
604 mov (8) mubMSGPAYLOAD2(7, 2)<4> r[a0.2, 33]<16;8,2>:ub
605 mov (8) mubMSGPAYLOAD2(7, 3)<4> r2.31:ub
607 mov (8) mubMSGPAYLOAD3(6, 0)<4> r[a0.0, 17]<16;8,2>:ub
608 mov (8) mubMSGPAYLOAD3(6, 1)<4> r[a0.1, 17]<16;8,2>:ub
609 mov (8) mubMSGPAYLOAD3(6, 2)<4> r[a0.2, 17]<16;8,2>:ub
610 mov (8) mubMSGPAYLOAD3(6, 3)<4> r2.31:ub
612 mov (8) mubMSGPAYLOAD3(7, 0)<4> r[a0.0, 49]<16;8,2>:ub
613 mov (8) mubMSGPAYLOAD3(7, 1)<4> r[a0.1, 49]<16;8,2>:ub
614 mov (8) mubMSGPAYLOAD3(7, 2)<4> r[a0.2, 49]<16;8,2>:ub
615 mov (8) mubMSGPAYLOAD3(7, 3)<4> r2.31:ub
618 send (16) null<1>:d r46 0x5 0x120A8018:ud
619 send (16) null<1>:d r55 0x5 0x120A8018:ud