1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_MIPS_CONSTANTS_H_
6 #define V8_MIPS_CONSTANTS_H_
8 #include "src/base/logging.h"
9 #include "src/base/macros.h"
10 #include "src/globals.h"
12 // UNIMPLEMENTED_ macro for MIPS.
14 #define UNIMPLEMENTED_MIPS() \
15 v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \
16 __FILE__, __LINE__, __func__)
18 #define UNIMPLEMENTED_MIPS()
21 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
29 #ifdef _MIPS_ARCH_MIPS64R2
30 static const ArchVariants kArchVariant = kMips64r2;
31 #elif _MIPS_ARCH_MIPS64R6
32 static const ArchVariants kArchVariant = kMips64r6;
34 static const ArchVariants kArchVariant = kMips64r2;
38 enum Endianness { kLittle, kBig };
40 #if defined(V8_TARGET_LITTLE_ENDIAN)
41 static const Endianness kArchEndian = kLittle;
42 #elif defined(V8_TARGET_BIG_ENDIAN)
43 static const Endianness kArchEndian = kBig;
45 #error Unknown endianness
48 // TODO(plind): consider deriving ABI from compiler flags or build system.
50 // ABI-dependent definitions are made with #define in simulator-mips64.h,
51 // so the ABI choice must be available to the pre-processor. However, in all
52 // other cases, we should use the enum AbiVariants with normal if statements.
54 #define MIPS_ABI_N64 1
55 // #define MIPS_ABI_O32 1
57 // The only supported Abi's are O32, and n64.
60 kN64 // Use upper case N for 'n64' ABI to conform to style standard.
64 static const AbiVariants kMipsAbi = kN64;
66 static const AbiVariants kMipsAbi = kO32;
70 // TODO(plind): consider renaming these ...
71 #if(defined(__mips_hard_float) && __mips_hard_float != 0)
72 // Use floating-point coprocessor instructions. This flag is raised when
73 // -mhard-float is passed to the compiler.
74 const bool IsMipsSoftFloatABI = false;
75 #elif(defined(__mips_soft_float) && __mips_soft_float != 0)
76 // This flag is raised when -msoft-float is passed to the compiler.
77 // Although FPU is a base requirement for v8, soft-float ABI is used
78 // on soft-float systems with FPU kernel emulation.
79 const bool IsMipsSoftFloatABI = true;
81 const bool IsMipsSoftFloatABI = true;
85 #ifndef __STDC_FORMAT_MACROS
86 #define __STDC_FORMAT_MACROS
91 // Defines constants and accessor classes to assemble, disassemble and
92 // simulate MIPS32 instructions.
94 // See: MIPS32 Architecture For Programmers
95 // Volume II: The MIPS32 Instruction Set
96 // Try www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol2.pdf.
101 // -----------------------------------------------------------------------------
102 // Registers and FPURegisters.
104 // Number of general purpose registers.
105 const int kNumRegisters = 32;
106 const int kInvalidRegister = -1;
108 // Number of registers with HI, LO, and pc.
109 const int kNumSimuRegisters = 35;
111 // In the simulator, the PC register is simulated as the 34th register.
112 const int kPCRegister = 34;
114 // Number coprocessor registers.
115 const int kNumFPURegisters = 32;
116 const int kInvalidFPURegister = -1;
118 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
119 const int kFCSRRegister = 31;
120 const int kInvalidFPUControlRegister = -1;
121 const uint32_t kFPUInvalidResult = static_cast<uint32_t>(1 << 31) - 1;
122 const uint64_t kFPU64InvalidResult =
123 static_cast<uint64_t>(static_cast<uint64_t>(1) << 63) - 1;
126 const uint32_t kFCSRInexactFlagBit = 2;
127 const uint32_t kFCSRUnderflowFlagBit = 3;
128 const uint32_t kFCSROverflowFlagBit = 4;
129 const uint32_t kFCSRDivideByZeroFlagBit = 5;
130 const uint32_t kFCSRInvalidOpFlagBit = 6;
132 const uint32_t kFCSRInexactFlagMask = 1 << kFCSRInexactFlagBit;
133 const uint32_t kFCSRUnderflowFlagMask = 1 << kFCSRUnderflowFlagBit;
134 const uint32_t kFCSROverflowFlagMask = 1 << kFCSROverflowFlagBit;
135 const uint32_t kFCSRDivideByZeroFlagMask = 1 << kFCSRDivideByZeroFlagBit;
136 const uint32_t kFCSRInvalidOpFlagMask = 1 << kFCSRInvalidOpFlagBit;
138 const uint32_t kFCSRFlagMask =
139 kFCSRInexactFlagMask |
140 kFCSRUnderflowFlagMask |
141 kFCSROverflowFlagMask |
142 kFCSRDivideByZeroFlagMask |
143 kFCSRInvalidOpFlagMask;
145 const uint32_t kFCSRExceptionFlagMask = kFCSRFlagMask ^ kFCSRInexactFlagMask;
147 // 'pref' instruction hints
148 const int32_t kPrefHintLoad = 0;
149 const int32_t kPrefHintStore = 1;
150 const int32_t kPrefHintLoadStreamed = 4;
151 const int32_t kPrefHintStoreStreamed = 5;
152 const int32_t kPrefHintLoadRetained = 6;
153 const int32_t kPrefHintStoreRetained = 7;
154 const int32_t kPrefHintWritebackInvalidate = 25;
155 const int32_t kPrefHintPrepareForStore = 30;
157 // Helper functions for converting between register numbers and names.
160 // Return the name of the register.
161 static const char* Name(int reg);
163 // Lookup the register number for the name provided.
164 static int Number(const char* name);
166 struct RegisterAlias {
171 static const int64_t kMaxValue = 0x7fffffffffffffffl;
172 static const int64_t kMinValue = 0x8000000000000000l;
175 static const char* names_[kNumSimuRegisters];
176 static const RegisterAlias aliases_[];
179 // Helper functions for converting between register numbers and names.
182 // Return the name of the register.
183 static const char* Name(int reg);
185 // Lookup the register number for the name provided.
186 static int Number(const char* name);
188 struct RegisterAlias {
194 static const char* names_[kNumFPURegisters];
195 static const RegisterAlias aliases_[];
199 // -----------------------------------------------------------------------------
200 // Instructions encoding constants.
202 // On MIPS all instructions are 32 bits.
203 typedef int32_t Instr;
205 // Special Software Interrupt codes when used in the presence of the MIPS
207 enum SoftwareInterruptCodes {
208 // Transition to C code.
209 call_rt_redirected = 0xfffff
212 // On MIPS Simulator breakpoints can have different codes:
213 // - Breaks between 0 and kMaxWatchpointCode are treated as simple watchpoints,
214 // the simulator will run through them and print the registers.
215 // - Breaks between kMaxWatchpointCode and kMaxStopCode are treated as stop()
216 // instructions (see Assembler::stop()).
217 // - Breaks larger than kMaxStopCode are simple breaks, dropping you into the
219 const uint32_t kMaxWatchpointCode = 31;
220 const uint32_t kMaxStopCode = 127;
221 STATIC_ASSERT(kMaxWatchpointCode < kMaxStopCode);
224 // ----- Fields offset and length.
225 const int kOpcodeShift = 26;
226 const int kOpcodeBits = 6;
227 const int kRsShift = 21;
228 const int kRsBits = 5;
229 const int kRtShift = 16;
230 const int kRtBits = 5;
231 const int kRdShift = 11;
232 const int kRdBits = 5;
233 const int kSaShift = 6;
234 const int kSaBits = 5;
235 const int kFunctionShift = 0;
236 const int kFunctionBits = 6;
237 const int kLuiShift = 16;
238 const int kBp2Shift = 6;
239 const int kBp2Bits = 2;
240 const int kBp3Shift = 6;
241 const int kBp3Bits = 3;
243 const int kImm16Shift = 0;
244 const int kImm16Bits = 16;
245 const int kImm18Shift = 0;
246 const int kImm18Bits = 18;
247 const int kImm19Shift = 0;
248 const int kImm19Bits = 19;
249 const int kImm21Shift = 0;
250 const int kImm21Bits = 21;
251 const int kImm26Shift = 0;
252 const int kImm26Bits = 26;
253 const int kImm28Shift = 0;
254 const int kImm28Bits = 28;
255 const int kImm32Shift = 0;
256 const int kImm32Bits = 32;
258 // In branches and jumps immediate fields point to words, not bytes,
259 // and are therefore shifted by 2.
260 const int kImmFieldShift = 2;
262 const int kFrBits = 5;
263 const int kFrShift = 21;
264 const int kFsShift = 11;
265 const int kFsBits = 5;
266 const int kFtShift = 16;
267 const int kFtBits = 5;
268 const int kFdShift = 6;
269 const int kFdBits = 5;
270 const int kFCccShift = 8;
271 const int kFCccBits = 3;
272 const int kFBccShift = 18;
273 const int kFBccBits = 3;
274 const int kFBtrueShift = 16;
275 const int kFBtrueBits = 1;
277 // ----- Miscellaneous useful masks.
278 // Instruction bit masks.
279 const int kOpcodeMask = ((1 << kOpcodeBits) - 1) << kOpcodeShift;
280 const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
281 const int kImm18Mask = ((1 << kImm18Bits) - 1) << kImm18Shift;
282 const int kImm19Mask = ((1 << kImm19Bits) - 1) << kImm19Shift;
283 const int kImm21Mask = ((1 << kImm21Bits) - 1) << kImm21Shift;
284 const int kImm26Mask = ((1 << kImm26Bits) - 1) << kImm26Shift;
285 const int kImm28Mask = ((1 << kImm28Bits) - 1) << kImm28Shift;
286 const int kRsFieldMask = ((1 << kRsBits) - 1) << kRsShift;
287 const int kRtFieldMask = ((1 << kRtBits) - 1) << kRtShift;
288 const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift;
289 const int kSaFieldMask = ((1 << kSaBits) - 1) << kSaShift;
290 const int kFunctionFieldMask = ((1 << kFunctionBits) - 1) << kFunctionShift;
292 const int kHiMask = 0xffff << 16;
293 const int kLoMask = 0xffff;
294 const int kSignMask = 0x80000000;
295 const int kJumpAddrMask = (1 << (kImm26Bits + kImmFieldShift)) - 1;
296 const int64_t kHi16MaskOf64 = (int64_t)0xffff << 48;
297 const int64_t kSe16MaskOf64 = (int64_t)0xffff << 32;
298 const int64_t kTh16MaskOf64 = (int64_t)0xffff << 16;
299 const int32_t kJalRawMark = 0x00000000;
300 const int32_t kJRawMark = 0xf0000000;
302 // ----- MIPS Opcodes and Function Fields.
303 // We use this presentation to stay close to the table representation in
304 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
306 SPECIAL = 0 << kOpcodeShift,
307 REGIMM = 1 << kOpcodeShift,
309 J = ((0 << 3) + 2) << kOpcodeShift,
310 JAL = ((0 << 3) + 3) << kOpcodeShift,
311 BEQ = ((0 << 3) + 4) << kOpcodeShift,
312 BNE = ((0 << 3) + 5) << kOpcodeShift,
313 BLEZ = ((0 << 3) + 6) << kOpcodeShift,
314 BGTZ = ((0 << 3) + 7) << kOpcodeShift,
316 ADDI = ((1 << 3) + 0) << kOpcodeShift,
317 ADDIU = ((1 << 3) + 1) << kOpcodeShift,
318 SLTI = ((1 << 3) + 2) << kOpcodeShift,
319 SLTIU = ((1 << 3) + 3) << kOpcodeShift,
320 ANDI = ((1 << 3) + 4) << kOpcodeShift,
321 ORI = ((1 << 3) + 5) << kOpcodeShift,
322 XORI = ((1 << 3) + 6) << kOpcodeShift,
323 LUI = ((1 << 3) + 7) << kOpcodeShift, // LUI/AUI family.
324 DAUI = ((3 << 3) + 5) << kOpcodeShift,
326 BEQC = ((2 << 3) + 0) << kOpcodeShift,
327 COP1 = ((2 << 3) + 1) << kOpcodeShift, // Coprocessor 1 class.
328 BEQL = ((2 << 3) + 4) << kOpcodeShift,
329 BNEL = ((2 << 3) + 5) << kOpcodeShift,
330 BLEZL = ((2 << 3) + 6) << kOpcodeShift,
331 BGTZL = ((2 << 3) + 7) << kOpcodeShift,
333 DADDI = ((3 << 3) + 0) << kOpcodeShift, // This is also BNEC.
334 DADDIU = ((3 << 3) + 1) << kOpcodeShift,
335 LDL = ((3 << 3) + 2) << kOpcodeShift,
336 LDR = ((3 << 3) + 3) << kOpcodeShift,
337 SPECIAL2 = ((3 << 3) + 4) << kOpcodeShift,
338 SPECIAL3 = ((3 << 3) + 7) << kOpcodeShift,
340 LB = ((4 << 3) + 0) << kOpcodeShift,
341 LH = ((4 << 3) + 1) << kOpcodeShift,
342 LWL = ((4 << 3) + 2) << kOpcodeShift,
343 LW = ((4 << 3) + 3) << kOpcodeShift,
344 LBU = ((4 << 3) + 4) << kOpcodeShift,
345 LHU = ((4 << 3) + 5) << kOpcodeShift,
346 LWR = ((4 << 3) + 6) << kOpcodeShift,
347 LWU = ((4 << 3) + 7) << kOpcodeShift,
349 SB = ((5 << 3) + 0) << kOpcodeShift,
350 SH = ((5 << 3) + 1) << kOpcodeShift,
351 SWL = ((5 << 3) + 2) << kOpcodeShift,
352 SW = ((5 << 3) + 3) << kOpcodeShift,
353 SDL = ((5 << 3) + 4) << kOpcodeShift,
354 SDR = ((5 << 3) + 5) << kOpcodeShift,
355 SWR = ((5 << 3) + 6) << kOpcodeShift,
357 LWC1 = ((6 << 3) + 1) << kOpcodeShift,
358 BC = ((6 << 3) + 2) << kOpcodeShift,
359 LLD = ((6 << 3) + 4) << kOpcodeShift,
360 LDC1 = ((6 << 3) + 5) << kOpcodeShift,
361 POP66 = ((6 << 3) + 6) << kOpcodeShift,
362 LD = ((6 << 3) + 7) << kOpcodeShift,
364 PREF = ((6 << 3) + 3) << kOpcodeShift,
366 SWC1 = ((7 << 3) + 1) << kOpcodeShift,
367 BALC = ((7 << 3) + 2) << kOpcodeShift,
368 PCREL = ((7 << 3) + 3) << kOpcodeShift,
369 SCD = ((7 << 3) + 4) << kOpcodeShift,
370 SDC1 = ((7 << 3) + 5) << kOpcodeShift,
371 POP76 = ((7 << 3) + 6) << kOpcodeShift,
372 SD = ((7 << 3) + 7) << kOpcodeShift,
374 COP1X = ((1 << 4) + 3) << kOpcodeShift
377 enum SecondaryField {
378 // SPECIAL Encoding of Function Field.
379 SLL = ((0 << 3) + 0),
380 MOVCI = ((0 << 3) + 1),
381 SRL = ((0 << 3) + 2),
382 SRA = ((0 << 3) + 3),
383 SLLV = ((0 << 3) + 4),
384 SRLV = ((0 << 3) + 6),
385 SRAV = ((0 << 3) + 7),
388 JALR = ((1 << 3) + 1),
389 MOVZ = ((1 << 3) + 2),
390 MOVN = ((1 << 3) + 3),
391 BREAK = ((1 << 3) + 5),
393 MFHI = ((2 << 3) + 0),
394 CLZ_R6 = ((2 << 3) + 0),
395 CLO_R6 = ((2 << 3) + 1),
396 MFLO = ((2 << 3) + 2),
397 DSLLV = ((2 << 3) + 4),
398 DSRLV = ((2 << 3) + 6),
399 DSRAV = ((2 << 3) + 7),
401 MULT = ((3 << 3) + 0),
402 MULTU = ((3 << 3) + 1),
403 DIV = ((3 << 3) + 2),
404 DIVU = ((3 << 3) + 3),
405 DMULT = ((3 << 3) + 4),
406 DMULTU = ((3 << 3) + 5),
407 DDIV = ((3 << 3) + 6),
408 DDIVU = ((3 << 3) + 7),
410 ADD = ((4 << 3) + 0),
411 ADDU = ((4 << 3) + 1),
412 SUB = ((4 << 3) + 2),
413 SUBU = ((4 << 3) + 3),
414 AND = ((4 << 3) + 4),
416 XOR = ((4 << 3) + 6),
417 NOR = ((4 << 3) + 7),
419 SLT = ((5 << 3) + 2),
420 SLTU = ((5 << 3) + 3),
421 DADD = ((5 << 3) + 4),
422 DADDU = ((5 << 3) + 5),
423 DSUB = ((5 << 3) + 6),
424 DSUBU = ((5 << 3) + 7),
426 TGE = ((6 << 3) + 0),
427 TGEU = ((6 << 3) + 1),
428 TLT = ((6 << 3) + 2),
429 TLTU = ((6 << 3) + 3),
430 TEQ = ((6 << 3) + 4),
431 SELEQZ_S = ((6 << 3) + 5),
432 TNE = ((6 << 3) + 6),
433 SELNEZ_S = ((6 << 3) + 7),
435 DSLL = ((7 << 3) + 0),
436 DSRL = ((7 << 3) + 2),
437 DSRA = ((7 << 3) + 3),
438 DSLL32 = ((7 << 3) + 4),
439 DSRL32 = ((7 << 3) + 6),
440 DSRA32 = ((7 << 3) + 7),
442 // Multiply integers in r6.
443 MUL_MUH = ((3 << 3) + 0), // MUL, MUH.
444 MUL_MUH_U = ((3 << 3) + 1), // MUL_U, MUH_U.
445 D_MUL_MUH = ((7 << 2) + 0), // DMUL, DMUH.
446 D_MUL_MUH_U = ((7 << 2) + 1), // DMUL_U, DMUH_U.
447 RINT = ((3 << 3) + 2),
449 MUL_OP = ((0 << 3) + 2),
450 MUH_OP = ((0 << 3) + 3),
451 DIV_OP = ((0 << 3) + 2),
452 MOD_OP = ((0 << 3) + 3),
454 DIV_MOD = ((3 << 3) + 2),
455 DIV_MOD_U = ((3 << 3) + 3),
456 D_DIV_MOD = ((3 << 3) + 6),
457 D_DIV_MOD_U = ((3 << 3) + 7),
459 // drotr in special4?
461 // SPECIAL2 Encoding of Function Field.
462 MUL = ((0 << 3) + 2),
463 CLZ = ((4 << 3) + 0),
464 CLO = ((4 << 3) + 1),
466 // SPECIAL3 Encoding of Function Field.
467 EXT = ((0 << 3) + 0),
468 DEXTM = ((0 << 3) + 1),
469 DEXTU = ((0 << 3) + 2),
470 DEXT = ((0 << 3) + 3),
471 INS = ((0 << 3) + 4),
472 DINSM = ((0 << 3) + 5),
473 DINSU = ((0 << 3) + 6),
474 DINS = ((0 << 3) + 7),
476 BSHFL = ((4 << 3) + 0),
477 DBSHFL = ((4 << 3) + 4),
479 // SPECIAL3 Encoding of sa Field.
480 BITSWAP = ((0 << 3) + 0),
481 ALIGN = ((0 << 3) + 2),
482 WSBH = ((0 << 3) + 2),
483 SEB = ((2 << 3) + 0),
484 SEH = ((3 << 3) + 0),
486 DBITSWAP = ((0 << 3) + 0),
487 DALIGN = ((0 << 3) + 1),
488 DBITSWAP_SA = ((0 << 3) + 0) << kSaShift,
489 DSBH = ((0 << 3) + 2),
490 DSHD = ((0 << 3) + 5),
492 // REGIMM encoding of rt Field.
493 BLTZ = ((0 << 3) + 0) << 16,
494 BGEZ = ((0 << 3) + 1) << 16,
495 BLTZAL = ((2 << 3) + 0) << 16,
496 BGEZAL = ((2 << 3) + 1) << 16,
497 BGEZALL = ((2 << 3) + 3) << 16,
498 DAHI = ((0 << 3) + 6) << 16,
499 DATI = ((3 << 3) + 6) << 16,
501 // COP1 Encoding of rs Field.
502 MFC1 = ((0 << 3) + 0) << 21,
503 DMFC1 = ((0 << 3) + 1) << 21,
504 CFC1 = ((0 << 3) + 2) << 21,
505 MFHC1 = ((0 << 3) + 3) << 21,
506 MTC1 = ((0 << 3) + 4) << 21,
507 DMTC1 = ((0 << 3) + 5) << 21,
508 CTC1 = ((0 << 3) + 6) << 21,
509 MTHC1 = ((0 << 3) + 7) << 21,
510 BC1 = ((1 << 3) + 0) << 21,
511 S = ((2 << 3) + 0) << 21,
512 D = ((2 << 3) + 1) << 21,
513 W = ((2 << 3) + 4) << 21,
514 L = ((2 << 3) + 5) << 21,
515 PS = ((2 << 3) + 6) << 21,
516 // COP1 Encoding of Function Field When rs=S.
518 ADD_S = ((0 << 3) + 0),
519 SUB_S = ((0 << 3) + 1),
520 MUL_S = ((0 << 3) + 2),
521 DIV_S = ((0 << 3) + 3),
522 ABS_S = ((0 << 3) + 5),
523 SQRT_S = ((0 << 3) + 4),
524 MOV_S = ((0 << 3) + 6),
525 NEG_S = ((0 << 3) + 7),
526 ROUND_L_S = ((1 << 3) + 0),
527 TRUNC_L_S = ((1 << 3) + 1),
528 CEIL_L_S = ((1 << 3) + 2),
529 FLOOR_L_S = ((1 << 3) + 3),
530 ROUND_W_S = ((1 << 3) + 4),
531 TRUNC_W_S = ((1 << 3) + 5),
532 CEIL_W_S = ((1 << 3) + 6),
533 FLOOR_W_S = ((1 << 3) + 7),
534 RECIP_S = ((2 << 3) + 5),
535 RSQRT_S = ((2 << 3) + 6),
536 CLASS_S = ((3 << 3) + 3),
537 CVT_D_S = ((4 << 3) + 1),
538 CVT_W_S = ((4 << 3) + 4),
539 CVT_L_S = ((4 << 3) + 5),
540 CVT_PS_S = ((4 << 3) + 6),
541 // COP1 Encoding of Function Field When rs=D.
542 ADD_D = ((0 << 3) + 0),
543 SUB_D = ((0 << 3) + 1),
544 MUL_D = ((0 << 3) + 2),
545 DIV_D = ((0 << 3) + 3),
546 SQRT_D = ((0 << 3) + 4),
547 ABS_D = ((0 << 3) + 5),
548 MOV_D = ((0 << 3) + 6),
549 NEG_D = ((0 << 3) + 7),
550 ROUND_L_D = ((1 << 3) + 0),
551 TRUNC_L_D = ((1 << 3) + 1),
552 CEIL_L_D = ((1 << 3) + 2),
553 FLOOR_L_D = ((1 << 3) + 3),
554 ROUND_W_D = ((1 << 3) + 4),
555 TRUNC_W_D = ((1 << 3) + 5),
556 CEIL_W_D = ((1 << 3) + 6),
557 FLOOR_W_D = ((1 << 3) + 7),
558 RECIP_D = ((2 << 3) + 5),
559 RSQRT_D = ((2 << 3) + 6),
560 CLASS_D = ((3 << 3) + 3),
561 MIN = ((3 << 3) + 4),
562 MINA = ((3 << 3) + 5),
563 MAX = ((3 << 3) + 6),
564 MAXA = ((3 << 3) + 7),
565 CVT_S_D = ((4 << 3) + 0),
566 CVT_W_D = ((4 << 3) + 4),
567 CVT_L_D = ((4 << 3) + 5),
568 C_F_D = ((6 << 3) + 0),
569 C_UN_D = ((6 << 3) + 1),
570 C_EQ_D = ((6 << 3) + 2),
571 C_UEQ_D = ((6 << 3) + 3),
572 C_OLT_D = ((6 << 3) + 4),
573 C_ULT_D = ((6 << 3) + 5),
574 C_OLE_D = ((6 << 3) + 6),
575 C_ULE_D = ((6 << 3) + 7),
577 // COP1 Encoding of Function Field When rs=W or L.
578 CVT_S_W = ((4 << 3) + 0),
579 CVT_D_W = ((4 << 3) + 1),
580 CVT_S_L = ((4 << 3) + 0),
581 CVT_D_L = ((4 << 3) + 1),
582 BC1EQZ = ((2 << 2) + 1) << 21,
583 BC1NEZ = ((3 << 2) + 1) << 21,
584 // COP1 CMP positive predicates Bit 5..4 = 00.
585 CMP_AF = ((0 << 3) + 0),
586 CMP_UN = ((0 << 3) + 1),
587 CMP_EQ = ((0 << 3) + 2),
588 CMP_UEQ = ((0 << 3) + 3),
589 CMP_LT = ((0 << 3) + 4),
590 CMP_ULT = ((0 << 3) + 5),
591 CMP_LE = ((0 << 3) + 6),
592 CMP_ULE = ((0 << 3) + 7),
593 CMP_SAF = ((1 << 3) + 0),
594 CMP_SUN = ((1 << 3) + 1),
595 CMP_SEQ = ((1 << 3) + 2),
596 CMP_SUEQ = ((1 << 3) + 3),
597 CMP_SSLT = ((1 << 3) + 4),
598 CMP_SSULT = ((1 << 3) + 5),
599 CMP_SLE = ((1 << 3) + 6),
600 CMP_SULE = ((1 << 3) + 7),
601 // COP1 CMP negative predicates Bit 5..4 = 01.
602 CMP_AT = ((2 << 3) + 0), // Reserved, not implemented.
603 CMP_OR = ((2 << 3) + 1),
604 CMP_UNE = ((2 << 3) + 2),
605 CMP_NE = ((2 << 3) + 3),
606 CMP_UGE = ((2 << 3) + 4), // Reserved, not implemented.
607 CMP_OGE = ((2 << 3) + 5), // Reserved, not implemented.
608 CMP_UGT = ((2 << 3) + 6), // Reserved, not implemented.
609 CMP_OGT = ((2 << 3) + 7), // Reserved, not implemented.
610 CMP_SAT = ((3 << 3) + 0), // Reserved, not implemented.
611 CMP_SOR = ((3 << 3) + 1),
612 CMP_SUNE = ((3 << 3) + 2),
613 CMP_SNE = ((3 << 3) + 3),
614 CMP_SUGE = ((3 << 3) + 4), // Reserved, not implemented.
615 CMP_SOGE = ((3 << 3) + 5), // Reserved, not implemented.
616 CMP_SUGT = ((3 << 3) + 6), // Reserved, not implemented.
617 CMP_SOGT = ((3 << 3) + 7), // Reserved, not implemented.
619 SEL = ((2 << 3) + 0),
620 MOVF = ((2 << 3) + 1), // Function field for MOVT.fmt and MOVF.fmt
621 MOVZ_C = ((2 << 3) + 2), // COP1 on FPR registers.
622 MOVN_C = ((2 << 3) + 3), // COP1 on FPR registers.
623 SELEQZ_C = ((2 << 3) + 4), // COP1 on FPR registers.
624 SELNEZ_C = ((2 << 3) + 7), // COP1 on FPR registers.
626 // COP1 Encoding of Function Field When rs=PS.
627 // COP1X Encoding of Function Field.
628 MADD_D = ((4 << 3) + 1),
630 // PCREL Encoding of rt Field.
631 ADDIUPC = ((0 << 2) + 0),
632 LWPC = ((0 << 2) + 1),
633 LWUPC = ((0 << 2) + 2),
634 LDPC = ((0 << 3) + 6),
635 // reserved ((1 << 3) + 6),
636 AUIPC = ((3 << 3) + 6),
637 ALUIPC = ((3 << 3) + 7),
639 // POP66 Encoding of rs Field.
640 JIC = ((0 << 5) + 0),
642 // POP76 Encoding of rs Field.
643 JIALC = ((0 << 5) + 0),
649 // ----- Emulated conditions.
650 // On MIPS we use this enum to abstract from conditional branch instructions.
651 // The 'U' prefix is used to specify unsigned comparisons.
652 // Opposite conditions must be paired as odd/even numbers
653 // because 'NegateCondition' function flips LSB to negate condition.
655 // Any value < 0 is considered no_condition.
664 not_equal = 7, // Unordered or Not Equal.
673 ueq = 16, // Unordered or Equal.
674 ogl = 17, // Ordered and Not Equal.
679 not_carry = Ugreater_equal,
682 not_zero = not_equal,
699 uge = Ugreater_equal,
702 cc_default = kNoCondition
706 // Returns the equivalent of !cc.
707 // Negation of the default kNoCondition (-1) results in a non-default
708 // no_condition value (-2). As long as tests for no_condition check
709 // for condition < 0, this will work as expected.
710 inline Condition NegateCondition(Condition cc) {
711 DCHECK(cc != cc_always);
712 return static_cast<Condition>(cc ^ 1);
716 inline Condition NegateFpuCondition(Condition cc) {
717 DCHECK(cc != cc_always);
749 // Commute a condition such that {a cond b == b cond' a}.
750 inline Condition CommuteCondition(Condition cc) {
759 return Ugreater_equal;
767 return greater_equal;
774 // ----- Coprocessor conditions.
776 kNoFPUCondition = -1,
779 UN = 0x01, // Unordered.
781 UEQ = 0x03, // Unordered or Equal.
782 OLT = 0x04, // Ordered or Less Than, on Mips release < 6.
783 LT = 0x04, // Ordered or Less Than, on Mips release >= 6.
784 ULT = 0x05, // Unordered or Less Than.
785 OLE = 0x06, // Ordered or Less Than or Equal, on Mips release < 6.
786 LE = 0x06, // Ordered or Less Than or Equal, on Mips release >= 6.
787 ULE = 0x07, // Unordered or Less Than or Equal.
789 // Following constants are available on Mips release >= 6 only.
790 ORD = 0x11, // Ordered, on Mips release >= 6.
791 UNE = 0x12, // Not equal, on Mips release >= 6.
792 NE = 0x13, // Ordered Greater Than or Less Than. on Mips >= 6 only.
796 // FPU rounding modes.
797 enum FPURoundingMode {
798 RN = 0 << 0, // Round to Nearest.
799 RZ = 1 << 0, // Round towards zero.
800 RP = 2 << 0, // Round towards Plus Infinity.
801 RM = 3 << 0, // Round towards Minus Infinity.
804 kRoundToNearest = RN,
806 kRoundToPlusInf = RP,
807 kRoundToMinusInf = RM
810 const uint32_t kFPURoundingModeMask = 3 << 0;
812 enum CheckForInexactConversion {
813 kCheckForInexactConversion,
814 kDontCheckForInexactConversion
818 // -----------------------------------------------------------------------------
821 // Branch hints are not used on the MIPS. They are defined so that they can
822 // appear in shared function signatures, but will be ignored in MIPS
829 inline Hint NegateHint(Hint hint) {
834 // -----------------------------------------------------------------------------
835 // Specific instructions, constants, and masks.
836 // These constants are declared in assembler-mips.cc, as they use named
837 // registers and other constants.
839 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
840 // operations as post-increment of sp.
841 extern const Instr kPopInstruction;
842 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
843 extern const Instr kPushInstruction;
844 // sw(r, MemOperand(sp, 0))
845 extern const Instr kPushRegPattern;
846 // lw(r, MemOperand(sp, 0))
847 extern const Instr kPopRegPattern;
848 extern const Instr kLwRegFpOffsetPattern;
849 extern const Instr kSwRegFpOffsetPattern;
850 extern const Instr kLwRegFpNegOffsetPattern;
851 extern const Instr kSwRegFpNegOffsetPattern;
852 // A mask for the Rt register for push, pop, lw, sw instructions.
853 extern const Instr kRtMask;
854 extern const Instr kLwSwInstrTypeMask;
855 extern const Instr kLwSwInstrArgumentMask;
856 extern const Instr kLwSwOffsetMask;
858 // Break 0xfffff, reserved for redirected real time call.
859 const Instr rtCallRedirInstr = SPECIAL | BREAK | call_rt_redirected << 6;
860 // A nop instruction. (Encoding of sll 0 0 0).
861 const Instr nopInstr = 0;
868 // On MIPS PC cannot actually be directly accessed. We behave as if PC was
869 // always the value of the current instruction being executed.
873 // Get the raw instruction bits.
874 inline Instr InstructionBits() const {
875 return *reinterpret_cast<const Instr*>(this);
878 // Set the raw instruction bits to value.
879 inline void SetInstructionBits(Instr value) {
880 *reinterpret_cast<Instr*>(this) = value;
883 // Read one particular bit out of the instruction bits.
884 inline int Bit(int nr) const {
885 return (InstructionBits() >> nr) & 1;
888 // Read a bit field out of the instruction bits.
889 inline int Bits(int hi, int lo) const {
890 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
901 enum TypeChecks { NORMAL, EXTRA };
904 #define OpcodeToBitNumber(opcode) \
905 (1ULL << (static_cast<uint32_t>(opcode) >> kOpcodeShift))
907 static const uint64_t kOpcodeImmediateTypeMask =
908 OpcodeToBitNumber(REGIMM) | OpcodeToBitNumber(BEQ) |
909 OpcodeToBitNumber(BNE) | OpcodeToBitNumber(BLEZ) |
910 OpcodeToBitNumber(BGTZ) | OpcodeToBitNumber(ADDI) |
911 OpcodeToBitNumber(DADDI) | OpcodeToBitNumber(ADDIU) |
912 OpcodeToBitNumber(DADDIU) | OpcodeToBitNumber(SLTI) |
913 OpcodeToBitNumber(SLTIU) | OpcodeToBitNumber(ANDI) |
914 OpcodeToBitNumber(ORI) | OpcodeToBitNumber(XORI) |
915 OpcodeToBitNumber(LUI) | OpcodeToBitNumber(BEQL) |
916 OpcodeToBitNumber(BNEL) | OpcodeToBitNumber(BLEZL) |
917 OpcodeToBitNumber(BGTZL) | OpcodeToBitNumber(POP66) |
918 OpcodeToBitNumber(POP76) | OpcodeToBitNumber(LB) | OpcodeToBitNumber(LH) |
919 OpcodeToBitNumber(LWL) | OpcodeToBitNumber(LW) | OpcodeToBitNumber(LWU) |
920 OpcodeToBitNumber(LD) | OpcodeToBitNumber(LBU) | OpcodeToBitNumber(LHU) |
921 OpcodeToBitNumber(LWR) | OpcodeToBitNumber(SB) | OpcodeToBitNumber(SH) |
922 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SD) |
923 OpcodeToBitNumber(SWR) | OpcodeToBitNumber(LWC1) |
924 OpcodeToBitNumber(LDC1) | OpcodeToBitNumber(SWC1) |
925 OpcodeToBitNumber(SDC1) | OpcodeToBitNumber(PCREL) |
926 OpcodeToBitNumber(BC) | OpcodeToBitNumber(BALC);
928 #define FunctionFieldToBitNumber(function) (1ULL << function)
930 static const uint64_t kFunctionFieldRegisterTypeMask =
931 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) |
932 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) |
933 FunctionFieldToBitNumber(DSLL) | FunctionFieldToBitNumber(DSLL32) |
934 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(DSRL) |
935 FunctionFieldToBitNumber(DSRL32) | FunctionFieldToBitNumber(SRA) |
936 FunctionFieldToBitNumber(DSRA) | FunctionFieldToBitNumber(DSRA32) |
937 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(DSLLV) |
938 FunctionFieldToBitNumber(SRLV) | FunctionFieldToBitNumber(DSRLV) |
939 FunctionFieldToBitNumber(SRAV) | FunctionFieldToBitNumber(DSRAV) |
940 FunctionFieldToBitNumber(MFHI) | FunctionFieldToBitNumber(MFLO) |
941 FunctionFieldToBitNumber(MULT) | FunctionFieldToBitNumber(DMULT) |
942 FunctionFieldToBitNumber(MULTU) | FunctionFieldToBitNumber(DMULTU) |
943 FunctionFieldToBitNumber(DIV) | FunctionFieldToBitNumber(DDIV) |
944 FunctionFieldToBitNumber(DIVU) | FunctionFieldToBitNumber(DDIVU) |
945 FunctionFieldToBitNumber(ADD) | FunctionFieldToBitNumber(DADD) |
946 FunctionFieldToBitNumber(ADDU) | FunctionFieldToBitNumber(DADDU) |
947 FunctionFieldToBitNumber(SUB) | FunctionFieldToBitNumber(DSUB) |
948 FunctionFieldToBitNumber(SUBU) | FunctionFieldToBitNumber(DSUBU) |
949 FunctionFieldToBitNumber(AND) | FunctionFieldToBitNumber(OR) |
950 FunctionFieldToBitNumber(XOR) | FunctionFieldToBitNumber(NOR) |
951 FunctionFieldToBitNumber(SLT) | FunctionFieldToBitNumber(SLTU) |
952 FunctionFieldToBitNumber(TGE) | FunctionFieldToBitNumber(TGEU) |
953 FunctionFieldToBitNumber(TLT) | FunctionFieldToBitNumber(TLTU) |
954 FunctionFieldToBitNumber(TEQ) | FunctionFieldToBitNumber(TNE) |
955 FunctionFieldToBitNumber(MOVZ) | FunctionFieldToBitNumber(MOVN) |
956 FunctionFieldToBitNumber(MOVCI) | FunctionFieldToBitNumber(SELEQZ_S) |
957 FunctionFieldToBitNumber(SELNEZ_S);
960 // Get the encoding type of the instruction.
961 inline Type InstructionType(TypeChecks checks = NORMAL) const;
964 // Accessors for the different named fields used in the MIPS encoding.
965 inline Opcode OpcodeValue() const {
966 return static_cast<Opcode>(
967 Bits(kOpcodeShift + kOpcodeBits - 1, kOpcodeShift));
970 inline int RsValue() const {
971 DCHECK(InstructionType() == kRegisterType ||
972 InstructionType() == kImmediateType);
973 return Bits(kRsShift + kRsBits - 1, kRsShift);
976 inline int RtValue() const {
977 DCHECK(InstructionType() == kRegisterType ||
978 InstructionType() == kImmediateType);
979 return Bits(kRtShift + kRtBits - 1, kRtShift);
982 inline int RdValue() const {
983 DCHECK(InstructionType() == kRegisterType);
984 return Bits(kRdShift + kRdBits - 1, kRdShift);
987 inline int SaValue() const {
988 DCHECK(InstructionType() == kRegisterType);
989 return Bits(kSaShift + kSaBits - 1, kSaShift);
992 inline int FunctionValue() const {
993 DCHECK(InstructionType() == kRegisterType ||
994 InstructionType() == kImmediateType);
995 return Bits(kFunctionShift + kFunctionBits - 1, kFunctionShift);
998 inline int FdValue() const {
999 return Bits(kFdShift + kFdBits - 1, kFdShift);
1002 inline int FsValue() const {
1003 return Bits(kFsShift + kFsBits - 1, kFsShift);
1006 inline int FtValue() const {
1007 return Bits(kFtShift + kFtBits - 1, kFtShift);
1010 inline int FrValue() const {
1011 return Bits(kFrShift + kFrBits -1, kFrShift);
1014 inline int Bp2Value() const {
1015 DCHECK(InstructionType() == kRegisterType);
1016 return Bits(kBp2Shift + kBp2Bits - 1, kBp2Shift);
1019 inline int Bp3Value() const {
1020 DCHECK(InstructionType() == kRegisterType);
1021 return Bits(kBp3Shift + kBp3Bits - 1, kBp3Shift);
1024 // Float Compare condition code instruction bits.
1025 inline int FCccValue() const {
1026 return Bits(kFCccShift + kFCccBits - 1, kFCccShift);
1029 // Float Branch condition code instruction bits.
1030 inline int FBccValue() const {
1031 return Bits(kFBccShift + kFBccBits - 1, kFBccShift);
1034 // Float Branch true/false instruction bit.
1035 inline int FBtrueValue() const {
1036 return Bits(kFBtrueShift + kFBtrueBits - 1, kFBtrueShift);
1039 // Return the fields at their original place in the instruction encoding.
1040 inline Opcode OpcodeFieldRaw() const {
1041 return static_cast<Opcode>(InstructionBits() & kOpcodeMask);
1044 inline int RsFieldRaw() const {
1045 DCHECK(InstructionType() == kRegisterType ||
1046 InstructionType() == kImmediateType);
1047 return InstructionBits() & kRsFieldMask;
1050 // Same as above function, but safe to call within InstructionType().
1051 inline int RsFieldRawNoAssert() const {
1052 return InstructionBits() & kRsFieldMask;
1055 inline int RtFieldRaw() const {
1056 DCHECK(InstructionType() == kRegisterType ||
1057 InstructionType() == kImmediateType);
1058 return InstructionBits() & kRtFieldMask;
1061 inline int RdFieldRaw() const {
1062 DCHECK(InstructionType() == kRegisterType);
1063 return InstructionBits() & kRdFieldMask;
1066 inline int SaFieldRaw() const {
1067 return InstructionBits() & kSaFieldMask;
1070 inline int FunctionFieldRaw() const {
1071 return InstructionBits() & kFunctionFieldMask;
1074 // Get the secondary field according to the opcode.
1075 inline int SecondaryValue() const {
1076 Opcode op = OpcodeFieldRaw();
1080 return FunctionValue();
1090 inline int32_t Imm16Value() const {
1091 DCHECK(InstructionType() == kImmediateType);
1092 return Bits(kImm16Shift + kImm16Bits - 1, kImm16Shift);
1095 inline int32_t Imm18Value() const {
1096 DCHECK(InstructionType() == kImmediateType);
1097 return Bits(kImm18Shift + kImm18Bits - 1, kImm18Shift);
1100 inline int32_t Imm19Value() const {
1101 DCHECK(InstructionType() == kImmediateType);
1102 return Bits(kImm19Shift + kImm19Bits - 1, kImm19Shift);
1105 inline int32_t Imm21Value() const {
1106 DCHECK(InstructionType() == kImmediateType);
1107 return Bits(kImm21Shift + kImm21Bits - 1, kImm21Shift);
1110 inline int32_t Imm26Value() const {
1111 DCHECK((InstructionType() == kJumpType) ||
1112 (InstructionType() == kImmediateType));
1113 return Bits(kImm26Shift + kImm26Bits - 1, kImm26Shift);
1116 // Say if the instruction should not be used in a branch delay slot.
1117 bool IsForbiddenInBranchDelay() const;
1118 // Say if the instruction 'links'. e.g. jal, bal.
1119 bool IsLinkingInstruction() const;
1120 // Say if the instruction is a break or a trap.
1121 bool IsTrap() const;
1123 // Instructions are read of out a code stream. The only way to get a
1124 // reference to an instruction is to convert a pointer. There is no way
1125 // to allocate or create instances of class Instruction.
1126 // Use the At(pc) function to create references to Instruction.
1127 static Instruction* At(byte* pc) {
1128 return reinterpret_cast<Instruction*>(pc);
1132 // We need to prevent the creation of instances of class Instruction.
1133 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
1137 // -----------------------------------------------------------------------------
1138 // MIPS assembly various constants.
1140 // C/C++ argument slots size.
1141 const int kCArgSlotCount = (kMipsAbi == kN64) ? 0 : 4;
1143 // TODO(plind): below should be based on kPointerSize
1144 // TODO(plind): find all usages and remove the needless instructions for n64.
1145 const int kCArgsSlotsSize = kCArgSlotCount * Instruction::kInstrSize * 2;
1147 const int kInvalidStackOffset = -1;
1148 const int kBranchReturnOffset = 2 * Instruction::kInstrSize;
1151 Instruction::Type Instruction::InstructionType(TypeChecks checks) const {
1152 if (checks == EXTRA) {
1153 if (OpcodeToBitNumber(OpcodeFieldRaw()) & kOpcodeImmediateTypeMask) {
1154 return kImmediateType;
1157 switch (OpcodeFieldRaw()) {
1159 if (checks == EXTRA) {
1160 if (FunctionFieldToBitNumber(FunctionFieldRaw()) &
1161 kFunctionFieldRegisterTypeMask) {
1162 return kRegisterType;
1164 return kUnsupported;
1167 return kRegisterType;
1171 switch (FunctionFieldRaw()) {
1174 return kRegisterType;
1176 return kUnsupported;
1180 switch (FunctionFieldRaw()) {
1184 return kRegisterType;
1186 int sa = SaFieldRaw() >> kSaShift;
1189 return kRegisterType;
1193 return kUnsupported;
1198 return kRegisterType;
1200 return kUnsupported;
1204 int sa = SaFieldRaw() >> kSaShift;
1207 return kRegisterType;
1210 return kUnsupported;
1212 sa = SaFieldRaw() >> kSaShift;
1216 return kRegisterType;
1218 return kUnsupported;
1222 return kUnsupported;
1225 case COP1: // Coprocessor instructions.
1226 switch (RsFieldRawNoAssert()) {
1227 case BC1: // Branch on coprocessor condition.
1230 return kImmediateType;
1232 return kRegisterType;
1236 return kRegisterType;
1238 // 26 bits immediate type instructions. e.g.: j imm26.
1244 if (checks == NORMAL) {
1245 return kImmediateType;
1247 return kUnsupported;
1250 return kUnsupported;
1253 #undef OpcodeToBitNumber
1254 #undef FunctionFieldToBitNumber
1255 } // namespace internal
1258 #endif // #ifndef V8_MIPS_CONSTANTS_H_