1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
8 #include "src/assembler.h"
9 #include "src/globals.h"
10 #include "src/mips/assembler-mips.h"
15 // Give alias names to registers for calling conventions.
16 const Register kReturnRegister0 = {kRegister_v0_Code};
17 const Register kReturnRegister1 = {kRegister_v1_Code};
18 const Register kJSFunctionRegister = {kRegister_a1_Code};
19 const Register kContextRegister = {Register::kCpRegister};
20 const Register kInterpreterAccumulatorRegister = {kRegister_v0_Code};
21 const Register kInterpreterRegisterFileRegister = {kRegister_t3_Code};
22 const Register kInterpreterBytecodeOffsetRegister = {kRegister_t4_Code};
23 const Register kInterpreterBytecodeArrayRegister = {kRegister_t5_Code};
24 const Register kInterpreterDispatchTableRegister = {kRegister_t6_Code};
25 const Register kRuntimeCallFunctionRegister = {kRegister_a1_Code};
26 const Register kRuntimeCallArgCountRegister = {kRegister_a0_Code};
28 // Forward declaration.
31 // Reserved Register Usage Summary.
33 // Registers t8, t9, and at are reserved for use by the MacroAssembler.
35 // The programmer should know that the MacroAssembler may clobber these three,
36 // but won't touch other registers except in special cases.
38 // Per the MIPS ABI, register t9 must be used for indirect function call
39 // via 'jalr t9' or 'jr t9' instructions. This is relied upon by gcc when
40 // trying to update gp register for position-independent-code. Whenever
41 // MIPS generated code calls C code, it must be via t9 register.
44 // Flags used for LeaveExitFrame function.
45 enum LeaveExitFrameMode {
47 NO_EMIT_RETURN = false
50 // Flags used for AllocateHeapNumber
58 // Flags used for the ObjectToDoubleFPURegister function.
59 enum ObjectToDoubleFlags {
61 NO_OBJECT_TO_DOUBLE_FLAGS = 0,
62 // Object is known to be a non smi.
63 OBJECT_NOT_SMI = 1 << 0,
64 // Don't load NaNs or infinities, branch to the non number case instead.
65 AVOID_NANS_AND_INFINITIES = 1 << 1
68 // Allow programmer to use Branch Delay Slot of Branches, Jumps, Calls.
69 enum BranchDelaySlot {
74 // Flags used for the li macro-assembler function.
76 // If the constant value can be represented in just 16 bits, then
77 // optimize the li to use a single instruction, rather than lui/ori pair.
79 // Always use 2 instructions (lui/ori pair), even if the constant could
80 // be loaded with just one, so that this value is patchable later.
85 enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET };
86 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK };
87 enum PointersToHereCheck {
88 kPointersToHereMaybeInteresting,
89 kPointersToHereAreAlwaysInteresting
91 enum RAStatus { kRAHasNotBeenSaved, kRAHasBeenSaved };
93 Register GetRegisterThatIsNotOneOf(Register reg1,
94 Register reg2 = no_reg,
95 Register reg3 = no_reg,
96 Register reg4 = no_reg,
97 Register reg5 = no_reg,
98 Register reg6 = no_reg);
100 bool AreAliased(Register reg1,
102 Register reg3 = no_reg,
103 Register reg4 = no_reg,
104 Register reg5 = no_reg,
105 Register reg6 = no_reg,
106 Register reg7 = no_reg,
107 Register reg8 = no_reg);
110 // -----------------------------------------------------------------------------
111 // Static helper functions.
113 inline MemOperand ContextOperand(Register context, int index) {
114 return MemOperand(context, Context::SlotOffset(index));
118 inline MemOperand GlobalObjectOperand() {
119 return ContextOperand(cp, Context::GLOBAL_OBJECT_INDEX);
123 // Generate a MemOperand for loading a field from an object.
124 inline MemOperand FieldMemOperand(Register object, int offset) {
125 return MemOperand(object, offset - kHeapObjectTag);
129 // Generate a MemOperand for storing arguments 5..N on the stack
130 // when calling CallCFunction().
131 inline MemOperand CFunctionArgumentOperand(int index) {
132 DCHECK(index > kCArgSlotCount);
133 // Argument 5 takes the slot just past the four Arg-slots.
134 int offset = (index - 5) * kPointerSize + kCArgsSlotsSize;
135 return MemOperand(sp, offset);
139 // MacroAssembler implements a collection of frequently used macros.
140 class MacroAssembler: public Assembler {
142 // The isolate parameter can be NULL if the macro assembler should
143 // not use isolate-dependent functionality. In this case, it's the
144 // responsibility of the caller to never invoke such function on the
146 MacroAssembler(Isolate* isolate, void* buffer, int size);
149 #define COND_TYPED_ARGS Condition cond, Register r1, const Operand& r2
150 #define COND_ARGS cond, r1, r2
152 // Cases when relocation is not needed.
153 #define DECLARE_NORELOC_PROTOTYPE(Name, target_type) \
154 void Name(target_type target, BranchDelaySlot bd = PROTECT); \
155 inline void Name(BranchDelaySlot bd, target_type target) { \
158 void Name(target_type target, \
160 BranchDelaySlot bd = PROTECT); \
161 inline void Name(BranchDelaySlot bd, \
162 target_type target, \
164 Name(target, COND_ARGS, bd); \
167 #define DECLARE_BRANCH_PROTOTYPES(Name) \
168 DECLARE_NORELOC_PROTOTYPE(Name, Label*) \
169 DECLARE_NORELOC_PROTOTYPE(Name, int16_t)
171 DECLARE_BRANCH_PROTOTYPES(Branch)
172 DECLARE_BRANCH_PROTOTYPES(BranchAndLink)
173 DECLARE_BRANCH_PROTOTYPES(BranchShort)
175 #undef DECLARE_BRANCH_PROTOTYPES
176 #undef COND_TYPED_ARGS
180 // Jump, Call, and Ret pseudo instructions implementing inter-working.
181 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
182 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
184 void Jump(Register target, COND_ARGS);
185 void Jump(intptr_t target, RelocInfo::Mode rmode, COND_ARGS);
186 void Jump(Address target, RelocInfo::Mode rmode, COND_ARGS);
187 void Jump(Handle<Code> code, RelocInfo::Mode rmode, COND_ARGS);
188 static int CallSize(Register target, COND_ARGS);
189 void Call(Register target, COND_ARGS);
190 static int CallSize(Address target, RelocInfo::Mode rmode, COND_ARGS);
191 void Call(Address target, RelocInfo::Mode rmode, COND_ARGS);
192 int CallSize(Handle<Code> code,
193 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
194 TypeFeedbackId ast_id = TypeFeedbackId::None(),
196 void Call(Handle<Code> code,
197 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
198 TypeFeedbackId ast_id = TypeFeedbackId::None(),
201 inline void Ret(BranchDelaySlot bd, Condition cond = al,
202 Register rs = zero_reg, const Operand& rt = Operand(zero_reg)) {
203 Ret(cond, rs, rt, bd);
206 void Branch(Label* L,
209 Heap::RootListIndex index,
210 BranchDelaySlot bdslot = PROTECT);
214 // Emit code to discard a non-negative number of pointer-sized elements
215 // from the stack, clobbering only the sp register.
217 Condition cond = cc_always,
218 Register reg = no_reg,
219 const Operand& op = Operand(no_reg));
221 // Trivial case of DropAndRet that utilizes the delay slot and only emits
223 void DropAndRet(int drop);
225 void DropAndRet(int drop,
230 // Swap two registers. If the scratch register is omitted then a slightly
231 // less efficient form using xor instead of mov is emitted.
232 void Swap(Register reg1, Register reg2, Register scratch = no_reg);
234 void Call(Label* target);
236 inline void Move(Register dst, Register src) {
242 inline void Move(FPURegister dst, FPURegister src) {
248 inline void Move(Register dst_low, Register dst_high, FPURegister src) {
250 Mfhc1(dst_high, src);
253 inline void FmoveHigh(Register dst_high, FPURegister src) {
254 Mfhc1(dst_high, src);
257 inline void FmoveHigh(FPURegister dst, Register src_high) {
258 Mthc1(src_high, dst);
261 inline void FmoveLow(Register dst_low, FPURegister src) {
265 void FmoveLow(FPURegister dst, Register src_low);
267 inline void Move(FPURegister dst, Register src_low, Register src_high) {
269 Mthc1(src_high, dst);
272 void Move(FPURegister dst, float imm);
273 void Move(FPURegister dst, double imm);
276 void Movz(Register rd, Register rs, Register rt);
277 void Movn(Register rd, Register rs, Register rt);
278 void Movt(Register rd, Register rs, uint16_t cc = 0);
279 void Movf(Register rd, Register rs, uint16_t cc = 0);
281 void Clz(Register rd, Register rs);
283 // Jump unconditionally to given label.
284 // We NEED a nop in the branch delay slot, as it used by v8, for example in
285 // CodeGenerator::ProcessDeferred().
286 // Currently the branch delay slot is filled by the MacroAssembler.
287 // Use rather b(Label) for code generation.
292 void Load(Register dst, const MemOperand& src, Representation r);
293 void Store(Register src, const MemOperand& dst, Representation r);
295 void PushRoot(Heap::RootListIndex index) {
300 // Compare the object in a register to a value and jump if they are equal.
301 void JumpIfRoot(Register with, Heap::RootListIndex index, Label* if_equal) {
303 Branch(if_equal, eq, with, Operand(at));
306 // Compare the object in a register to a value and jump if they are not equal.
307 void JumpIfNotRoot(Register with, Heap::RootListIndex index,
308 Label* if_not_equal) {
310 Branch(if_not_equal, ne, with, Operand(at));
313 // Load an object from the root table.
314 void LoadRoot(Register destination,
315 Heap::RootListIndex index);
316 void LoadRoot(Register destination,
317 Heap::RootListIndex index,
318 Condition cond, Register src1, const Operand& src2);
320 // Store an object to the root table.
321 void StoreRoot(Register source,
322 Heap::RootListIndex index);
323 void StoreRoot(Register source,
324 Heap::RootListIndex index,
325 Condition cond, Register src1, const Operand& src2);
327 // ---------------------------------------------------------------------------
330 void IncrementalMarkingRecordWriteHelper(Register object,
334 enum RememberedSetFinalAction {
340 // Record in the remembered set the fact that we have a pointer to new space
341 // at the address pointed to by the addr register. Only works if addr is not
343 void RememberedSetHelper(Register object, // Used for debug code.
346 SaveFPRegsMode save_fp,
347 RememberedSetFinalAction and_then);
349 void CheckPageFlag(Register object,
353 Label* condition_met);
355 // Check if object is in new space. Jumps if the object is not in new space.
356 // The register scratch can be object itself, but it will be clobbered.
357 void JumpIfNotInNewSpace(Register object,
360 InNewSpace(object, scratch, ne, branch);
363 // Check if object is in new space. Jumps if the object is in new space.
364 // The register scratch can be object itself, but scratch will be clobbered.
365 void JumpIfInNewSpace(Register object,
368 InNewSpace(object, scratch, eq, branch);
371 // Check if an object has a given incremental marking color.
372 void HasColor(Register object,
379 void JumpIfBlack(Register object,
384 // Checks the color of an object. If the object is already grey or black
385 // then we just fall through, since it is already live. If it is white and
386 // we can determine that it doesn't need to be scanned, then we just mark it
387 // black and fall through. For the rest we jump to the label so the
388 // incremental marker can fix its assumptions.
389 void EnsureNotWhite(Register object,
393 Label* object_is_white_and_not_data);
395 // Detects conservatively whether an object is data-only, i.e. it does need to
396 // be scanned by the garbage collector.
397 void JumpIfDataObject(Register value,
399 Label* not_data_object);
401 // Notify the garbage collector that we wrote a pointer into an object.
402 // |object| is the object being stored into, |value| is the object being
403 // stored. value and scratch registers are clobbered by the operation.
404 // The offset is the offset from the start of the object, not the offset from
405 // the tagged HeapObject pointer. For use with FieldOperand(reg, off).
406 void RecordWriteField(
412 SaveFPRegsMode save_fp,
413 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
414 SmiCheck smi_check = INLINE_SMI_CHECK,
415 PointersToHereCheck pointers_to_here_check_for_value =
416 kPointersToHereMaybeInteresting);
418 // As above, but the offset has the tag presubtracted. For use with
419 // MemOperand(reg, off).
420 inline void RecordWriteContextSlot(
426 SaveFPRegsMode save_fp,
427 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
428 SmiCheck smi_check = INLINE_SMI_CHECK,
429 PointersToHereCheck pointers_to_here_check_for_value =
430 kPointersToHereMaybeInteresting) {
431 RecordWriteField(context,
432 offset + kHeapObjectTag,
437 remembered_set_action,
439 pointers_to_here_check_for_value);
442 void RecordWriteForMap(
447 SaveFPRegsMode save_fp);
449 // For a given |object| notify the garbage collector that the slot |address|
450 // has been written. |value| is the object being stored. The value and
451 // address registers are clobbered by the operation.
457 SaveFPRegsMode save_fp,
458 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET,
459 SmiCheck smi_check = INLINE_SMI_CHECK,
460 PointersToHereCheck pointers_to_here_check_for_value =
461 kPointersToHereMaybeInteresting);
464 // ---------------------------------------------------------------------------
465 // Inline caching support.
467 // Generate code for checking access rights - used for security checks
468 // on access to global objects across environments. The holder register
469 // is left untouched, whereas both scratch registers are clobbered.
470 void CheckAccessGlobalProxy(Register holder_reg,
474 void GetNumberHash(Register reg0, Register scratch);
476 void LoadFromNumberDictionary(Label* miss,
485 inline void MarkCode(NopMarkerTypes type) {
489 // Check if the given instruction is a 'type' marker.
490 // i.e. check if it is a sll zero_reg, zero_reg, <type> (referenced as
491 // nop(type)). These instructions are generated to mark special location in
492 // the code, like some special IC code.
493 static inline bool IsMarkedCode(Instr instr, int type) {
494 DCHECK((FIRST_IC_MARKER <= type) && (type < LAST_CODE_MARKER));
495 return IsNop(instr, type);
499 static inline int GetCodeMarker(Instr instr) {
500 uint32_t opcode = ((instr & kOpcodeMask));
501 uint32_t rt = ((instr & kRtFieldMask) >> kRtShift);
502 uint32_t rs = ((instr & kRsFieldMask) >> kRsShift);
503 uint32_t sa = ((instr & kSaFieldMask) >> kSaShift);
505 // Return <n> if we have a sll zero_reg, zero_reg, n
507 bool sllzz = (opcode == SLL &&
508 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
509 rs == static_cast<uint32_t>(ToNumber(zero_reg)));
511 (sllzz && FIRST_IC_MARKER <= sa && sa < LAST_CODE_MARKER) ? sa : -1;
512 DCHECK((type == -1) ||
513 ((FIRST_IC_MARKER <= type) && (type < LAST_CODE_MARKER)));
519 // ---------------------------------------------------------------------------
520 // Allocation support.
522 // Allocate an object in new space or old space. The object_size is
523 // specified either in bytes or in words if the allocation flag SIZE_IN_WORDS
524 // is passed. If the space is exhausted control continues at the gc_required
525 // label. The allocated object is returned in result. If the flag
526 // tag_allocated_object is true the result is tagged as as a heap object.
527 // All registers are clobbered also when control continues at the gc_required
529 void Allocate(int object_size,
534 AllocationFlags flags);
536 void Allocate(Register object_size,
541 AllocationFlags flags);
543 void AllocateTwoByteString(Register result,
549 void AllocateOneByteString(Register result, Register length,
550 Register scratch1, Register scratch2,
551 Register scratch3, Label* gc_required);
552 void AllocateTwoByteConsString(Register result,
557 void AllocateOneByteConsString(Register result, Register length,
558 Register scratch1, Register scratch2,
560 void AllocateTwoByteSlicedString(Register result,
565 void AllocateOneByteSlicedString(Register result, Register length,
566 Register scratch1, Register scratch2,
569 // Allocates a heap number or jumps to the gc_required label if the young
570 // space is full and a scavenge is needed. All registers are clobbered also
571 // when control continues at the gc_required label.
572 void AllocateHeapNumber(Register result,
575 Register heap_number_map,
577 TaggingMode tagging_mode = TAG_RESULT,
578 MutableMode mode = IMMUTABLE);
579 void AllocateHeapNumberWithValue(Register result,
585 // ---------------------------------------------------------------------------
586 // Instruction macros.
588 #define DEFINE_INSTRUCTION(instr) \
589 void instr(Register rd, Register rs, const Operand& rt); \
590 void instr(Register rd, Register rs, Register rt) { \
591 instr(rd, rs, Operand(rt)); \
593 void instr(Register rs, Register rt, int32_t j) { \
594 instr(rs, rt, Operand(j)); \
597 #define DEFINE_INSTRUCTION2(instr) \
598 void instr(Register rs, const Operand& rt); \
599 void instr(Register rs, Register rt) { \
600 instr(rs, Operand(rt)); \
602 void instr(Register rs, int32_t j) { \
603 instr(rs, Operand(j)); \
606 #define DEFINE_INSTRUCTION3(instr) \
607 void instr(Register rd_hi, Register rd_lo, Register rs, const Operand& rt); \
608 void instr(Register rd_hi, Register rd_lo, Register rs, Register rt) { \
609 instr(rd_hi, rd_lo, rs, Operand(rt)); \
611 void instr(Register rd_hi, Register rd_lo, Register rs, int32_t j) { \
612 instr(rd_hi, rd_lo, rs, Operand(j)); \
615 DEFINE_INSTRUCTION(Addu);
616 DEFINE_INSTRUCTION(Subu);
617 DEFINE_INSTRUCTION(Mul);
618 DEFINE_INSTRUCTION(Div);
619 DEFINE_INSTRUCTION(Divu);
620 DEFINE_INSTRUCTION(Mod);
621 DEFINE_INSTRUCTION(Modu);
622 DEFINE_INSTRUCTION(Mulh);
623 DEFINE_INSTRUCTION2(Mult);
624 DEFINE_INSTRUCTION(Mulhu);
625 DEFINE_INSTRUCTION2(Multu);
626 DEFINE_INSTRUCTION2(Div);
627 DEFINE_INSTRUCTION2(Divu);
629 DEFINE_INSTRUCTION3(Div);
630 DEFINE_INSTRUCTION3(Mul);
632 DEFINE_INSTRUCTION(And);
633 DEFINE_INSTRUCTION(Or);
634 DEFINE_INSTRUCTION(Xor);
635 DEFINE_INSTRUCTION(Nor);
636 DEFINE_INSTRUCTION2(Neg);
638 DEFINE_INSTRUCTION(Slt);
639 DEFINE_INSTRUCTION(Sltu);
641 // MIPS32 R2 instruction macro.
642 DEFINE_INSTRUCTION(Ror);
644 #undef DEFINE_INSTRUCTION
645 #undef DEFINE_INSTRUCTION2
647 void Pref(int32_t hint, const MemOperand& rs);
650 // ---------------------------------------------------------------------------
651 // Pseudo-instructions.
653 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); }
655 void Ulw(Register rd, const MemOperand& rs);
656 void Usw(Register rd, const MemOperand& rs);
658 // Load int32 in the rd register.
659 void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE);
660 inline void li(Register rd, int32_t j, LiFlags mode = OPTIMIZE_SIZE) {
661 li(rd, Operand(j), mode);
663 void li(Register dst, Handle<Object> value, LiFlags mode = OPTIMIZE_SIZE);
665 // Push multiple registers on the stack.
666 // Registers are saved in numerical order, with higher numbered registers
667 // saved in higher memory addresses.
668 void MultiPush(RegList regs);
669 void MultiPushReversed(RegList regs);
671 void MultiPushFPU(RegList regs);
672 void MultiPushReversedFPU(RegList regs);
674 void push(Register src) {
675 Addu(sp, sp, Operand(-kPointerSize));
676 sw(src, MemOperand(sp, 0));
678 void Push(Register src) { push(src); }
681 void Push(Handle<Object> handle);
682 void Push(Smi* smi) { Push(Handle<Smi>(smi, isolate())); }
684 // Push two registers. Pushes leftmost register first (to highest address).
685 void Push(Register src1, Register src2) {
686 Subu(sp, sp, Operand(2 * kPointerSize));
687 sw(src1, MemOperand(sp, 1 * kPointerSize));
688 sw(src2, MemOperand(sp, 0 * kPointerSize));
691 // Push three registers. Pushes leftmost register first (to highest address).
692 void Push(Register src1, Register src2, Register src3) {
693 Subu(sp, sp, Operand(3 * kPointerSize));
694 sw(src1, MemOperand(sp, 2 * kPointerSize));
695 sw(src2, MemOperand(sp, 1 * kPointerSize));
696 sw(src3, MemOperand(sp, 0 * kPointerSize));
699 // Push four registers. Pushes leftmost register first (to highest address).
700 void Push(Register src1, Register src2, Register src3, Register src4) {
701 Subu(sp, sp, Operand(4 * kPointerSize));
702 sw(src1, MemOperand(sp, 3 * kPointerSize));
703 sw(src2, MemOperand(sp, 2 * kPointerSize));
704 sw(src3, MemOperand(sp, 1 * kPointerSize));
705 sw(src4, MemOperand(sp, 0 * kPointerSize));
708 // Push five registers. Pushes leftmost register first (to highest address).
709 void Push(Register src1, Register src2, Register src3, Register src4,
711 Subu(sp, sp, Operand(5 * kPointerSize));
712 sw(src1, MemOperand(sp, 4 * kPointerSize));
713 sw(src2, MemOperand(sp, 3 * kPointerSize));
714 sw(src3, MemOperand(sp, 2 * kPointerSize));
715 sw(src4, MemOperand(sp, 1 * kPointerSize));
716 sw(src5, MemOperand(sp, 0 * kPointerSize));
719 void Push(Register src, Condition cond, Register tst1, Register tst2) {
720 // Since we don't have conditional execution we use a Branch.
721 Branch(3, cond, tst1, Operand(tst2));
722 Subu(sp, sp, Operand(kPointerSize));
723 sw(src, MemOperand(sp, 0));
726 // Pops multiple values from the stack and load them in the
727 // registers specified in regs. Pop order is the opposite as in MultiPush.
728 void MultiPop(RegList regs);
729 void MultiPopReversed(RegList regs);
731 void MultiPopFPU(RegList regs);
732 void MultiPopReversedFPU(RegList regs);
734 void pop(Register dst) {
735 lw(dst, MemOperand(sp, 0));
736 Addu(sp, sp, Operand(kPointerSize));
738 void Pop(Register dst) { pop(dst); }
740 // Pop two registers. Pops rightmost register first (from lower address).
741 void Pop(Register src1, Register src2) {
742 DCHECK(!src1.is(src2));
743 lw(src2, MemOperand(sp, 0 * kPointerSize));
744 lw(src1, MemOperand(sp, 1 * kPointerSize));
745 Addu(sp, sp, 2 * kPointerSize);
748 // Pop three registers. Pops rightmost register first (from lower address).
749 void Pop(Register src1, Register src2, Register src3) {
750 lw(src3, MemOperand(sp, 0 * kPointerSize));
751 lw(src2, MemOperand(sp, 1 * kPointerSize));
752 lw(src1, MemOperand(sp, 2 * kPointerSize));
753 Addu(sp, sp, 3 * kPointerSize);
756 void Pop(uint32_t count = 1) {
757 Addu(sp, sp, Operand(count * kPointerSize));
760 // Push and pop the registers that can hold pointers, as defined by the
761 // RegList constant kSafepointSavedRegisters.
762 void PushSafepointRegisters();
763 void PopSafepointRegisters();
764 // Store value in register src in the safepoint stack slot for
766 void StoreToSafepointRegisterSlot(Register src, Register dst);
767 // Load the value of the src register from its safepoint stack slot
768 // into register dst.
769 void LoadFromSafepointRegisterSlot(Register dst, Register src);
771 // Flush the I-cache from asm code. You should use CpuFeatures::FlushICache
773 // Does not handle errors.
774 void FlushICache(Register address, unsigned instructions);
776 // MIPS32 R2 instruction macro.
777 void Ins(Register rt, Register rs, uint16_t pos, uint16_t size);
778 void Ext(Register rt, Register rs, uint16_t pos, uint16_t size);
780 // ---------------------------------------------------------------------------
781 // FPU macros. These do not handle special cases like NaN or +- inf.
783 // Convert unsigned word to double.
784 void Cvt_d_uw(FPURegister fd, FPURegister fs, FPURegister scratch);
785 void Cvt_d_uw(FPURegister fd, Register rs, FPURegister scratch);
787 // Convert double to unsigned word.
788 void Trunc_uw_d(FPURegister fd, FPURegister fs, FPURegister scratch);
789 void Trunc_uw_d(FPURegister fd, Register rs, FPURegister scratch);
791 void Trunc_w_d(FPURegister fd, FPURegister fs);
792 void Round_w_d(FPURegister fd, FPURegister fs);
793 void Floor_w_d(FPURegister fd, FPURegister fs);
794 void Ceil_w_d(FPURegister fd, FPURegister fs);
796 // FP32 mode: Move the general purpose register into
797 // the high part of the double-register pair.
798 // FP64 mode: Move the general-purpose register into
799 // the higher 32 bits of the 64-bit coprocessor register,
800 // while leaving the low bits unchanged.
801 void Mthc1(Register rt, FPURegister fs);
803 // FP32 mode: move the high part of the double-register pair into
804 // general purpose register.
805 // FP64 mode: Move the higher 32 bits of the 64-bit coprocessor register into
806 // general-purpose register.
807 void Mfhc1(Register rt, FPURegister fs);
809 // Wrapper functions for the different cmp/branch types.
810 inline void BranchF32(Label* target, Label* nan, Condition cc,
811 FPURegister cmp1, FPURegister cmp2,
812 BranchDelaySlot bd = PROTECT) {
813 BranchFCommon(S, target, nan, cc, cmp1, cmp2, bd);
816 inline void BranchF64(Label* target, Label* nan, Condition cc,
817 FPURegister cmp1, FPURegister cmp2,
818 BranchDelaySlot bd = PROTECT) {
819 BranchFCommon(D, target, nan, cc, cmp1, cmp2, bd);
822 // Alternate (inline) version for better readability with USE_DELAY_SLOT.
823 inline void BranchF64(BranchDelaySlot bd, Label* target, Label* nan,
824 Condition cc, FPURegister cmp1, FPURegister cmp2) {
825 BranchF64(target, nan, cc, cmp1, cmp2, bd);
828 inline void BranchF32(BranchDelaySlot bd, Label* target, Label* nan,
829 Condition cc, FPURegister cmp1, FPURegister cmp2) {
830 BranchF32(target, nan, cc, cmp1, cmp2, bd);
833 // Alias functions for backward compatibility.
834 inline void BranchF(Label* target, Label* nan, Condition cc, FPURegister cmp1,
835 FPURegister cmp2, BranchDelaySlot bd = PROTECT) {
836 BranchF64(target, nan, cc, cmp1, cmp2, bd);
839 inline void BranchF(BranchDelaySlot bd, Label* target, Label* nan,
840 Condition cc, FPURegister cmp1, FPURegister cmp2) {
841 BranchF64(bd, target, nan, cc, cmp1, cmp2);
844 // Truncates a double using a specific rounding mode, and writes the value
845 // to the result register.
846 // The except_flag will contain any exceptions caused by the instruction.
847 // If check_inexact is kDontCheckForInexactConversion, then the inexact
848 // exception is masked.
849 void EmitFPUTruncate(FPURoundingMode rounding_mode,
851 DoubleRegister double_input,
853 DoubleRegister double_scratch,
854 Register except_flag,
855 CheckForInexactConversion check_inexact
856 = kDontCheckForInexactConversion);
858 // Performs a truncating conversion of a floating point number as used by
859 // the JS bitwise operations. See ECMA-262 9.5: ToInt32. Goes to 'done' if it
860 // succeeds, otherwise falls through if result is saturated. On return
861 // 'result' either holds answer, or is clobbered on fall through.
863 // Only public for the test code in test-code-stubs-arm.cc.
864 void TryInlineTruncateDoubleToI(Register result,
865 DoubleRegister input,
868 // Performs a truncating conversion of a floating point number as used by
869 // the JS bitwise operations. See ECMA-262 9.5: ToInt32.
870 // Exits with 'result' holding the answer.
871 void TruncateDoubleToI(Register result, DoubleRegister double_input);
873 // Performs a truncating conversion of a heap number as used by
874 // the JS bitwise operations. See ECMA-262 9.5: ToInt32. 'result' and 'input'
875 // must be different registers. Exits with 'result' holding the answer.
876 void TruncateHeapNumberToI(Register result, Register object);
878 // Converts the smi or heap number in object to an int32 using the rules
879 // for ToInt32 as described in ECMAScript 9.5.: the value is truncated
880 // and brought into the range -2^31 .. +2^31 - 1. 'result' and 'input' must be
881 // different registers.
882 void TruncateNumberToI(Register object,
884 Register heap_number_map,
888 // Loads the number from object into dst register.
889 // If |object| is neither smi nor heap number, |not_number| is jumped to
890 // with |object| still intact.
891 void LoadNumber(Register object,
893 Register heap_number_map,
897 // Loads the number from object into double_dst in the double format.
898 // Control will jump to not_int32 if the value cannot be exactly represented
899 // by a 32-bit integer.
900 // Floating point value in the 32-bit integer range that are not exact integer
902 void LoadNumberAsInt32Double(Register object,
903 DoubleRegister double_dst,
904 Register heap_number_map,
907 FPURegister double_scratch,
910 // Loads the number from object into dst as a 32-bit integer.
911 // Control will jump to not_int32 if the object cannot be exactly represented
912 // by a 32-bit integer.
913 // Floating point value in the 32-bit integer range that are not exact integer
914 // won't be converted.
915 void LoadNumberAsInt32(Register object,
917 Register heap_number_map,
920 FPURegister double_scratch0,
921 FPURegister double_scratch1,
925 // argc - argument count to be dropped by LeaveExitFrame.
926 // save_doubles - saves FPU registers on stack, currently disabled.
927 // stack_space - extra stack space.
928 void EnterExitFrame(bool save_doubles,
929 int stack_space = 0);
931 // Leave the current exit frame.
932 void LeaveExitFrame(bool save_doubles, Register arg_count,
933 bool restore_context, bool do_return = NO_EMIT_RETURN,
934 bool argument_count_is_length = false);
936 // Get the actual activation frame alignment for target environment.
937 static int ActivationFrameAlignment();
939 // Make sure the stack is aligned. Only emits code in debug mode.
940 void AssertStackIsAligned();
942 void LoadContext(Register dst, int context_chain_length);
944 // Load the global proxy from the current context.
945 void LoadGlobalProxy(Register dst);
947 // Conditionally load the cached Array transitioned map of type
948 // transitioned_kind from the native context if the map in register
949 // map_in_out is the cached Array map in the native context of
951 void LoadTransitionedArrayMapConditional(
952 ElementsKind expected_kind,
953 ElementsKind transitioned_kind,
956 Label* no_map_match);
958 void LoadGlobalFunction(int index, Register function);
960 // Load the initial map from the global function. The registers
961 // function and map can be the same, function is then overwritten.
962 void LoadGlobalFunctionInitialMap(Register function,
966 void InitializeRootRegister() {
967 ExternalReference roots_array_start =
968 ExternalReference::roots_array_start(isolate());
969 li(kRootRegister, Operand(roots_array_start));
972 // -------------------------------------------------------------------------
973 // JavaScript invokes.
975 // Invoke the JavaScript function code by either calling or jumping.
976 void InvokeCode(Register code,
977 const ParameterCount& expected,
978 const ParameterCount& actual,
980 const CallWrapper& call_wrapper);
982 // Invoke the JavaScript function in the given register. Changes the
983 // current context to the context in the function before invoking.
984 void InvokeFunction(Register function,
985 const ParameterCount& actual,
987 const CallWrapper& call_wrapper);
989 void InvokeFunction(Register function,
990 const ParameterCount& expected,
991 const ParameterCount& actual,
993 const CallWrapper& call_wrapper);
995 void InvokeFunction(Handle<JSFunction> function,
996 const ParameterCount& expected,
997 const ParameterCount& actual,
999 const CallWrapper& call_wrapper);
1001 void IsObjectJSStringType(Register object,
1005 void IsObjectNameType(Register object,
1009 // -------------------------------------------------------------------------
1010 // Debugger Support.
1014 // -------------------------------------------------------------------------
1015 // Exception handling.
1017 // Push a new stack handler and link into stack handler chain.
1018 void PushStackHandler();
1020 // Unlink the stack handler on top of the stack from the stack handler chain.
1021 // Must preserve the result register.
1022 void PopStackHandler();
1024 // Copies a fixed number of fields of heap objects from src to dst.
1025 void CopyFields(Register dst, Register src, RegList temps, int field_count);
1027 // Copies a number of bytes from src to dst. All registers are clobbered. On
1028 // exit src and dst will point to the place just after where the last byte was
1029 // read or written and length will be zero.
1030 void CopyBytes(Register src,
1035 // Initialize fields with filler values. Fields starting at |start_offset|
1036 // not including end_offset are overwritten with the value in |filler|. At
1037 // the end the loop, |start_offset| takes the value of |end_offset|.
1038 void InitializeFieldsWithFiller(Register start_offset,
1039 Register end_offset,
1042 // -------------------------------------------------------------------------
1043 // Support functions.
1045 // Machine code version of Map::GetConstructor().
1046 // |temp| holds |result|'s map when done, and |temp2| its instance type.
1047 void GetMapConstructor(Register result, Register map, Register temp,
1050 // Try to get function prototype of a function and puts the value in
1051 // the result register. Checks that the function really is a
1052 // function and jumps to the miss label if the fast checks fail. The
1053 // function register will be untouched; the other registers may be
1055 void TryGetFunctionPrototype(Register function, Register result,
1056 Register scratch, Label* miss);
1058 void GetObjectType(Register function,
1062 // Check if a map for a JSObject indicates that the object has fast elements.
1063 // Jump to the specified label if it does not.
1064 void CheckFastElements(Register map,
1068 // Check if a map for a JSObject indicates that the object can have both smi
1069 // and HeapObject elements. Jump to the specified label if it does not.
1070 void CheckFastObjectElements(Register map,
1074 // Check if a map for a JSObject indicates that the object has fast smi only
1075 // elements. Jump to the specified label if it does not.
1076 void CheckFastSmiElements(Register map,
1080 // Check to see if maybe_number can be stored as a double in
1081 // FastDoubleElements. If it can, store it at the index specified by key in
1082 // the FastDoubleElements array elements. Otherwise jump to fail.
1083 void StoreNumberToDoubleElements(Register value_reg,
1085 Register elements_reg,
1090 int elements_offset = 0);
1092 // Compare an object's map with the specified map and its transitioned
1093 // elements maps if mode is ALLOW_ELEMENT_TRANSITION_MAPS. Jumps to
1094 // "branch_to" if the result of the comparison is "cond". If multiple map
1095 // compares are required, the compare sequences branches to early_success.
1096 void CompareMapAndBranch(Register obj,
1099 Label* early_success,
1103 // As above, but the map of the object is already loaded into the register
1104 // which is preserved by the code generated.
1105 void CompareMapAndBranch(Register obj_map,
1107 Label* early_success,
1111 // Check if the map of an object is equal to a specified map and branch to
1112 // label if not. Skip the smi check if not required (object is known to be a
1113 // heap object). If mode is ALLOW_ELEMENT_TRANSITION_MAPS, then also match
1114 // against maps that are ElementsKind transition maps of the specificed map.
1115 void CheckMap(Register obj,
1119 SmiCheckType smi_check_type);
1122 void CheckMap(Register obj,
1124 Heap::RootListIndex index,
1126 SmiCheckType smi_check_type);
1128 // Check if the map of an object is equal to a specified weak map and branch
1129 // to a specified target if equal. Skip the smi check if not required
1130 // (object is known to be a heap object)
1131 void DispatchWeakMap(Register obj, Register scratch1, Register scratch2,
1132 Handle<WeakCell> cell, Handle<Code> success,
1133 SmiCheckType smi_check_type);
1135 // Get value of the weak cell.
1136 void GetWeakValue(Register value, Handle<WeakCell> cell);
1138 // Load the value of the weak cell in the value register. Branch to the
1139 // given miss label is the weak cell was cleared.
1140 void LoadWeakValue(Register value, Handle<WeakCell> cell, Label* miss);
1142 // Load and check the instance type of an object for being a string.
1143 // Loads the type into the second argument register.
1144 // Returns a condition that will be enabled if the object was a string.
1145 Condition IsObjectStringType(Register obj,
1148 lw(type, FieldMemOperand(obj, HeapObject::kMapOffset));
1149 lbu(type, FieldMemOperand(type, Map::kInstanceTypeOffset));
1150 And(type, type, Operand(kIsNotStringMask));
1151 DCHECK_EQ(0u, kStringTag);
1156 // Picks out an array index from the hash field.
1158 // hash - holds the index's hash. Clobbered.
1159 // index - holds the overwritten index on exit.
1160 void IndexFromHash(Register hash, Register index);
1162 // Get the number of least significant bits from a register.
1163 void GetLeastBitsFromSmi(Register dst, Register src, int num_least_bits);
1164 void GetLeastBitsFromInt32(Register dst, Register src, int mun_least_bits);
1166 // Load the value of a number object into a FPU double register. If the
1167 // object is not a number a jump to the label not_number is performed
1168 // and the FPU double register is unchanged.
1169 void ObjectToDoubleFPURegister(
1174 Register heap_number_map,
1176 ObjectToDoubleFlags flags = NO_OBJECT_TO_DOUBLE_FLAGS);
1178 // Load the value of a smi object into a FPU double register. The register
1179 // scratch1 can be the same register as smi in which case smi will hold the
1180 // untagged value afterwards.
1181 void SmiToDoubleFPURegister(Register smi,
1185 // -------------------------------------------------------------------------
1186 // Overflow handling functions.
1187 // Usage: first call the appropriate arithmetic function, then call one of the
1188 // jump functions with the overflow_dst register as the second parameter.
1190 void AdduAndCheckForOverflow(Register dst,
1193 Register overflow_dst,
1194 Register scratch = at);
1196 void AdduAndCheckForOverflow(Register dst, Register left,
1197 const Operand& right, Register overflow_dst,
1198 Register scratch = at);
1200 void SubuAndCheckForOverflow(Register dst,
1203 Register overflow_dst,
1204 Register scratch = at);
1206 void SubuAndCheckForOverflow(Register dst, Register left,
1207 const Operand& right, Register overflow_dst,
1208 Register scratch = at);
1210 void BranchOnOverflow(Label* label,
1211 Register overflow_check,
1212 BranchDelaySlot bd = PROTECT) {
1213 Branch(label, lt, overflow_check, Operand(zero_reg), bd);
1216 void BranchOnNoOverflow(Label* label,
1217 Register overflow_check,
1218 BranchDelaySlot bd = PROTECT) {
1219 Branch(label, ge, overflow_check, Operand(zero_reg), bd);
1222 void RetOnOverflow(Register overflow_check, BranchDelaySlot bd = PROTECT) {
1223 Ret(lt, overflow_check, Operand(zero_reg), bd);
1226 void RetOnNoOverflow(Register overflow_check, BranchDelaySlot bd = PROTECT) {
1227 Ret(ge, overflow_check, Operand(zero_reg), bd);
1230 // -------------------------------------------------------------------------
1233 // See comments at the beginning of CEntryStub::Generate.
1234 inline void PrepareCEntryArgs(int num_args) { li(a0, num_args); }
1236 inline void PrepareCEntryFunction(const ExternalReference& ref) {
1237 li(a1, Operand(ref));
1240 #define COND_ARGS Condition cond = al, Register rs = zero_reg, \
1241 const Operand& rt = Operand(zero_reg), BranchDelaySlot bd = PROTECT
1243 // Call a code stub.
1244 void CallStub(CodeStub* stub,
1245 TypeFeedbackId ast_id = TypeFeedbackId::None(),
1248 // Tail call a code stub (jump).
1249 void TailCallStub(CodeStub* stub, COND_ARGS);
1253 void CallJSExitStub(CodeStub* stub);
1255 // Call a runtime routine.
1256 void CallRuntime(const Runtime::Function* f, int num_arguments,
1257 SaveFPRegsMode save_doubles = kDontSaveFPRegs,
1258 BranchDelaySlot bd = PROTECT);
1259 void CallRuntimeSaveDoubles(Runtime::FunctionId id) {
1260 const Runtime::Function* function = Runtime::FunctionForId(id);
1261 CallRuntime(function, function->nargs, kSaveFPRegs);
1264 // Convenience function: Same as above, but takes the fid instead.
1265 void CallRuntime(Runtime::FunctionId id, int num_arguments,
1266 SaveFPRegsMode save_doubles = kDontSaveFPRegs,
1267 BranchDelaySlot bd = PROTECT) {
1268 CallRuntime(Runtime::FunctionForId(id), num_arguments, save_doubles, bd);
1271 // Convenience function: call an external reference.
1272 void CallExternalReference(const ExternalReference& ext,
1274 BranchDelaySlot bd = PROTECT);
1276 // Tail call of a runtime routine (jump).
1277 // Like JumpToExternalReference, but also takes care of passing the number
1279 void TailCallExternalReference(const ExternalReference& ext,
1283 // Convenience function: tail call a runtime routine (jump).
1284 void TailCallRuntime(Runtime::FunctionId fid,
1288 int CalculateStackPassedWords(int num_reg_arguments,
1289 int num_double_arguments);
1291 // Before calling a C-function from generated code, align arguments on stack
1292 // and add space for the four mips argument slots.
1293 // After aligning the frame, non-register arguments must be stored on the
1294 // stack, after the argument-slots using helper: CFunctionArgumentOperand().
1295 // The argument count assumes all arguments are word sized.
1296 // Some compilers/platforms require the stack to be aligned when calling
1298 // Needs a scratch register to do some arithmetic. This register will be
1300 void PrepareCallCFunction(int num_reg_arguments,
1301 int num_double_registers,
1303 void PrepareCallCFunction(int num_reg_arguments,
1306 // Arguments 1-4 are placed in registers a0 thru a3 respectively.
1307 // Arguments 5..n are stored to stack using following:
1308 // sw(t0, CFunctionArgumentOperand(5));
1310 // Calls a C function and cleans up the space for arguments allocated
1311 // by PrepareCallCFunction. The called function is not allowed to trigger a
1312 // garbage collection, since that might move the code and invalidate the
1313 // return address (unless this is somehow accounted for by the called
1315 void CallCFunction(ExternalReference function, int num_arguments);
1316 void CallCFunction(Register function, int num_arguments);
1317 void CallCFunction(ExternalReference function,
1318 int num_reg_arguments,
1319 int num_double_arguments);
1320 void CallCFunction(Register function,
1321 int num_reg_arguments,
1322 int num_double_arguments);
1323 void MovFromFloatResult(DoubleRegister dst);
1324 void MovFromFloatParameter(DoubleRegister dst);
1326 // There are two ways of passing double arguments on MIPS, depending on
1327 // whether soft or hard floating point ABI is used. These functions
1328 // abstract parameter passing for the three different ways we call
1329 // C functions from generated code.
1330 void MovToFloatParameter(DoubleRegister src);
1331 void MovToFloatParameters(DoubleRegister src1, DoubleRegister src2);
1332 void MovToFloatResult(DoubleRegister src);
1334 // Jump to the builtin routine.
1335 void JumpToExternalReference(const ExternalReference& builtin,
1336 BranchDelaySlot bd = PROTECT);
1338 // Invoke specified builtin JavaScript function.
1339 void InvokeBuiltin(int native_context_index, InvokeFlag flag,
1340 const CallWrapper& call_wrapper = NullCallWrapper());
1342 // Store the code object for the given builtin in the target register and
1343 // setup the function in a1.
1344 void GetBuiltinEntry(Register target, int native_context_index);
1346 // Store the function for the given builtin in the target register.
1347 void GetBuiltinFunction(Register target, int native_context_index);
1351 uint32_t flags; // See Bootstrapper::FixupFlags decoders/encoders.
1355 Handle<Object> CodeObject() {
1356 DCHECK(!code_object_.is_null());
1357 return code_object_;
1360 // Emit code for a truncating division by a constant. The dividend register is
1361 // unchanged and at gets clobbered. Dividend and result must be different.
1362 void TruncatingDiv(Register result, Register dividend, int32_t divisor);
1364 // -------------------------------------------------------------------------
1365 // StatsCounter support.
1367 void SetCounter(StatsCounter* counter, int value,
1368 Register scratch1, Register scratch2);
1369 void IncrementCounter(StatsCounter* counter, int value,
1370 Register scratch1, Register scratch2);
1371 void DecrementCounter(StatsCounter* counter, int value,
1372 Register scratch1, Register scratch2);
1375 // -------------------------------------------------------------------------
1378 // Calls Abort(msg) if the condition cc is not satisfied.
1379 // Use --debug_code to enable.
1380 void Assert(Condition cc, BailoutReason reason, Register rs, Operand rt);
1381 void AssertFastElements(Register elements);
1383 // Like Assert(), but always enabled.
1384 void Check(Condition cc, BailoutReason reason, Register rs, Operand rt);
1386 // Print a message to stdout and abort execution.
1387 void Abort(BailoutReason msg);
1389 // Verify restrictions about code generated in stubs.
1390 void set_generating_stub(bool value) { generating_stub_ = value; }
1391 bool generating_stub() { return generating_stub_; }
1392 void set_has_frame(bool value) { has_frame_ = value; }
1393 bool has_frame() { return has_frame_; }
1394 inline bool AllowThisStubCall(CodeStub* stub);
1396 // ---------------------------------------------------------------------------
1397 // Number utilities.
1399 // Check whether the value of reg is a power of two and not zero. If not
1400 // control continues at the label not_power_of_two. If reg is a power of two
1401 // the register scratch contains the value of (reg - 1) when control falls
1403 void JumpIfNotPowerOfTwoOrZero(Register reg,
1405 Label* not_power_of_two_or_zero);
1407 // -------------------------------------------------------------------------
1410 void SmiTag(Register reg) {
1411 Addu(reg, reg, reg);
1414 // Test for overflow < 0: use BranchOnOverflow() or BranchOnNoOverflow().
1415 void SmiTagCheckOverflow(Register reg, Register overflow);
1416 void SmiTagCheckOverflow(Register dst, Register src, Register overflow);
1418 void SmiTag(Register dst, Register src) {
1419 Addu(dst, src, src);
1422 // Try to convert int32 to smi. If the value is to large, preserve
1423 // the original value and jump to not_a_smi. Destroys scratch and
1425 void TrySmiTag(Register reg, Register scratch, Label* not_a_smi) {
1426 TrySmiTag(reg, reg, scratch, not_a_smi);
1428 void TrySmiTag(Register dst,
1432 SmiTagCheckOverflow(at, src, scratch);
1433 BranchOnOverflow(not_a_smi, scratch);
1437 void SmiUntag(Register reg) {
1438 sra(reg, reg, kSmiTagSize);
1441 void SmiUntag(Register dst, Register src) {
1442 sra(dst, src, kSmiTagSize);
1445 // Test if the register contains a smi.
1446 inline void SmiTst(Register value, Register scratch) {
1447 And(scratch, value, Operand(kSmiTagMask));
1449 inline void NonNegativeSmiTst(Register value, Register scratch) {
1450 And(scratch, value, Operand(kSmiTagMask | kSmiSignMask));
1453 // Untag the source value into destination and jump if source is a smi.
1454 // Souce and destination can be the same register.
1455 void UntagAndJumpIfSmi(Register dst, Register src, Label* smi_case);
1457 // Untag the source value into destination and jump if source is not a smi.
1458 // Souce and destination can be the same register.
1459 void UntagAndJumpIfNotSmi(Register dst, Register src, Label* non_smi_case);
1461 // Jump the register contains a smi.
1462 void JumpIfSmi(Register value,
1464 Register scratch = at,
1465 BranchDelaySlot bd = PROTECT);
1467 // Jump if the register contains a non-smi.
1468 void JumpIfNotSmi(Register value,
1469 Label* not_smi_label,
1470 Register scratch = at,
1471 BranchDelaySlot bd = PROTECT);
1473 // Jump if either of the registers contain a non-smi.
1474 void JumpIfNotBothSmi(Register reg1, Register reg2, Label* on_not_both_smi);
1475 // Jump if either of the registers contain a smi.
1476 void JumpIfEitherSmi(Register reg1, Register reg2, Label* on_either_smi);
1478 // Abort execution if argument is a smi, enabled via --debug-code.
1479 void AssertNotSmi(Register object);
1480 void AssertSmi(Register object);
1482 // Abort execution if argument is not a string, enabled via --debug-code.
1483 void AssertString(Register object);
1485 // Abort execution if argument is not a name, enabled via --debug-code.
1486 void AssertName(Register object);
1488 // Abort execution if argument is not a JSFunction, enabled via --debug-code.
1489 void AssertFunction(Register object);
1491 // Abort execution if argument is not undefined or an AllocationSite, enabled
1492 // via --debug-code.
1493 void AssertUndefinedOrAllocationSite(Register object, Register scratch);
1495 // Abort execution if reg is not the root value with the given index,
1496 // enabled via --debug-code.
1497 void AssertIsRoot(Register reg, Heap::RootListIndex index);
1499 // ---------------------------------------------------------------------------
1500 // HeapNumber utilities.
1502 void JumpIfNotHeapNumber(Register object,
1503 Register heap_number_map,
1505 Label* on_not_heap_number);
1507 // -------------------------------------------------------------------------
1508 // String utilities.
1510 // Generate code to do a lookup in the number string cache. If the number in
1511 // the register object is found in the cache the generated code falls through
1512 // with the result in the result register. The object and the result register
1513 // can be the same. If the number is not found in the cache the code jumps to
1514 // the label not_found with only the content of register object unchanged.
1515 void LookupNumberStringCache(Register object,
1522 // Checks if both instance types are sequential ASCII strings and jumps to
1523 // label if either is not.
1524 void JumpIfBothInstanceTypesAreNotSequentialOneByte(
1525 Register first_object_instance_type, Register second_object_instance_type,
1526 Register scratch1, Register scratch2, Label* failure);
1528 // Check if instance type is sequential one-byte string and jump to label if
1530 void JumpIfInstanceTypeIsNotSequentialOneByte(Register type, Register scratch,
1533 void JumpIfNotUniqueNameInstanceType(Register reg, Label* not_unique_name);
1535 void EmitSeqStringSetCharCheck(Register string,
1539 uint32_t encoding_mask);
1541 // Checks if both objects are sequential one-byte strings and jumps to label
1542 // if either is not. Assumes that neither object is a smi.
1543 void JumpIfNonSmisNotBothSequentialOneByteStrings(Register first,
1549 // Checks if both objects are sequential one-byte strings and jumps to label
1550 // if either is not.
1551 void JumpIfNotBothSequentialOneByteStrings(Register first, Register second,
1554 Label* not_flat_one_byte_strings);
1556 void ClampUint8(Register output_reg, Register input_reg);
1558 void ClampDoubleToUint8(Register result_reg,
1559 DoubleRegister input_reg,
1560 DoubleRegister temp_double_reg);
1563 void LoadInstanceDescriptors(Register map, Register descriptors);
1564 void EnumLength(Register dst, Register map);
1565 void NumberOfOwnDescriptors(Register dst, Register map);
1566 void LoadAccessor(Register dst, Register holder, int accessor_index,
1567 AccessorComponent accessor);
1569 template<typename Field>
1570 void DecodeField(Register dst, Register src) {
1571 Ext(dst, src, Field::kShift, Field::kSize);
1574 template<typename Field>
1575 void DecodeField(Register reg) {
1576 DecodeField<Field>(reg, reg);
1579 template<typename Field>
1580 void DecodeFieldToSmi(Register dst, Register src) {
1581 static const int shift = Field::kShift;
1582 static const int mask = Field::kMask >> shift << kSmiTagSize;
1583 STATIC_ASSERT((mask & (0x80000000u >> (kSmiTagSize - 1))) == 0);
1584 STATIC_ASSERT(kSmiTag == 0);
1585 if (shift < kSmiTagSize) {
1586 sll(dst, src, kSmiTagSize - shift);
1587 And(dst, dst, Operand(mask));
1588 } else if (shift > kSmiTagSize) {
1589 srl(dst, src, shift - kSmiTagSize);
1590 And(dst, dst, Operand(mask));
1592 And(dst, src, Operand(mask));
1596 template<typename Field>
1597 void DecodeFieldToSmi(Register reg) {
1598 DecodeField<Field>(reg, reg);
1601 // Generates function and stub prologue code.
1602 void StubPrologue();
1603 void Prologue(bool code_pre_aging);
1605 // Activation support.
1606 void EnterFrame(StackFrame::Type type);
1607 void EnterFrame(StackFrame::Type type, bool load_constant_pool_pointer_reg);
1608 void LeaveFrame(StackFrame::Type type);
1610 // Expects object in a0 and returns map with validated enum cache
1611 // in a0. Assumes that any other register can be used as a scratch.
1612 void CheckEnumCache(Register null_value, Label* call_runtime);
1614 // AllocationMemento support. Arrays may have an associated
1615 // AllocationMemento object that can be checked for in order to pretransition
1617 // On entry, receiver_reg should point to the array object.
1618 // scratch_reg gets clobbered.
1619 // If allocation info is present, jump to allocation_memento_present.
1620 void TestJSArrayForAllocationMemento(
1621 Register receiver_reg,
1622 Register scratch_reg,
1623 Label* no_memento_found,
1624 Condition cond = al,
1625 Label* allocation_memento_present = NULL);
1627 void JumpIfJSArrayHasAllocationMemento(Register receiver_reg,
1628 Register scratch_reg,
1629 Label* memento_found) {
1630 Label no_memento_found;
1631 TestJSArrayForAllocationMemento(receiver_reg, scratch_reg,
1632 &no_memento_found, eq, memento_found);
1633 bind(&no_memento_found);
1636 // Jumps to found label if a prototype map has dictionary elements.
1637 void JumpIfDictionaryInPrototypeChain(Register object, Register scratch0,
1638 Register scratch1, Label* found);
1641 void CallCFunctionHelper(Register function,
1642 int num_reg_arguments,
1643 int num_double_arguments);
1645 void BranchAndLinkShort(int16_t offset, BranchDelaySlot bdslot = PROTECT);
1646 void BranchAndLinkShort(int16_t offset, Condition cond, Register rs,
1648 BranchDelaySlot bdslot = PROTECT);
1649 void BranchAndLinkShort(Label* L, BranchDelaySlot bdslot = PROTECT);
1650 void BranchAndLinkShort(Label* L, Condition cond, Register rs,
1652 BranchDelaySlot bdslot = PROTECT);
1653 void Jr(Label* L, BranchDelaySlot bdslot);
1654 void Jalr(Label* L, BranchDelaySlot bdslot);
1656 // Common implementation of BranchF functions for the different formats.
1657 void BranchFCommon(SecondaryField sizeField, Label* target, Label* nan,
1658 Condition cc, FPURegister cmp1, FPURegister cmp2,
1659 BranchDelaySlot bd = PROTECT);
1661 void BranchShortF(SecondaryField sizeField, Label* target, Condition cc,
1662 FPURegister cmp1, FPURegister cmp2,
1663 BranchDelaySlot bd = PROTECT);
1665 // Helper functions for generating invokes.
1666 void InvokePrologue(const ParameterCount& expected,
1667 const ParameterCount& actual,
1668 Handle<Code> code_constant,
1671 bool* definitely_mismatches,
1673 const CallWrapper& call_wrapper);
1675 void InitializeNewString(Register string,
1677 Heap::RootListIndex map_index,
1681 // Helper for implementing JumpIfNotInNewSpace and JumpIfInNewSpace.
1682 void InNewSpace(Register object,
1684 Condition cond, // eq for new space, ne otherwise.
1687 // Helper for finding the mark bits for an address. Afterwards, the
1688 // bitmap register points at the word with the mark bits and the mask
1689 // the position of the first bit. Leaves addr_reg unchanged.
1690 inline void GetMarkBits(Register addr_reg,
1691 Register bitmap_reg,
1694 // Compute memory operands for safepoint stack slots.
1695 static int SafepointRegisterStackIndex(int reg_code);
1696 MemOperand SafepointRegisterSlot(Register reg);
1697 MemOperand SafepointRegistersAndDoublesSlot(Register reg);
1699 bool generating_stub_;
1701 bool has_double_zero_reg_set_;
1702 // This handle will be patched with the code object on installation.
1703 Handle<Object> code_object_;
1705 // Needs access to SafepointRegisterStackIndex for compiled frame
1707 friend class StandardFrame;
1711 // The code patcher is used to patch (typically) small parts of code e.g. for
1712 // debugging and other types of instrumentation. When using the code patcher
1713 // the exact number of bytes specified must be emitted. It is not legal to emit
1714 // relocation information. If any of these constraints are violated it causes
1715 // an assertion to fail.
1723 CodePatcher(byte* address,
1725 FlushICache flush_cache = FLUSH);
1728 // Macro assembler to emit code.
1729 MacroAssembler* masm() { return &masm_; }
1731 // Emit an instruction directly.
1732 void Emit(Instr instr);
1734 // Emit an address directly.
1735 void Emit(Address addr);
1737 // Change the condition part of an instruction leaving the rest of the current
1738 // instruction unchanged.
1739 void ChangeBranchCondition(Condition cond);
1742 byte* address_; // The address of the code being patched.
1743 int size_; // Number of bytes of the expected patch size.
1744 MacroAssembler masm_; // Macro assembler used to generate the code.
1745 FlushICache flush_cache_; // Whether to flush the I cache after patching.
1750 #ifdef GENERATED_CODE_COVERAGE
1751 #define CODE_COVERAGE_STRINGIFY(x) #x
1752 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x)
1753 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
1754 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
1756 #define ACCESS_MASM(masm) masm->
1759 } } // namespace v8::internal
1761 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_