src/mesa/drivers/dri/r600/r700_chip.c

   1 /*
   2  * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21
  22 /*
  23  * Authors:
  24  *   Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
  25  *   CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
  26  */
  27
  28 #include "main/imports.h"
  29 #include "main/glheader.h"
  30 #include "main/simple_list.h"
  31
  32 #include "r600_context.h"
  33 #include "r600_cmdbuf.h"
  34
  35 #include "r600_tex.h"
  36 #include "r700_oglprog.h"
  37 #include "r700_fragprog.h"
  38 #include "r700_vertprog.h"
  39
  40 #include "radeon_mipmap_tree.h"
  41
  42 static void r700SendTexState(struct gl_context *ctx, struct radeon_state_atom *atom)
  43 {
  44         context_t         *context = R700_CONTEXT(ctx);
  45         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
  46
  47     struct r700_vertex_program *vp = context->selected_vp;
  48
  49         struct radeon_bo *bo = NULL;
  50         unsigned int i;
  51         BATCH_LOCALS(&context->radeon);
  52
  53         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
  54
  55         for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
  56                 if (ctx->Texture.Unit[i]._ReallyEnabled) {
  57                         radeonTexObj *t = r700->textures[i];
  58                         if (t) {
  59                                 if (!t->image_override) {
  60                                         bo = t->mt->bo;
  61                                 } else {
  62                                         bo = t->bo;
  63                                 }
  64                                 if (bo) {
  65
  66                                         r700SyncSurf(context, bo,
  67                                                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
  68                                                      0, TC_ACTION_ENA_bit);
  69
  70                                         BEGIN_BATCH_NO_AUTOSTATE(9 + 4);
  71                                         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
  72
  73                     if( (1<<i) & vp->r700AsmCode.unVetTexBits )
  74                     {   /* vs texture */
  75                         R600_OUT_BATCH((i + VERT_ATTRIB_MAX + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
  76                     }
  77                     else
  78                     {
  79                                             R600_OUT_BATCH(i * 7);
  80                     }
  81
  82                                         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
  83                                         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
  84                                         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE2);
  85                                         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE3);
  86                                         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
  87                                         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
  88                                         R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
  89                                         R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
  90                                                              bo,
  91                                                              r700->textures[i]->SQ_TEX_RESOURCE2,
  92                                                              RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
  93                                         R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
  94                                                              bo,
  95                                                              r700->textures[i]->SQ_TEX_RESOURCE3,
  96                                                              RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
  97                                         END_BATCH();
  98                                         COMMIT_BATCH();
  99                                 }
 100                         }
 101                 }
 102         }
 103 }
 104
 105 #define SAMPLER_STRIDE                 3
 106
 107 static void r700SendTexSamplerState(struct gl_context *ctx, struct radeon_state_atom *atom)
 108 {
 109         context_t         *context = R700_CONTEXT(ctx);
 110         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 111         unsigned int i;
 112
 113     struct r700_vertex_program *vp = context->selected_vp;
 114
 115         BATCH_LOCALS(&context->radeon);
 116         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 117
 118         for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
 119                 if (ctx->Texture.Unit[i]._ReallyEnabled) {
 120                         radeonTexObj *t = r700->textures[i];
 121                         if (t) {
 122                                 BEGIN_BATCH_NO_AUTOSTATE(5);
 123                                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
 124
 125                 if( (1<<i) & vp->r700AsmCode.unVetTexBits )
 126                 {   /* vs texture */
 127                     R600_OUT_BATCH((i+SQ_TEX_SAMPLER_VS_OFFSET) * SAMPLER_STRIDE); //work 1
 128                 }
 129                 else
 130                 {
 131                                     R600_OUT_BATCH(i * 3);
 132                 }
 133
 134                                 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
 135                                 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
 136                                 R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
 137                                 END_BATCH();
 138                                 COMMIT_BATCH();
 139                         }
 140                 }
 141         }
 142 }
 143
 144 static void r700SendTexBorderColorState(struct gl_context *ctx, struct radeon_state_atom *atom)
 145 {
 146         context_t         *context = R700_CONTEXT(ctx);
 147         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 148         unsigned int i;
 149         BATCH_LOCALS(&context->radeon);
 150         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 151
 152         for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
 153                 if (ctx->Texture.Unit[i]._ReallyEnabled) {
 154                         radeonTexObj *t = r700->textures[i];
 155                         if (t) {
 156                                 BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
 157                                 R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
 158                                 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
 159                                 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
 160                                 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
 161                                 R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
 162                                 END_BATCH();
 163                                 COMMIT_BATCH();
 164                         }
 165                 }
 166         }
 167 }
 168
 169 extern int getTypeSize(GLenum type);
 170 static void r700SetupVTXConstants(struct gl_context  * ctx,
 171                                   void *       pAos,
 172                                   StreamDesc * pStreamDesc)
 173 {
 174     context_t *context = R700_CONTEXT(ctx);
 175     struct radeon_aos * paos = (struct radeon_aos *)pAos;
 176     BATCH_LOCALS(&context->radeon);
 177
 178     unsigned int uSQ_VTX_CONSTANT_WORD0_0;
 179     unsigned int uSQ_VTX_CONSTANT_WORD1_0;
 180     unsigned int uSQ_VTX_CONSTANT_WORD2_0 = 0;
 181     unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
 182     unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
 183
 184     if (!paos->bo)
 185             return;
 186
 187     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 188         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 189         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
 190         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS880) ||
 191         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
 192             r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
 193     else
 194             r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 195
 196     uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
 197     uSQ_VTX_CONSTANT_WORD1_0 = paos->bo->size - paos->offset - 1;
 198
 199     SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
 200     SETfield(uSQ_VTX_CONSTANT_WORD2_0, pStreamDesc->stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
 201              SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
 202     SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
 203              SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
 204              SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
 205         SETfield(uSQ_VTX_CONSTANT_WORD2_0,
 206 #ifdef MESA_BIG_ENDIAN
 207                          SQ_ENDIAN_8IN32,
 208 #else
 209                          SQ_ENDIAN_NONE,
 210 #endif
 211              SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
 212              SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
 213
 214     if(GL_TRUE == pStreamDesc->normalize)
 215     {
 216         SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
 217                      SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
 218     }
 219     else
 220     {
 221         SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
 222                      SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
 223     }
 224
 225     if(1 == pStreamDesc->_signed)
 226     {
 227         SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
 228     }
 229
 230     SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
 231     SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
 232              SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
 233
 234     BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
 235
 236     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
 237     R600_OUT_BATCH((pStreamDesc->element + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE);
 238     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD0_0);
 239     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
 240     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
 241     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
 242     R600_OUT_BATCH(0);
 243     R600_OUT_BATCH(0);
 244     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0);
 245     R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
 246                          paos->bo,
 247                          uSQ_VTX_CONSTANT_WORD0_0,
 248                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 249     END_BATCH();
 250     COMMIT_BATCH();
 251
 252 }
 253
 254 static void r700SendVTXState(struct gl_context *ctx, struct radeon_state_atom *atom)
 255 {
 256     context_t         *context = R700_CONTEXT(ctx);
 257     struct r700_vertex_program *vp = context->selected_vp;
 258     unsigned int i, j = 0;
 259     BATCH_LOCALS(&context->radeon);
 260     (void) b_l_rmesa; /* silence unused var warning */
 261         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 262
 263     if (context->radeon.tcl.aos_count == 0)
 264             return;
 265
 266     for(i=0; i<VERT_ATTRIB_MAX; i++) {
 267             if(vp->mesa_program->Base.InputsRead & (1 << i))
 268             {
 269                 r700SetupVTXConstants(ctx,
 270                                       (void*)(&context->radeon.tcl.aos[j]),
 271                                       &(context->stream_desc[j]));
 272                 j++;
 273             }
 274     }
 275 }
 276
 277 static void r700SetRenderTarget(context_t *context, int id)
 278 {
 279     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 280     uint32_t format = COLOR_8_8_8_8, comp_swap = SWAP_ALT, number_type = NUMBER_UNORM;
 281     struct radeon_renderbuffer *rrb;
 282     unsigned int nPitchInPixel, height;
 283
 284     rrb = radeon_get_colorbuffer(&context->radeon);
 285     if (!rrb || !rrb->bo) {
 286             return;
 287     }
 288
 289     R600_STATECHANGE(context, cb_target);
 290
 291     /* color buffer */
 292     r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset / 256;
 293
 294     nPitchInPixel = rrb->pitch/rrb->cpp;
 295
 296     if (context->radeon.radeonScreen->driScreen->dri2.enabled)
 297     {
 298         height = rrb->base.Height;
 299     }
 300     else
 301     {
 302         height =  context->radeon.radeonScreen->driScreen->fbHeight;
 303     }
 304
 305     SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
 306              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
 307     SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
 308              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
 309     SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
 310     SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
 311              CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 312
 313     switch (rrb->base.Format) {
 314     case MESA_FORMAT_RGBA8888:
 315             format = COLOR_8_8_8_8;
 316             comp_swap = SWAP_STD_REV;
 317             number_type = NUMBER_UNORM;
 318             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 319             break;
 320     case MESA_FORMAT_SIGNED_RGBA8888:
 321             format = COLOR_8_8_8_8;
 322             comp_swap = SWAP_STD_REV;
 323             number_type = NUMBER_SNORM;
 324             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 325             break;
 326     case MESA_FORMAT_RGBA8888_REV:
 327             format = COLOR_8_8_8_8;
 328             comp_swap = SWAP_STD;
 329             number_type = NUMBER_UNORM;
 330             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 331             break;
 332     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 333             format = COLOR_8_8_8_8;
 334             comp_swap = SWAP_STD;
 335             number_type = NUMBER_SNORM;
 336             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 337             break;
 338     case MESA_FORMAT_ARGB8888:
 339     case MESA_FORMAT_XRGB8888:
 340             format = COLOR_8_8_8_8;
 341             comp_swap = SWAP_ALT;
 342             number_type = NUMBER_UNORM;
 343             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 344             break;
 345     case MESA_FORMAT_ARGB8888_REV:
 346     case MESA_FORMAT_XRGB8888_REV:
 347             format = COLOR_8_8_8_8;
 348             comp_swap = SWAP_ALT_REV;
 349             number_type = NUMBER_UNORM;
 350             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 351             break;
 352     case MESA_FORMAT_RGB565:
 353             format = COLOR_5_6_5;
 354             comp_swap = SWAP_STD_REV;
 355             number_type = NUMBER_UNORM;
 356             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 357             break;
 358     case MESA_FORMAT_RGB565_REV:
 359             format = COLOR_5_6_5;
 360             comp_swap = SWAP_STD;
 361             number_type = NUMBER_UNORM;
 362             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 363             break;
 364     case MESA_FORMAT_ARGB4444:
 365             format = COLOR_4_4_4_4;
 366             comp_swap = SWAP_ALT;
 367             number_type = NUMBER_UNORM;
 368             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 369             break;
 370     case MESA_FORMAT_ARGB4444_REV:
 371             format = COLOR_4_4_4_4;
 372             comp_swap = SWAP_ALT_REV;
 373             number_type = NUMBER_UNORM;
 374             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 375             break;
 376     case MESA_FORMAT_ARGB1555:
 377             format = COLOR_1_5_5_5;
 378             comp_swap = SWAP_ALT;
 379             number_type = NUMBER_UNORM;
 380             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 381             break;
 382     case MESA_FORMAT_ARGB1555_REV:
 383             format = COLOR_1_5_5_5;
 384             comp_swap = SWAP_ALT_REV;
 385             number_type = NUMBER_UNORM;
 386             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 387             break;
 388     case MESA_FORMAT_AL88:
 389             format = COLOR_8_8;
 390             comp_swap = SWAP_STD;
 391             number_type = NUMBER_UNORM;
 392             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 393             break;
 394     case MESA_FORMAT_AL88_REV:
 395             format = COLOR_8_8;
 396             comp_swap = SWAP_STD_REV;
 397             number_type = NUMBER_UNORM;
 398             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 399             break;
 400     case MESA_FORMAT_RGB332:
 401             format = COLOR_3_3_2;
 402             comp_swap = SWAP_STD_REV;
 403             number_type = NUMBER_UNORM;
 404             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 405             break;
 406     case MESA_FORMAT_A8:
 407             format = COLOR_8;
 408             comp_swap = SWAP_ALT_REV;
 409             number_type = NUMBER_UNORM;
 410             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 411             break;
 412     case MESA_FORMAT_I8:
 413     case MESA_FORMAT_CI8:
 414             format = COLOR_8;
 415             comp_swap = SWAP_STD;
 416             number_type = NUMBER_UNORM;
 417             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 418             break;
 419     case MESA_FORMAT_L8:
 420             format = COLOR_8;
 421             comp_swap = SWAP_ALT;
 422             number_type = NUMBER_UNORM;
 423             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 424             break;
 425     case MESA_FORMAT_RGBA_FLOAT32:
 426             format = COLOR_32_32_32_32_FLOAT;
 427             comp_swap = SWAP_STD_REV;
 428             number_type = NUMBER_FLOAT;
 429             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
 430             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 431             break;
 432     case MESA_FORMAT_RGBA_FLOAT16:
 433             format = COLOR_16_16_16_16_FLOAT;
 434             comp_swap = SWAP_STD_REV;
 435             number_type = NUMBER_FLOAT;
 436             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 437             break;
 438     case MESA_FORMAT_ALPHA_FLOAT32:
 439             format = COLOR_32_FLOAT;
 440             comp_swap = SWAP_ALT_REV;
 441             number_type = NUMBER_FLOAT;
 442             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
 443             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 444             break;
 445     case MESA_FORMAT_ALPHA_FLOAT16:
 446             format = COLOR_16_FLOAT;
 447             comp_swap = SWAP_ALT_REV;
 448             number_type = NUMBER_FLOAT;
 449             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 450             break;
 451     case MESA_FORMAT_LUMINANCE_FLOAT32:
 452             format = COLOR_32_FLOAT;
 453             comp_swap = SWAP_ALT;
 454             number_type = NUMBER_FLOAT;
 455             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
 456             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 457             break;
 458     case MESA_FORMAT_LUMINANCE_FLOAT16:
 459             format = COLOR_16_FLOAT;
 460             comp_swap = SWAP_ALT;
 461             number_type = NUMBER_FLOAT;
 462             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 463             break;
 464     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 465             format = COLOR_32_32_FLOAT;
 466             comp_swap = SWAP_ALT_REV;
 467             number_type = NUMBER_FLOAT;
 468             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
 469             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 470             break;
 471     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 472             format = COLOR_16_16_FLOAT;
 473             comp_swap = SWAP_ALT_REV;
 474             number_type = NUMBER_FLOAT;
 475             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 476             break;
 477     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 478             format = COLOR_32_FLOAT;
 479             comp_swap = SWAP_STD;
 480             number_type = NUMBER_FLOAT;
 481             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
 482             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 483             break;
 484     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 485             format = COLOR_16_FLOAT;
 486             comp_swap = SWAP_STD;
 487             number_type = NUMBER_UNORM;
 488             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 489             break;
 490     case MESA_FORMAT_X8_Z24:
 491     case MESA_FORMAT_S8_Z24:
 492             format = COLOR_8_24;
 493             comp_swap = SWAP_STD;
 494             number_type = NUMBER_UNORM;
 495             SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
 496                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 497             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 498             break;
 499     case MESA_FORMAT_Z24_S8:
 500             format = COLOR_24_8;
 501             comp_swap = SWAP_STD;
 502             number_type = NUMBER_UNORM;
 503             SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
 504                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 505             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 506             break;
 507     case MESA_FORMAT_Z16:
 508             format = COLOR_16;
 509             comp_swap = SWAP_STD;
 510             number_type = NUMBER_UNORM;
 511             SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
 512                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 513             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 514             break;
 515     case MESA_FORMAT_Z32:
 516             format = COLOR_32;
 517             comp_swap = SWAP_STD;
 518             number_type = NUMBER_UNORM;
 519             SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_1D_TILED_THIN1,
 520                      CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
 521             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 522             break;
 523     case MESA_FORMAT_SARGB8:
 524             format = COLOR_8_8_8_8;
 525             comp_swap = SWAP_ALT;
 526             number_type = NUMBER_SRGB;
 527             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 528             break;
 529     case MESA_FORMAT_SLA8:
 530             format = COLOR_8_8;
 531             comp_swap = SWAP_ALT_REV;
 532             number_type = NUMBER_SRGB;
 533             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 534             break;
 535     case MESA_FORMAT_SL8:
 536             format = COLOR_8;
 537             comp_swap = SWAP_ALT_REV;
 538             number_type = NUMBER_SRGB;
 539             SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
 540             break;
 541     default:
 542             _mesa_problem(context->radeon.glCtx, "unexpected format in r700SetRenderTarget()");
 543             break;
 544     }
 545
 546     /* must be 0 on r7xx */
 547     if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
 548             CLEARbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_FLOAT32_bit);
 549
 550     SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, format,
 551              CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
 552     SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, comp_swap,
 553              COMP_SWAP_shift, COMP_SWAP_mask);
 554     SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, number_type,
 555              NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 556     SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
 557
 558     r700->render_target[id].enabled = GL_TRUE;
 559 }
 560
 561 static void r700SetDepthTarget(context_t *context)
 562 {
 563     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 564
 565     struct radeon_renderbuffer *rrb;
 566     unsigned int nPitchInPixel, height;
 567
 568     rrb = radeon_get_depthbuffer(&context->radeon);
 569     if (!rrb)
 570             return;
 571
 572     R600_STATECHANGE(context, db_target);
 573
 574     /* depth buf */
 575     r700->DB_DEPTH_SIZE.u32All = 0;
 576     r700->DB_DEPTH_BASE.u32All = 0;
 577     r700->DB_DEPTH_INFO.u32All = 0;
 578     r700->DB_DEPTH_VIEW.u32All = 0;
 579
 580     nPitchInPixel = rrb->pitch/rrb->cpp;
 581
 582     if (context->radeon.radeonScreen->driScreen->dri2.enabled)
 583     {
 584         height = rrb->base.Height;
 585     }
 586     else
 587     {
 588         height =  context->radeon.radeonScreen->driScreen->fbHeight;
 589     }
 590
 591     SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
 592              PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
 593     SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * height)/64 )-1,
 594              SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
 595
 596     if(4 == rrb->cpp)
 597     {
 598         SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
 599                  DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
 600     }
 601     else
 602     {
 603         SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
 604                      DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
 605     }
 606     SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_1D_TILED_THIN1,
 607              DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
 608     /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
 609 }
 610
 611 static void r700SendDepthTargetState(struct gl_context *ctx, struct radeon_state_atom *atom)
 612 {
 613         context_t *context = R700_CONTEXT(ctx);
 614         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 615         struct radeon_renderbuffer *rrb;
 616         BATCH_LOCALS(&context->radeon);
 617         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 618
 619         rrb = radeon_get_depthbuffer(&context->radeon);
 620         if (!rrb || !rrb->bo) {
 621                 return;
 622         }
 623
 624         r700SetDepthTarget(context);
 625
 626         BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
 627         R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
 628         R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
 629         R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
 630         R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
 631         R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
 632         R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
 633                              rrb->bo,
 634                              r700->DB_DEPTH_BASE.u32All,
 635                              0, RADEON_GEM_DOMAIN_VRAM, 0);
 636         END_BATCH();
 637         BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 638         R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
 639         R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
 640         R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
 641                              rrb->bo,
 642                              r700->DB_DEPTH_INFO.u32All,
 643                              0, RADEON_GEM_DOMAIN_VRAM, 0);
 644         END_BATCH();
 645
 646         if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 647             (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 648                 BEGIN_BATCH_NO_AUTOSTATE(2);
 649                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
 650                 R600_OUT_BATCH(1 << 0);
 651                 END_BATCH();
 652         }
 653
 654         COMMIT_BATCH();
 655
 656 }
 657
 658 static void r700SendRenderTargetState(struct gl_context *ctx, struct radeon_state_atom *atom)
 659 {
 660         context_t *context = R700_CONTEXT(ctx);
 661         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 662         struct radeon_renderbuffer *rrb;
 663         BATCH_LOCALS(&context->radeon);
 664         int id = 0;
 665         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 666
 667         rrb = radeon_get_colorbuffer(&context->radeon);
 668         if (!rrb || !rrb->bo) {
 669                 return;
 670         }
 671
 672         r700SetRenderTarget(context, 0);
 673
 674         if (id > R700_MAX_RENDER_TARGETS)
 675                 return;
 676
 677         if (!r700->render_target[id].enabled)
 678                 return;
 679
 680         BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 681         R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
 682         R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_BASE.u32All);
 683         R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
 684                              rrb->bo,
 685                              r700->render_target[id].CB_COLOR0_BASE.u32All,
 686                              0, RADEON_GEM_DOMAIN_VRAM, 0);
 687         END_BATCH();
 688
 689         if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
 690             (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
 691                 BEGIN_BATCH_NO_AUTOSTATE(2);
 692                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
 693                 R600_OUT_BATCH((2 << id));
 694                 END_BATCH();
 695         }
 696         /* Set CMASK & TILE buffer to the offset of color buffer as
 697          * we don't use those this shouldn't cause any issue and we
 698          * then have a valid cmd stream
 699          */
 700         BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 701         R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
 702         R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
 703         R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
 704                              rrb->bo,
 705                              r700->render_target[id].CB_COLOR0_TILE.u32All,
 706                              0, RADEON_GEM_DOMAIN_VRAM, 0);
 707         END_BATCH();
 708         BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 709         R600_OUT_BATCH_REGSEQ(CB_COLOR0_FRAG + (4 * id), 1);
 710         R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_FRAG.u32All);
 711         R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_FRAG.u32All,
 712                              rrb->bo,
 713                              r700->render_target[id].CB_COLOR0_FRAG.u32All,
 714                              0, RADEON_GEM_DOMAIN_VRAM, 0);
 715         END_BATCH();
 716
 717         BEGIN_BATCH_NO_AUTOSTATE(9);
 718         R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All);
 719         R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All);
 720         R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
 721         END_BATCH();
 722
 723         BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 724         R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All);
 725         R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_INFO.u32All,
 726                              rrb->bo,
 727                              r700->render_target[id].CB_COLOR0_INFO.u32All,
 728                              0, RADEON_GEM_DOMAIN_VRAM, 0);
 729
 730         END_BATCH();
 731
 732         COMMIT_BATCH();
 733
 734 }
 735
 736 static void r700SendPSState(struct gl_context *ctx, struct radeon_state_atom *atom)
 737 {
 738     context_t *context = R700_CONTEXT(ctx);
 739     R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 740     struct radeon_bo * pbo;
 741     struct radeon_bo * pbo_const;
 742     BATCH_LOCALS(&context->radeon);
 743     radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 744
 745     pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
 746
 747     if (!pbo)
 748             return;
 749
 750     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 751
 752     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 753     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1);
 754     R600_OUT_BATCH(r700->ps.SQ_PGM_START_PS.u32All);
 755     R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
 756                          pbo,
 757                          r700->ps.SQ_PGM_START_PS.u32All,
 758                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 759     END_BATCH();
 760
 761     BEGIN_BATCH_NO_AUTOSTATE(9);
 762     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All);
 763     R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All);
 764     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All);
 765     END_BATCH();
 766
 767     BEGIN_BATCH_NO_AUTOSTATE(3);
 768     R600_OUT_BATCH_REGVAL(SQ_LOOP_CONST_0, 0x01000FFF);
 769     END_BATCH();
 770
 771     pbo_const = (struct radeon_bo *)r700GetActiveFpShaderConstBo(GL_CONTEXT(context));
 772     //TODO : set up shader const
 773
 774     COMMIT_BATCH();
 775
 776 }
 777
 778 static void r700SendVSState(struct gl_context *ctx, struct radeon_state_atom *atom)
 779 {
 780     context_t *context = R700_CONTEXT(ctx);
 781     R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 782     struct radeon_bo * pbo;
 783     struct radeon_bo * pbo_const;
 784     BATCH_LOCALS(&context->radeon);
 785     radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 786
 787     pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
 788
 789     if (!pbo)
 790         return;
 791
 792     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 793
 794     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 795     R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1);
 796     R600_OUT_BATCH(r700->vs.SQ_PGM_START_VS.u32All);
 797     R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
 798                          pbo,
 799                          r700->vs.SQ_PGM_START_VS.u32All,
 800                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 801     END_BATCH();
 802
 803     BEGIN_BATCH_NO_AUTOSTATE(6);
 804     R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All);
 805     R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All);
 806     END_BATCH();
 807
 808     BEGIN_BATCH_NO_AUTOSTATE(3);
 809     R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + 32*4), 0x0100000F);
 810     //R600_OUT_BATCH_REGVAL((SQ_LOOP_CONST_0 + (SQ_LOOP_CONST_vs<2)), 0x0100000F);
 811     END_BATCH();
 812
 813     /* TODO : handle 4 bufs */
 814     if(GL_TRUE == r700->bShaderUseMemConstant)
 815     {
 816             pbo_const = (struct radeon_bo *)r700GetActiveVpShaderConstBo(GL_CONTEXT(context));
 817         if(NULL != pbo_const)
 818         {
 819             r700SyncSurf(context, pbo_const, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit); /* TODO : Check kc bit. */
 820
 821             BEGIN_BATCH_NO_AUTOSTATE(3);
 822             R600_OUT_BATCH_REGVAL(SQ_ALU_CONST_BUFFER_SIZE_VS_0, (r700->vs.num_consts * 4)/16 );
 823             END_BATCH();
 824
 825             BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 826             R600_OUT_BATCH_REGSEQ(SQ_ALU_CONST_CACHE_VS_0, 1);
 827             R600_OUT_BATCH(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All);
 828             R600_OUT_BATCH_RELOC(r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
 829                          pbo_const,
 830                          r700->vs.SQ_ALU_CONST_CACHE_VS_0.u32All,
 831                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 832             END_BATCH();
 833         }
 834     }
 835
 836     COMMIT_BATCH();
 837 }
 838
 839 static void r700SendFSState(struct gl_context *ctx, struct radeon_state_atom *atom)
 840 {
 841         context_t *context = R700_CONTEXT(ctx);
 842         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 843         struct radeon_bo * pbo;
 844         BATCH_LOCALS(&context->radeon);
 845         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 846
 847         /* XXX fixme
 848          * R6xx chips require a FS be emitted, even if it's not used.
 849          * since we aren't using FS yet, just send the VS address to make
 850          * the kernel command checker happy
 851          */
 852         pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
 853         r700->fs.SQ_PGM_START_FS.u32All = r700->vs.SQ_PGM_START_VS.u32All;
 854         r700->fs.SQ_PGM_RESOURCES_FS.u32All = 0;
 855         r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
 856         /* XXX */
 857
 858         if (!pbo)
 859                 return;
 860
 861         r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 862
 863         BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 864         R600_OUT_BATCH_REGSEQ(SQ_PGM_START_FS, 1);
 865         R600_OUT_BATCH(r700->fs.SQ_PGM_START_FS.u32All);
 866         R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
 867                              pbo,
 868                              r700->fs.SQ_PGM_START_FS.u32All,
 869                              RADEON_GEM_DOMAIN_GTT, 0, 0);
 870         END_BATCH();
 871
 872         BEGIN_BATCH_NO_AUTOSTATE(6);
 873         R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_FS, r700->fs.SQ_PGM_RESOURCES_FS.u32All);
 874         R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_FS, r700->fs.SQ_PGM_CF_OFFSET_FS.u32All);
 875         END_BATCH();
 876
 877         COMMIT_BATCH();
 878
 879 }
 880
 881 static void r700SendViewportState(struct gl_context *ctx, struct radeon_state_atom *atom)
 882 {
 883         context_t *context = R700_CONTEXT(ctx);
 884         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 885         BATCH_LOCALS(&context->radeon);
 886         int id = 0;
 887         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 888
 889         if (id > R700_MAX_VIEWPORTS)
 890                 return;
 891
 892         if (!r700->viewport[id].enabled)
 893                 return;
 894
 895         BEGIN_BATCH_NO_AUTOSTATE(16);
 896         R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2);
 897         R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All);
 898         R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All);
 899         R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2);
 900         R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All);
 901         R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All);
 902         R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6);
 903         R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All);
 904         R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All);
 905         R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All);
 906         R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All);
 907         R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All);
 908         R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All);
 909         END_BATCH();
 910
 911         COMMIT_BATCH();
 912
 913 }
 914
 915 static void r700SendSQConfig(struct gl_context *ctx, struct radeon_state_atom *atom)
 916 {
 917         context_t *context = R700_CONTEXT(ctx);
 918         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 919         BATCH_LOCALS(&context->radeon);
 920         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 921
 922         BEGIN_BATCH_NO_AUTOSTATE(34);
 923         R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
 924         R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
 925         R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
 926         R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
 927         R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
 928         R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
 929         R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
 930
 931         R600_OUT_BATCH_REGVAL(TA_CNTL_AUX, r700->TA_CNTL_AUX.u32All);
 932         R600_OUT_BATCH_REGVAL(VC_ENHANCE, r700->VC_ENHANCE.u32All);
 933         R600_OUT_BATCH_REGVAL(R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All);
 934         R600_OUT_BATCH_REGVAL(DB_DEBUG, r700->DB_DEBUG.u32All);
 935         R600_OUT_BATCH_REGVAL(DB_WATERMARKS, r700->DB_WATERMARKS.u32All);
 936
 937         R600_OUT_BATCH_REGSEQ(SQ_ESGS_RING_ITEMSIZE, 9);
 938         R600_OUT_BATCH(r700->SQ_ESGS_RING_ITEMSIZE.u32All);
 939         R600_OUT_BATCH(r700->SQ_GSVS_RING_ITEMSIZE.u32All);
 940         R600_OUT_BATCH(r700->SQ_ESTMP_RING_ITEMSIZE.u32All);
 941         R600_OUT_BATCH(r700->SQ_GSTMP_RING_ITEMSIZE.u32All);
 942         R600_OUT_BATCH(r700->SQ_VSTMP_RING_ITEMSIZE.u32All);
 943         R600_OUT_BATCH(r700->SQ_PSTMP_RING_ITEMSIZE.u32All);
 944         R600_OUT_BATCH(r700->SQ_FBUF_RING_ITEMSIZE.u32All);
 945         R600_OUT_BATCH(r700->SQ_REDUC_RING_ITEMSIZE.u32All);
 946         R600_OUT_BATCH(r700->SQ_GS_VERT_ITEMSIZE.u32All);
 947         END_BATCH();
 948
 949         COMMIT_BATCH();
 950 }
 951
 952 static void r700SendUCPState(struct gl_context *ctx, struct radeon_state_atom *atom)
 953 {
 954         context_t *context = R700_CONTEXT(ctx);
 955         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 956         BATCH_LOCALS(&context->radeon);
 957         int i;
 958         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 959
 960         for (i = 0; i < R700_MAX_UCP; i++) {
 961                 if (r700->ucp[i].enabled) {
 962                         BEGIN_BATCH_NO_AUTOSTATE(6);
 963                         R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
 964                         R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
 965                         R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
 966                         R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
 967                         R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
 968                         END_BATCH();
 969                         COMMIT_BATCH();
 970                 }
 971         }
 972 }
 973
 974 static void r700SendSPIState(struct gl_context *ctx, struct radeon_state_atom *atom)
 975 {
 976         context_t *context = R700_CONTEXT(ctx);
 977         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 978         BATCH_LOCALS(&context->radeon);
 979         unsigned int ui;
 980         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
 981
 982         BEGIN_BATCH_NO_AUTOSTATE(59 + R700_MAX_SHADER_EXPORTS);
 983
 984         R600_OUT_BATCH_REGSEQ(SQ_VTX_SEMANTIC_0, 32);
 985         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_0.u32All);
 986         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_1.u32All);
 987         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_2.u32All);
 988         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_3.u32All);
 989         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_4.u32All);
 990         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_5.u32All);
 991         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_6.u32All);
 992         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_7.u32All);
 993         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_8.u32All);
 994         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_9.u32All);
 995         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_10.u32All);
 996         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_11.u32All);
 997         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_12.u32All);
 998         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_13.u32All);
 999         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_14.u32All);
1000         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_15.u32All);
1001         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_16.u32All);
1002         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_17.u32All);
1003         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_18.u32All);
1004         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_19.u32All);
1005         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_20.u32All);
1006         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_21.u32All);
1007         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_22.u32All);
1008         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_23.u32All);
1009         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_24.u32All);
1010         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_25.u32All);
1011         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_26.u32All);
1012         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_27.u32All);
1013         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_28.u32All);
1014         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_29.u32All);
1015         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_30.u32All);
1016         R600_OUT_BATCH(r700->SQ_VTX_SEMANTIC_31.u32All);
1017
1018         R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_ID_0, 10);
1019         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_0.u32All);
1020         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_1.u32All);
1021         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_2.u32All);
1022         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_3.u32All);
1023         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_4.u32All);
1024         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_5.u32All);
1025         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_6.u32All);
1026         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_7.u32All);
1027         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_8.u32All);
1028         R600_OUT_BATCH(r700->SPI_VS_OUT_ID_9.u32All);
1029
1030         R600_OUT_BATCH_REGSEQ(SPI_VS_OUT_CONFIG, 9);
1031         R600_OUT_BATCH(r700->SPI_VS_OUT_CONFIG.u32All);
1032         R600_OUT_BATCH(r700->SPI_THREAD_GROUPING.u32All);
1033         R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_0.u32All);
1034         R600_OUT_BATCH(r700->SPI_PS_IN_CONTROL_1.u32All);
1035         R600_OUT_BATCH(r700->SPI_INTERP_CONTROL_0.u32All);
1036         R600_OUT_BATCH(r700->SPI_INPUT_Z.u32All);
1037         R600_OUT_BATCH(r700->SPI_FOG_CNTL.u32All);
1038         R600_OUT_BATCH(r700->SPI_FOG_FUNC_SCALE.u32All);
1039         R600_OUT_BATCH(r700->SPI_FOG_FUNC_BIAS.u32All);
1040
1041         R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
1042         for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
1043                 R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
1044
1045         END_BATCH();
1046         COMMIT_BATCH();
1047 }
1048
1049 static void r700SendVGTState(struct gl_context *ctx, struct radeon_state_atom *atom)
1050 {
1051         context_t *context = R700_CONTEXT(ctx);
1052         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1053         BATCH_LOCALS(&context->radeon);
1054         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1055
1056         BEGIN_BATCH_NO_AUTOSTATE(41);
1057
1058         R600_OUT_BATCH_REGSEQ(VGT_MAX_VTX_INDX, 4);
1059         R600_OUT_BATCH(r700->VGT_MAX_VTX_INDX.u32All);
1060         R600_OUT_BATCH(r700->VGT_MIN_VTX_INDX.u32All);
1061         R600_OUT_BATCH(r700->VGT_INDX_OFFSET.u32All);
1062         R600_OUT_BATCH(r700->VGT_MULTI_PRIM_IB_RESET_INDX.u32All);
1063
1064         R600_OUT_BATCH_REGSEQ(VGT_OUTPUT_PATH_CNTL, 13);
1065         R600_OUT_BATCH(r700->VGT_OUTPUT_PATH_CNTL.u32All);
1066         R600_OUT_BATCH(r700->VGT_HOS_CNTL.u32All);
1067         R600_OUT_BATCH(r700->VGT_HOS_MAX_TESS_LEVEL.u32All);
1068         R600_OUT_BATCH(r700->VGT_HOS_MIN_TESS_LEVEL.u32All);
1069         R600_OUT_BATCH(r700->VGT_HOS_REUSE_DEPTH.u32All);
1070         R600_OUT_BATCH(r700->VGT_GROUP_PRIM_TYPE.u32All);
1071         R600_OUT_BATCH(r700->VGT_GROUP_FIRST_DECR.u32All);
1072         R600_OUT_BATCH(r700->VGT_GROUP_DECR.u32All);
1073         R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_CNTL.u32All);
1074         R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_CNTL.u32All);
1075         R600_OUT_BATCH(r700->VGT_GROUP_VECT_0_FMT_CNTL.u32All);
1076         R600_OUT_BATCH(r700->VGT_GROUP_VECT_1_FMT_CNTL.u32All);
1077         R600_OUT_BATCH(r700->VGT_GS_MODE.u32All);
1078
1079         R600_OUT_BATCH_REGVAL(VGT_PRIMITIVEID_EN, r700->VGT_PRIMITIVEID_EN.u32All);
1080         R600_OUT_BATCH_REGVAL(VGT_MULTI_PRIM_IB_RESET_EN, r700->VGT_MULTI_PRIM_IB_RESET_EN.u32All);
1081         R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_0, r700->VGT_INSTANCE_STEP_RATE_0.u32All);
1082         R600_OUT_BATCH_REGVAL(VGT_INSTANCE_STEP_RATE_1, r700->VGT_INSTANCE_STEP_RATE_1.u32All);
1083
1084         R600_OUT_BATCH_REGSEQ(VGT_STRMOUT_EN, 3);
1085         R600_OUT_BATCH(r700->VGT_STRMOUT_EN.u32All);
1086         R600_OUT_BATCH(r700->VGT_REUSE_OFF.u32All);
1087         R600_OUT_BATCH(r700->VGT_VTX_CNT_EN.u32All);
1088
1089         R600_OUT_BATCH_REGVAL(VGT_STRMOUT_BUFFER_EN, r700->VGT_STRMOUT_BUFFER_EN.u32All);
1090
1091         END_BATCH();
1092         COMMIT_BATCH();
1093 }
1094
1095 static void r700SendSXState(struct gl_context *ctx, struct radeon_state_atom *atom)
1096 {
1097         context_t *context = R700_CONTEXT(ctx);
1098         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1099         BATCH_LOCALS(&context->radeon);
1100         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1101
1102         BEGIN_BATCH_NO_AUTOSTATE(9);
1103         R600_OUT_BATCH_REGVAL(SX_MISC, r700->SX_MISC.u32All);
1104         R600_OUT_BATCH_REGVAL(SX_ALPHA_TEST_CONTROL, r700->SX_ALPHA_TEST_CONTROL.u32All);
1105         R600_OUT_BATCH_REGVAL(SX_ALPHA_REF, r700->SX_ALPHA_REF.u32All);
1106         END_BATCH();
1107         COMMIT_BATCH();
1108 }
1109
1110 static void r700SendDBState(struct gl_context *ctx, struct radeon_state_atom *atom)
1111 {
1112         context_t *context = R700_CONTEXT(ctx);
1113         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1114         BATCH_LOCALS(&context->radeon);
1115         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1116
1117         BEGIN_BATCH_NO_AUTOSTATE(17);
1118
1119         R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
1120         R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
1121         R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
1122
1123         R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
1124         R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
1125
1126         R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
1127         R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
1128         R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
1129
1130         R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
1131
1132         END_BATCH();
1133         COMMIT_BATCH();
1134 }
1135
1136 static void r700SendStencilState(struct gl_context *ctx, struct radeon_state_atom *atom)
1137 {
1138         context_t *context = R700_CONTEXT(ctx);
1139         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1140         BATCH_LOCALS(&context->radeon);
1141
1142         BEGIN_BATCH_NO_AUTOSTATE(4);
1143         R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
1144         R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
1145         R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
1146         END_BATCH();
1147         COMMIT_BATCH();
1148 }
1149
1150 static void r700SendCBState(struct gl_context *ctx, struct radeon_state_atom *atom)
1151 {
1152         context_t *context = R700_CONTEXT(ctx);
1153         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1154         BATCH_LOCALS(&context->radeon);
1155         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1156
1157         if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1158                 BEGIN_BATCH_NO_AUTOSTATE(11);
1159                 R600_OUT_BATCH_REGSEQ(CB_CLEAR_RED, 4);
1160                 R600_OUT_BATCH(r700->CB_CLEAR_RED_R6XX.u32All);
1161                 R600_OUT_BATCH(r700->CB_CLEAR_GREEN_R6XX.u32All);
1162                 R600_OUT_BATCH(r700->CB_CLEAR_BLUE_R6XX.u32All);
1163                 R600_OUT_BATCH(r700->CB_CLEAR_ALPHA_R6XX.u32All);
1164                 R600_OUT_BATCH_REGSEQ(CB_FOG_RED, 3);
1165                 R600_OUT_BATCH(r700->CB_FOG_RED_R6XX.u32All);
1166                 R600_OUT_BATCH(r700->CB_FOG_GREEN_R6XX.u32All);
1167                 R600_OUT_BATCH(r700->CB_FOG_BLUE_R6XX.u32All);
1168                 END_BATCH();
1169         }
1170
1171         BEGIN_BATCH_NO_AUTOSTATE(7);
1172         R600_OUT_BATCH_REGSEQ(CB_TARGET_MASK, 2);
1173         R600_OUT_BATCH(r700->CB_TARGET_MASK.u32All);
1174         R600_OUT_BATCH(r700->CB_SHADER_MASK.u32All);
1175         R600_OUT_BATCH_REGVAL(R7xx_CB_SHADER_CONTROL, r700->CB_SHADER_CONTROL.u32All);
1176         END_BATCH();
1177         COMMIT_BATCH();
1178 }
1179
1180 static void r700SendCBCLRCMPState(struct gl_context *ctx, struct radeon_state_atom *atom)
1181 {
1182         context_t *context = R700_CONTEXT(ctx);
1183         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1184         BATCH_LOCALS(&context->radeon);
1185
1186         BEGIN_BATCH_NO_AUTOSTATE(6);
1187         R600_OUT_BATCH_REGSEQ(CB_CLRCMP_CONTROL, 4);
1188         R600_OUT_BATCH(r700->CB_CLRCMP_CONTROL.u32All);
1189         R600_OUT_BATCH(r700->CB_CLRCMP_SRC.u32All);
1190         R600_OUT_BATCH(r700->CB_CLRCMP_DST.u32All);
1191         R600_OUT_BATCH(r700->CB_CLRCMP_MSK.u32All);
1192         END_BATCH();
1193         COMMIT_BATCH();
1194 }
1195
1196 static void r700SendCBBlendState(struct gl_context *ctx, struct radeon_state_atom *atom)
1197 {
1198         context_t *context = R700_CONTEXT(ctx);
1199         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1200         BATCH_LOCALS(&context->radeon);
1201         unsigned int ui;
1202         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1203
1204         if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
1205                 BEGIN_BATCH_NO_AUTOSTATE(3);
1206                 R600_OUT_BATCH_REGVAL(CB_BLEND_CONTROL, r700->CB_BLEND_CONTROL.u32All);
1207                 END_BATCH();
1208         }
1209
1210         BEGIN_BATCH_NO_AUTOSTATE(3);
1211         R600_OUT_BATCH_REGVAL(CB_COLOR_CONTROL, r700->CB_COLOR_CONTROL.u32All);
1212         END_BATCH();
1213
1214         if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1215                 for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
1216                         if (r700->render_target[ui].enabled) {
1217                                 BEGIN_BATCH_NO_AUTOSTATE(3);
1218                                 R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
1219                                                       r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
1220                                 END_BATCH();
1221                         }
1222                 }
1223         }
1224
1225         COMMIT_BATCH();
1226 }
1227
1228 static void r700SendCBBlendColorState(struct gl_context *ctx, struct radeon_state_atom *atom)
1229 {
1230         context_t *context = R700_CONTEXT(ctx);
1231         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1232         BATCH_LOCALS(&context->radeon);
1233         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1234
1235         BEGIN_BATCH_NO_AUTOSTATE(6);
1236         R600_OUT_BATCH_REGSEQ(CB_BLEND_RED, 4);
1237         R600_OUT_BATCH(r700->CB_BLEND_RED.u32All);
1238         R600_OUT_BATCH(r700->CB_BLEND_GREEN.u32All);
1239         R600_OUT_BATCH(r700->CB_BLEND_BLUE.u32All);
1240         R600_OUT_BATCH(r700->CB_BLEND_ALPHA.u32All);
1241         END_BATCH();
1242         COMMIT_BATCH();
1243 }
1244
1245 static void r700SendSUState(struct gl_context *ctx, struct radeon_state_atom *atom)
1246 {
1247         context_t *context = R700_CONTEXT(ctx);
1248         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1249         BATCH_LOCALS(&context->radeon);
1250
1251         BEGIN_BATCH_NO_AUTOSTATE(9);
1252         R600_OUT_BATCH_REGVAL(PA_SU_SC_MODE_CNTL, r700->PA_SU_SC_MODE_CNTL.u32All);
1253         R600_OUT_BATCH_REGSEQ(PA_SU_POINT_SIZE, 4);
1254         R600_OUT_BATCH(r700->PA_SU_POINT_SIZE.u32All);
1255         R600_OUT_BATCH(r700->PA_SU_POINT_MINMAX.u32All);
1256         R600_OUT_BATCH(r700->PA_SU_LINE_CNTL.u32All);
1257         R600_OUT_BATCH(r700->PA_SU_VTX_CNTL.u32All);
1258         END_BATCH();
1259         COMMIT_BATCH();
1260
1261 }
1262
1263 static void r700SendPolyState(struct gl_context *ctx, struct radeon_state_atom *atom)
1264 {
1265         context_t *context = R700_CONTEXT(ctx);
1266         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1267         BATCH_LOCALS(&context->radeon);
1268
1269         BEGIN_BATCH_NO_AUTOSTATE(10);
1270         R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2);
1271         R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_DB_FMT_CNTL.u32All);
1272         R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_CLAMP.u32All);
1273         R600_OUT_BATCH_REGSEQ(PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
1274         R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_SCALE.u32All);
1275         R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.u32All);
1276         R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_SCALE.u32All);
1277         R600_OUT_BATCH(r700->PA_SU_POLY_OFFSET_BACK_OFFSET.u32All);
1278         END_BATCH();
1279         COMMIT_BATCH();
1280
1281 }
1282
1283 static void r700SendCLState(struct gl_context *ctx, struct radeon_state_atom *atom)
1284 {
1285         context_t *context = R700_CONTEXT(ctx);
1286         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1287         BATCH_LOCALS(&context->radeon);
1288         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1289
1290         BEGIN_BATCH_NO_AUTOSTATE(12);
1291         R600_OUT_BATCH_REGVAL(PA_CL_CLIP_CNTL, r700->PA_CL_CLIP_CNTL.u32All);
1292         R600_OUT_BATCH_REGVAL(PA_CL_VTE_CNTL, r700->PA_CL_VTE_CNTL.u32All);
1293         R600_OUT_BATCH_REGVAL(PA_CL_VS_OUT_CNTL, r700->PA_CL_VS_OUT_CNTL.u32All);
1294         R600_OUT_BATCH_REGVAL(PA_CL_NANINF_CNTL, r700->PA_CL_NANINF_CNTL.u32All);
1295         END_BATCH();
1296         COMMIT_BATCH();
1297 }
1298
1299 static void r700SendGBState(struct gl_context *ctx, struct radeon_state_atom *atom)
1300 {
1301         context_t *context = R700_CONTEXT(ctx);
1302         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1303         BATCH_LOCALS(&context->radeon);
1304
1305         BEGIN_BATCH_NO_AUTOSTATE(6);
1306         R600_OUT_BATCH_REGSEQ(PA_CL_GB_VERT_CLIP_ADJ, 4);
1307         R600_OUT_BATCH(r700->PA_CL_GB_VERT_CLIP_ADJ.u32All);
1308         R600_OUT_BATCH(r700->PA_CL_GB_VERT_DISC_ADJ.u32All);
1309         R600_OUT_BATCH(r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All);
1310         R600_OUT_BATCH(r700->PA_CL_GB_HORZ_DISC_ADJ.u32All);
1311         END_BATCH();
1312         COMMIT_BATCH();
1313 }
1314
1315 static void r700SendScissorState(struct gl_context *ctx, struct radeon_state_atom *atom)
1316 {
1317         context_t *context = R700_CONTEXT(ctx);
1318         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1319         BATCH_LOCALS(&context->radeon);
1320         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1321
1322         BEGIN_BATCH_NO_AUTOSTATE(22);
1323         R600_OUT_BATCH_REGSEQ(PA_SC_SCREEN_SCISSOR_TL, 2);
1324         R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_TL.u32All);
1325         R600_OUT_BATCH(r700->PA_SC_SCREEN_SCISSOR_BR.u32All);
1326
1327         R600_OUT_BATCH_REGSEQ(PA_SC_WINDOW_OFFSET, 12);
1328         R600_OUT_BATCH(r700->PA_SC_WINDOW_OFFSET.u32All);
1329         R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_TL.u32All);
1330         R600_OUT_BATCH(r700->PA_SC_WINDOW_SCISSOR_BR.u32All);
1331         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_RULE.u32All);
1332         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_TL.u32All);
1333         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_0_BR.u32All);
1334         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_TL.u32All);
1335         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_1_BR.u32All);
1336         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_TL.u32All);
1337         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_2_BR.u32All);
1338         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_TL.u32All);
1339         R600_OUT_BATCH(r700->PA_SC_CLIPRECT_3_BR.u32All);
1340
1341         R600_OUT_BATCH_REGSEQ(PA_SC_GENERIC_SCISSOR_TL, 2);
1342         R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_TL.u32All);
1343         R600_OUT_BATCH(r700->PA_SC_GENERIC_SCISSOR_BR.u32All);
1344         END_BATCH();
1345         COMMIT_BATCH();
1346 }
1347
1348 static void r700SendSCState(struct gl_context *ctx, struct radeon_state_atom *atom)
1349 {
1350         context_t *context = R700_CONTEXT(ctx);
1351         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1352         BATCH_LOCALS(&context->radeon);
1353         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1354
1355         BEGIN_BATCH_NO_AUTOSTATE(15);
1356         R600_OUT_BATCH_REGVAL(R7xx_PA_SC_EDGERULE, r700->PA_SC_EDGERULE.u32All);
1357         R600_OUT_BATCH_REGVAL(PA_SC_LINE_STIPPLE, r700->PA_SC_LINE_STIPPLE.u32All);
1358         R600_OUT_BATCH_REGVAL(PA_SC_MPASS_PS_CNTL, r700->PA_SC_MPASS_PS_CNTL.u32All);
1359         R600_OUT_BATCH_REGVAL(PA_SC_MODE_CNTL, r700->PA_SC_MODE_CNTL.u32All);
1360         R600_OUT_BATCH_REGVAL(PA_SC_LINE_CNTL, r700->PA_SC_LINE_CNTL.u32All);
1361         END_BATCH();
1362         COMMIT_BATCH();
1363 }
1364
1365 static void r700SendAAState(struct gl_context *ctx, struct radeon_state_atom *atom)
1366 {
1367         context_t *context = R700_CONTEXT(ctx);
1368         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1369         BATCH_LOCALS(&context->radeon);
1370
1371         BEGIN_BATCH_NO_AUTOSTATE(12);
1372         R600_OUT_BATCH_REGVAL(PA_SC_AA_CONFIG, r700->PA_SC_AA_CONFIG.u32All);
1373         R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_MCTX.u32All);
1374         R600_OUT_BATCH_REGVAL(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, r700->PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX.u32All);
1375         R600_OUT_BATCH_REGVAL(PA_SC_AA_MASK, r700->PA_SC_AA_MASK.u32All);
1376         END_BATCH();
1377         COMMIT_BATCH();
1378 }
1379
1380 static void r700SendPSConsts(struct gl_context *ctx, struct radeon_state_atom *atom)
1381 {
1382         context_t *context = R700_CONTEXT(ctx);
1383         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1384         int i;
1385         BATCH_LOCALS(&context->radeon);
1386
1387         if (r700->ps.num_consts == 0)
1388                 return;
1389
1390         BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->ps.num_consts * 4));
1391         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->ps.num_consts * 4)));
1392         /* assembler map const from very beginning. */
1393         R600_OUT_BATCH(SQ_ALU_CONSTANT_PS_OFFSET * 4);
1394         for (i = 0; i < r700->ps.num_consts; i++) {
1395                 R600_OUT_BATCH(r700->ps.consts[i][0].u32All);
1396                 R600_OUT_BATCH(r700->ps.consts[i][1].u32All);
1397                 R600_OUT_BATCH(r700->ps.consts[i][2].u32All);
1398                 R600_OUT_BATCH(r700->ps.consts[i][3].u32All);
1399         }
1400         END_BATCH();
1401         COMMIT_BATCH();
1402 }
1403
1404 static void r700SendVSConsts(struct gl_context *ctx, struct radeon_state_atom *atom)
1405 {
1406         context_t *context = R700_CONTEXT(ctx);
1407         R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
1408         int i;
1409         BATCH_LOCALS(&context->radeon);
1410         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1411
1412         if (r700->vs.num_consts == 0)
1413                 return;
1414
1415         BEGIN_BATCH_NO_AUTOSTATE(2 + (r700->vs.num_consts * 4));
1416         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (r700->vs.num_consts * 4)));
1417         /* assembler map const from very beginning. */
1418         R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
1419         for (i = 0; i < r700->vs.num_consts; i++) {
1420                 R600_OUT_BATCH(r700->vs.consts[i][0].u32All);
1421                 R600_OUT_BATCH(r700->vs.consts[i][1].u32All);
1422                 R600_OUT_BATCH(r700->vs.consts[i][2].u32All);
1423                 R600_OUT_BATCH(r700->vs.consts[i][3].u32All);
1424         }
1425         END_BATCH();
1426         COMMIT_BATCH();
1427 }
1428
1429 static void r700SendQueryBegin(struct gl_context *ctx, struct radeon_state_atom *atom)
1430 {
1431         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1432         struct radeon_query_object *query = radeon->query.current;
1433         BATCH_LOCALS(radeon);
1434         radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__);
1435
1436         /* clear the buffer */
1437         radeon_bo_map(query->bo, GL_FALSE);
1438         memset(query->bo->ptr, 0, 4 * 2 * sizeof(uint64_t)); /* 4 DBs, 2 qwords each */
1439         radeon_bo_unmap(query->bo);
1440
1441         radeon_cs_space_check_with_bo(radeon->cmdbuf.cs,
1442                                       query->bo,
1443                                       0, RADEON_GEM_DOMAIN_GTT);
1444
1445         BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
1446         R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
1447         R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
1448         R600_OUT_BATCH(query->curr_offset); /* hw writes qwords */
1449         R600_OUT_BATCH(0x00000000);
1450         R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
1451         END_BATCH();
1452         query->emitted_begin = GL_TRUE;
1453 }
1454
1455 static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
1456 {
1457         return atom->cmd_size;
1458 }
1459
1460 static int check_cb(struct gl_context *ctx, struct radeon_state_atom *atom)
1461 {
1462         context_t *context = R700_CONTEXT(ctx);
1463         int count = 7;
1464
1465         if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1466                 count += 11;
1467         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1468
1469         return count;
1470 }
1471
1472 static int check_blnd(struct gl_context *ctx, struct radeon_state_atom *atom)
1473 {
1474         context_t *context = R700_CONTEXT(ctx);
1475         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1476         unsigned int ui;
1477         int count = 3;
1478
1479         if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
1480                 count += 3;
1481
1482         if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
1483                 /* targets are enabled in r700SetRenderTarget but state
1484                    size is calculated before that. Until MRT's are done
1485                    hardcode target0 as enabled. */
1486                 count += 3;
1487                 for (ui = 1; ui < R700_MAX_RENDER_TARGETS; ui++) {
1488                         if (r700->render_target[ui].enabled)
1489                                 count += 3;
1490                 }
1491         }
1492         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1493
1494         return count;
1495 }
1496
1497 static int check_ucp(struct gl_context *ctx, struct radeon_state_atom *atom)
1498 {
1499         context_t *context = R700_CONTEXT(ctx);
1500         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1501         int i;
1502         int count = 0;
1503
1504         for (i = 0; i < R700_MAX_UCP; i++) {
1505                 if (r700->ucp[i].enabled)
1506                         count += 6;
1507         }
1508         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1509         return count;
1510 }
1511
1512 static int check_vtx(struct gl_context *ctx, struct radeon_state_atom *atom)
1513 {
1514         context_t *context = R700_CONTEXT(ctx);
1515         int count = context->radeon.tcl.aos_count * 18;
1516
1517         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1518         return count;
1519 }
1520
1521 static int check_tx(struct gl_context *ctx, struct radeon_state_atom *atom)
1522 {
1523         context_t *context = R700_CONTEXT(ctx);
1524         unsigned int i, count = 0;
1525         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1526
1527         for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
1528                 if (ctx->Texture.Unit[i]._ReallyEnabled) {
1529                         radeonTexObj *t = r700->textures[i];
1530                         if (t)
1531                                 count++;
1532                 }
1533         }
1534         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1535         return count * 31;
1536 }
1537
1538 static int check_ps_consts(struct gl_context *ctx, struct radeon_state_atom *atom)
1539 {
1540         context_t *context = R700_CONTEXT(ctx);
1541         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1542         int count = r700->ps.num_consts * 4;
1543
1544         if (count)
1545                 count += 2;
1546         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1547
1548         return count;
1549 }
1550
1551 static int check_vs_consts(struct gl_context *ctx, struct radeon_state_atom *atom)
1552 {
1553         context_t *context = R700_CONTEXT(ctx);
1554         R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
1555         int count = r700->vs.num_consts * 4;
1556
1557         if (count)
1558                 count += 2;
1559         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1560
1561         return count;
1562 }
1563
1564 static int check_queryobj(struct gl_context *ctx, struct radeon_state_atom *atom)
1565 {
1566         radeonContextPtr radeon = RADEON_CONTEXT(ctx);
1567         struct radeon_query_object *query = radeon->query.current;
1568         int count;
1569
1570         if (!query || query->emitted_begin)
1571                 count = 0;
1572         else
1573                 count = atom->cmd_size;
1574         radeon_print(RADEON_STATE, RADEON_TRACE, "%s %d\n", __func__, count);
1575         return count;
1576 }
1577
1578 #define ALLOC_STATE( ATOM, CHK, SZ, EMIT )                              \
1579 do {                                                                    \
1580         context->atoms.ATOM.cmd_size = (SZ);                            \
1581         context->atoms.ATOM.cmd = NULL;                                 \
1582         context->atoms.ATOM.name = #ATOM;                               \
1583         context->atoms.ATOM.idx = 0;                                    \
1584         context->atoms.ATOM.check = check_##CHK;                        \
1585         context->atoms.ATOM.dirty = GL_FALSE;                           \
1586         context->atoms.ATOM.emit = (EMIT);                              \
1587         context->radeon.hw.max_state_size += (SZ);                      \
1588         insert_at_tail(&context->radeon.hw.atomlist, &context->atoms.ATOM); \
1589 } while (0)
1590
1591 static void r600_init_query_stateobj(radeonContextPtr radeon, int SZ)
1592 {
1593         radeon->query.queryobj.cmd_size = (SZ);
1594         radeon->query.queryobj.cmd = NULL;
1595         radeon->query.queryobj.name = "queryobj";
1596         radeon->query.queryobj.idx = 0;
1597         radeon->query.queryobj.check = check_queryobj;
1598         radeon->query.queryobj.dirty = GL_FALSE;
1599         radeon->query.queryobj.emit = r700SendQueryBegin;
1600         radeon->hw.max_state_size += (SZ);
1601         insert_at_tail(&radeon->hw.atomlist, &radeon->query.queryobj);
1602 }
1603
1604 void r600InitAtoms(context_t *context)
1605 {
1606     R700_CHIP_CONTEXT *r700    = (R700_CHIP_CONTEXT*)(&context->hw);
1607     radeon_print(RADEON_STATE, RADEON_NORMAL, "%s %p\n", __func__, context);
1608     context->radeon.hw.max_state_size = 10 + 5 + 14; /* start 3d, idle, cb/db flush */
1609
1610     /* Setup the atom linked list */
1611     make_empty_list(&context->radeon.hw.atomlist);
1612     context->radeon.hw.atomlist.name = "atom-list";
1613
1614     ALLOC_STATE(sq, always, 34, r700SendSQConfig);
1615     ALLOC_STATE(db, always, 17, r700SendDBState);
1616     ALLOC_STATE(stencil, always, 4, r700SendStencilState);
1617     ALLOC_STATE(db_target, always, 16, r700SendDepthTargetState);
1618     ALLOC_STATE(sc, always, 15, r700SendSCState);
1619     ALLOC_STATE(scissor, always, 22, r700SendScissorState);
1620     ALLOC_STATE(aa, always, 12, r700SendAAState);
1621     ALLOC_STATE(cl, always, 12, r700SendCLState);
1622     ALLOC_STATE(gb, always, 6, r700SendGBState);
1623     ALLOC_STATE(ucp, ucp, (R700_MAX_UCP * 6), r700SendUCPState);
1624     ALLOC_STATE(su, always, 9, r700SendSUState);
1625     ALLOC_STATE(poly, always, 10, r700SendPolyState);
1626     ALLOC_STATE(cb, cb, 18, r700SendCBState);
1627     ALLOC_STATE(clrcmp, always, 6, r700SendCBCLRCMPState);
1628     ALLOC_STATE(cb_target, always, 31, r700SendRenderTargetState);
1629     ALLOC_STATE(blnd, blnd, (6 + (R700_MAX_RENDER_TARGETS * 3)), r700SendCBBlendState);
1630     ALLOC_STATE(blnd_clr, always, 6, r700SendCBBlendColorState);
1631     ALLOC_STATE(sx, always, 9, r700SendSXState);
1632     ALLOC_STATE(vgt, always, 41, r700SendVGTState);
1633     ALLOC_STATE(spi, always, (59 + R700_MAX_SHADER_EXPORTS), r700SendSPIState);
1634     ALLOC_STATE(vpt, always, 16, r700SendViewportState);
1635     ALLOC_STATE(fs, always, 18, r700SendFSState);
1636     if(GL_TRUE == r700->bShaderUseMemConstant)
1637     {
1638         ALLOC_STATE(vs, always, 36, r700SendVSState);
1639             ALLOC_STATE(ps, always, 24, r700SendPSState); /* TODO : not imp yet, fix later. */
1640     }
1641     else
1642     {
1643         ALLOC_STATE(vs, always, 21, r700SendVSState);
1644         ALLOC_STATE(ps, always, 24, r700SendPSState);
1645         ALLOC_STATE(vs_consts, vs_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendVSConsts);
1646         ALLOC_STATE(ps_consts, ps_consts, (2 + (R700_MAX_DX9_CONSTS * 4)), r700SendPSConsts);
1647     }
1648
1649     ALLOC_STATE(vtx, vtx, (VERT_ATTRIB_MAX * 18), r700SendVTXState);
1650     ALLOC_STATE(tx, tx, (R700_TEXTURE_NUMBERUNITS * 20), r700SendTexState);
1651     ALLOC_STATE(tx_smplr, tx, (R700_TEXTURE_NUMBERUNITS * 5), r700SendTexSamplerState);
1652     ALLOC_STATE(tx_brdr_clr, tx, (R700_TEXTURE_NUMBERUNITS * 6), r700SendTexBorderColorState);
1653     r600_init_query_stateobj(&context->radeon, 6 * 2);
1654
1655     context->radeon.hw.is_dirty = GL_TRUE;
1656     context->radeon.hw.all_dirty = GL_TRUE;
1657 }