src/mesa/drivers/dri/r600/r600_reg_r6xx.h

   1 /*
   2  * RadeonHD R6xx, R7xx Register documentation
   3  *
   4  * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
   5  * Copyright (C) 2008-2009  Matthias Hopf
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  21  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef _R600_REG_R6xx_H_
  26 #define _R600_REG_R6xx_H_
  27
  28 /*
  29  * Registers for R6xx chips that are not documented yet
  30  */
  31
  32 enum {
  33
  34     MM_INDEX                                              = 0x0000,
  35     MM_DATA                                               = 0x0004,
  36
  37     SRBM_STATUS                                           = 0x0e50,
  38         RLC_RQ_PENDING_bit                                = 1 << 3,
  39         RCU_RQ_PENDING_bit                                = 1 << 4,
  40         GRBM_RQ_PENDING_bit                               = 1 << 5,
  41         HI_RQ_PENDING_bit                                 = 1 << 6,
  42         IO_EXTERN_SIGNAL_bit                              = 1 << 7,
  43         VMC_BUSY_bit                                      = 1 << 8,
  44         MCB_BUSY_bit                                      = 1 << 9,
  45         MCDZ_BUSY_bit                                     = 1 << 10,
  46         MCDY_BUSY_bit                                     = 1 << 11,
  47         MCDX_BUSY_bit                                     = 1 << 12,
  48         MCDW_BUSY_bit                                     = 1 << 13,
  49         SEM_BUSY_bit                                      = 1 << 14,
  50         SRBM_STATUS__RLC_BUSY_bit                         = 1 << 15,
  51         PDMA_BUSY_bit                                     = 1 << 16,
  52         IH_BUSY_bit                                       = 1 << 17,
  53         CSC_BUSY_bit                                      = 1 << 20,
  54         CMC7_BUSY_bit                                     = 1 << 21,
  55         CMC6_BUSY_bit                                     = 1 << 22,
  56         CMC5_BUSY_bit                                     = 1 << 23,
  57         CMC4_BUSY_bit                                     = 1 << 24,
  58         CMC3_BUSY_bit                                     = 1 << 25,
  59         CMC2_BUSY_bit                                     = 1 << 26,
  60         CMC1_BUSY_bit                                     = 1 << 27,
  61         CMC0_BUSY_bit                                     = 1 << 28,
  62         BIF_BUSY_bit                                      = 1 << 29,
  63         IDCT_BUSY_bit                                     = 1 << 30,
  64
  65     SRBM_READ_ERROR                                       = 0x0e98,
  66         READ_ADDRESS_mask                                 = 0xffff << 2,
  67         READ_ADDRESS_shift                                = 2,
  68         READ_REQUESTER_HI_bit                             = 1 << 24,
  69         READ_REQUESTER_GRBM_bit                           = 1 << 25,
  70         READ_REQUESTER_RCU_bit                            = 1 << 26,
  71         READ_REQUESTER_RLC_bit                            = 1 << 27,
  72         READ_ERROR_bit                                    = 1 << 31,
  73
  74     SRBM_INT_STATUS                                       = 0x0ea4,
  75         RDERR_INT_STAT_bit                                = 1 << 0,
  76         GFX_CNTX_SWITCH_INT_STAT_bit                      = 1 << 1,
  77     SRBM_INT_ACK                                          = 0x0ea8,
  78         RDERR_INT_ACK_bit                                 = 1 << 0,
  79         GFX_CNTX_SWITCH_INT_ACK_bit                       = 1 << 1,
  80
  81     R6XX_MC_VM_FB_LOCATION                                = 0x2180,
  82
  83     VENDOR_DEVICE_ID                                      = 0x4000,
  84
  85     D1GRPH_PRIMARY_SURFACE_ADDRESS                        = 0x6110,
  86     D1GRPH_PITCH                                          = 0x6120,
  87     D1GRPH_Y_END                                          = 0x6138,
  88
  89     GRBM_STATUS                                           = 0x8010,
  90         CMDFIFO_AVAIL_mask                                = 0x1f << 0,
  91         CMDFIFO_AVAIL_shift                               = 0,
  92         SRBM_RQ_PENDING_bit                               = 1 << 5,
  93         CP_RQ_PENDING_bit                                 = 1 << 6,
  94         CF_RQ_PENDING_bit                                 = 1 << 7,
  95         PF_RQ_PENDING_bit                                 = 1 << 8,
  96         GRBM_EE_BUSY_bit                                  = 1 << 10,
  97         GRBM_STATUS__VC_BUSY_bit                          = 1 << 11,
  98         DB03_CLEAN_bit                                    = 1 << 12,
  99         CB03_CLEAN_bit                                    = 1 << 13,
 100         VGT_BUSY_NO_DMA_bit                               = 1 << 16,
 101         GRBM_STATUS__VGT_BUSY_bit                         = 1 << 17,
 102         TA03_BUSY_bit                                     = 1 << 18,
 103         GRBM_STATUS__TC_BUSY_bit                          = 1 << 19,
 104         SX_BUSY_bit                                       = 1 << 20,
 105         SH_BUSY_bit                                       = 1 << 21,
 106         SPI03_BUSY_bit                                    = 1 << 22,
 107         SMX_BUSY_bit                                      = 1 << 23,
 108         SC_BUSY_bit                                       = 1 << 24,
 109         PA_BUSY_bit                                       = 1 << 25,
 110         DB03_BUSY_bit                                     = 1 << 26,
 111         CR_BUSY_bit                                       = 1 << 27,
 112         CP_COHERENCY_BUSY_bit                             = 1 << 28,
 113         GRBM_STATUS__CP_BUSY_bit                          = 1 << 29,
 114         CB03_BUSY_bit                                     = 1 << 30,
 115         GUI_ACTIVE_bit                                    = 1 << 31,
 116     GRBM_STATUS2                                          = 0x8014,
 117         CR_CLEAN_bit                                      = 1 << 0,
 118         SMX_CLEAN_bit                                     = 1 << 1,
 119         SPI0_BUSY_bit                                     = 1 << 8,
 120         SPI1_BUSY_bit                                     = 1 << 9,
 121         SPI2_BUSY_bit                                     = 1 << 10,
 122         SPI3_BUSY_bit                                     = 1 << 11,
 123         TA0_BUSY_bit                                      = 1 << 12,
 124         TA1_BUSY_bit                                      = 1 << 13,
 125         TA2_BUSY_bit                                      = 1 << 14,
 126         TA3_BUSY_bit                                      = 1 << 15,
 127         DB0_BUSY_bit                                      = 1 << 16,
 128         DB1_BUSY_bit                                      = 1 << 17,
 129         DB2_BUSY_bit                                      = 1 << 18,
 130         DB3_BUSY_bit                                      = 1 << 19,
 131         CB0_BUSY_bit                                      = 1 << 20,
 132         CB1_BUSY_bit                                      = 1 << 21,
 133         CB2_BUSY_bit                                      = 1 << 22,
 134         CB3_BUSY_bit                                      = 1 << 23,
 135     GRBM_SOFT_RESET                                       = 0x8020,
 136         SOFT_RESET_CP_bit                                 = 1 << 0,
 137         SOFT_RESET_CB_bit                                 = 1 << 1,
 138         SOFT_RESET_CR_bit                                 = 1 << 2,
 139         SOFT_RESET_DB_bit                                 = 1 << 3,
 140         SOFT_RESET_PA_bit                                 = 1 << 5,
 141         SOFT_RESET_SC_bit                                 = 1 << 6,
 142         SOFT_RESET_SMX_bit                                = 1 << 7,
 143         SOFT_RESET_SPI_bit                                = 1 << 8,
 144         SOFT_RESET_SH_bit                                 = 1 << 9,
 145         SOFT_RESET_SX_bit                                 = 1 << 10,
 146         SOFT_RESET_TC_bit                                 = 1 << 11,
 147         SOFT_RESET_TA_bit                                 = 1 << 12,
 148         SOFT_RESET_VC_bit                                 = 1 << 13,
 149         SOFT_RESET_VGT_bit                                = 1 << 14,
 150         SOFT_RESET_GRBM_GCA_bit                           = 1 << 15,
 151
 152     WAIT_UNTIL                                            = 0x8040,
 153         WAIT_CP_DMA_IDLE_bit                              = 1 << 8,
 154         WAIT_CMDFIFO_bit                                  = 1 << 10,
 155         WAIT_2D_IDLE_bit                                  = 1 << 14,
 156         WAIT_3D_IDLE_bit                                  = 1 << 15,
 157         WAIT_2D_IDLECLEAN_bit                             = 1 << 16,
 158         WAIT_3D_IDLECLEAN_bit                             = 1 << 17,
 159         WAIT_EXTERN_SIG_bit                               = 1 << 19,
 160         CMDFIFO_ENTRIES_mask                              = 0x1f << 20,
 161         CMDFIFO_ENTRIES_shift                             = 20,
 162
 163     GRBM_READ_ERROR                                       = 0x8058,
 164 /*      READ_ADDRESS_mask                                 = 0xffff << 2, */
 165 /*      READ_ADDRESS_shift                                = 2, */
 166         READ_REQUESTER_SRBM_bit                           = 1 << 28,
 167         READ_REQUESTER_CP_bit                             = 1 << 29,
 168         READ_REQUESTER_WU_POLL_bit                        = 1 << 30,
 169 /*      READ_ERROR_bit                                    = 1 << 31, */
 170
 171     SCRATCH_REG0                                          = 0x8500,
 172     SCRATCH_REG1                                          = 0x8504,
 173     SCRATCH_REG2                                          = 0x8508,
 174     SCRATCH_REG3                                          = 0x850c,
 175     SCRATCH_REG4                                          = 0x8510,
 176     SCRATCH_REG5                                          = 0x8514,
 177     SCRATCH_REG6                                          = 0x8518,
 178     SCRATCH_REG7                                          = 0x851c,
 179     SCRATCH_UMSK                                          = 0x8540,
 180     SCRATCH_ADDR                                          = 0x8544,
 181
 182     CP_COHER_CNTL                                         = 0x85f0,
 183         DEST_BASE_0_ENA_bit                               = 1 << 0,
 184         DEST_BASE_1_ENA_bit                               = 1 << 1,
 185         SO0_DEST_BASE_ENA_bit                             = 1 << 2,
 186         SO1_DEST_BASE_ENA_bit                             = 1 << 3,
 187         SO2_DEST_BASE_ENA_bit                             = 1 << 4,
 188         SO3_DEST_BASE_ENA_bit                             = 1 << 5,
 189         CB0_DEST_BASE_ENA_bit                             = 1 << 6,
 190         CB1_DEST_BASE_ENA_bit                             = 1 << 7,
 191         CB2_DEST_BASE_ENA_bit                             = 1 << 8,
 192         CB3_DEST_BASE_ENA_bit                             = 1 << 9,
 193         CB4_DEST_BASE_ENA_bit                             = 1 << 10,
 194         CB5_DEST_BASE_ENA_bit                             = 1 << 11,
 195         CB6_DEST_BASE_ENA_bit                             = 1 << 12,
 196         CB7_DEST_BASE_ENA_bit                             = 1 << 13,
 197         DB_DEST_BASE_ENA_bit                              = 1 << 14,
 198         CR_DEST_BASE_ENA_bit                              = 1 << 15,
 199         TC_ACTION_ENA_bit                                 = 1 << 23,
 200         VC_ACTION_ENA_bit                                 = 1 << 24,
 201         CB_ACTION_ENA_bit                                 = 1 << 25,
 202         DB_ACTION_ENA_bit                                 = 1 << 26,
 203         SH_ACTION_ENA_bit                                 = 1 << 27,
 204         SMX_ACTION_ENA_bit                                = 1 << 28,
 205         CR0_ACTION_ENA_bit                                = 1 << 29,
 206         CR1_ACTION_ENA_bit                                = 1 << 30,
 207         CR2_ACTION_ENA_bit                                = 1 << 31,
 208     CP_COHER_SIZE                                         = 0x85f4,
 209     CP_COHER_BASE                                         = 0x85f8,
 210     CP_COHER_STATUS                                       = 0x85fc,
 211         MATCHING_GFX_CNTX_mask                            = 0xff << 0,
 212         MATCHING_GFX_CNTX_shift                           = 0,
 213         MATCHING_CR_CNTX_mask                             = 0xffff << 8,
 214         MATCHING_CR_CNTX_shift                            = 8,
 215         STATUS_bit                                        = 1 << 31,
 216
 217     CP_STALLED_STAT1                                      = 0x8674,
 218         RBIU_TO_DMA_NOT_RDY_TO_RCV_bit                    = 1 << 0,
 219         RBIU_TO_IBS_NOT_RDY_TO_RCV_bit                    = 1 << 1,
 220         RBIU_TO_SEM_NOT_RDY_TO_RCV_bit                    = 1 << 2,
 221         RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit                 = 1 << 3,
 222         RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit                  = 1 << 4,
 223         RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit                  = 1 << 5,
 224         RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit                   = 1 << 6,
 225         RBIU_TO_RECT_NOT_RDY_TO_RCV_bit                   = 1 << 7,
 226         RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit                  = 1 << 8,
 227         RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit                  = 1 << 9,
 228         MIU_WAITING_ON_RDREQ_FREE_bit                     = 1 << 16,
 229         MIU_WAITING_ON_WRREQ_FREE_bit                     = 1 << 17,
 230         MIU_NEEDS_AVAIL_WRREQ_PHASE_bit                   = 1 << 18,
 231         RCIU_WAITING_ON_GRBM_FREE_bit                     = 1 << 24,
 232         RCIU_WAITING_ON_VGT_FREE_bit                      = 1 << 25,
 233         RCIU_STALLED_ON_ME_READ_bit                       = 1 << 26,
 234         RCIU_STALLED_ON_DMA_READ_bit                      = 1 << 27,
 235         RCIU_HALTED_BY_REG_VIOLATION_bit                  = 1 << 28,
 236     CP_STALLED_STAT2                                      = 0x8678,
 237         PFP_TO_CSF_NOT_RDY_TO_RCV_bit                     = 1 << 0,
 238         PFP_TO_MEQ_NOT_RDY_TO_RCV_bit                     = 1 << 1,
 239         PFP_TO_VGT_NOT_RDY_TO_RCV_bit                     = 1 << 2,
 240         PFP_HALTED_BY_INSTR_VIOLATION_bit                 = 1 << 3,
 241         MULTIPASS_IB_PENDING_IN_PFP_bit                   = 1 << 4,
 242         ME_BRUSH_WC_NOT_RDY_TO_RCV_bit                    = 1 << 8,
 243         ME_STALLED_ON_BRUSH_LOGIC_bit                     = 1 << 9,
 244         CR_CNTX_NOT_AVAIL_TO_ME_bit                       = 1 << 10,
 245         GFX_CNTX_NOT_AVAIL_TO_ME_bit                      = 1 << 11,
 246         ME_RCIU_NOT_RDY_TO_RCV_bit                        = 1 << 12,
 247         ME_TO_CONST_NOT_RDY_TO_RCV_bit                    = 1 << 13,
 248         ME_WAITING_DATA_FROM_PFP_bit                      = 1 << 14,
 249         ME_WAITING_ON_PARTIAL_FLUSH_bit                   = 1 << 15,
 250         RECT_FIFO_NEEDS_CR_RECT_DONE_bit                  = 1 << 16,
 251         RECT_FIFO_NEEDS_WR_CONFIRM_bit                    = 1 << 17,
 252         EOPD_FIFO_NEEDS_SC_EOP_DONE_bit                   = 1 << 18,
 253         EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit                  = 1 << 19,
 254         EOPD_FIFO_NEEDS_WR_CONFIRM_bit                    = 1 << 20,
 255         EOPD_FIFO_NEEDS_SIGNAL_SEM_bit                    = 1 << 21,
 256         SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit                  = 1 << 22,
 257         SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit                 = 1 << 23,
 258         PIPE_STATS_FIFO_NEEDS_SAMPLE_bit                  = 1 << 24,
 259         SURF_SYNC_NEEDS_IDLE_CNTXS_bit                    = 1 << 30,
 260         SURF_SYNC_NEEDS_ALL_CLEAN_bit                     = 1 << 31,
 261     CP_BUSY_STAT                                          = 0x867c,
 262         REG_BUS_FIFO_BUSY_bit                             = 1 << 0,
 263         RING_FETCHING_DATA_bit                            = 1 << 1,
 264         INDR1_FETCHING_DATA_bit                           = 1 << 2,
 265         INDR2_FETCHING_DATA_bit                           = 1 << 3,
 266         STATE_FETCHING_DATA_bit                           = 1 << 4,
 267         PRED_FETCHING_DATA_bit                            = 1 << 5,
 268         COHER_CNTR_NEQ_ZERO_bit                           = 1 << 6,
 269         PFP_PARSING_PACKETS_bit                           = 1 << 7,
 270         ME_PARSING_PACKETS_bit                            = 1 << 8,
 271         RCIU_PFP_BUSY_bit                                 = 1 << 9,
 272         RCIU_ME_BUSY_bit                                  = 1 << 10,
 273         OUTSTANDING_READ_TAGS_bit                         = 1 << 11,
 274         SEM_CMDFIFO_NOT_EMPTY_bit                         = 1 << 12,
 275         SEM_FAILED_AND_HOLDING_bit                        = 1 << 13,
 276         SEM_POLLING_FOR_PASS_bit                          = 1 << 14,
 277         _3D_BUSY_bit                                      = 1 << 15,
 278         _2D_BUSY_bit                                      = 1 << 16,
 279     CP_STAT                                               = 0x8680,
 280         CSF_RING_BUSY_bit                                 = 1 << 0,
 281         CSF_WPTR_POLL_BUSY_bit                            = 1 << 1,
 282         CSF_INDIRECT1_BUSY_bit                            = 1 << 2,
 283         CSF_INDIRECT2_BUSY_bit                            = 1 << 3,
 284         CSF_STATE_BUSY_bit                                = 1 << 4,
 285         CSF_PREDICATE_BUSY_bit                            = 1 << 5,
 286         CSF_BUSY_bit                                      = 1 << 6,
 287         MIU_RDREQ_BUSY_bit                                = 1 << 7,
 288         MIU_WRREQ_BUSY_bit                                = 1 << 8,
 289         ROQ_RING_BUSY_bit                                 = 1 << 9,
 290         ROQ_INDIRECT1_BUSY_bit                            = 1 << 10,
 291         ROQ_INDIRECT2_BUSY_bit                            = 1 << 11,
 292         ROQ_STATE_BUSY_bit                                = 1 << 12,
 293         ROQ_PREDICATE_BUSY_bit                            = 1 << 13,
 294         ROQ_ALIGN_BUSY_bit                                = 1 << 14,
 295         PFP_BUSY_bit                                      = 1 << 15,
 296         MEQ_BUSY_bit                                      = 1 << 16,
 297         ME_BUSY_bit                                       = 1 << 17,
 298         QUERY_BUSY_bit                                    = 1 << 18,
 299         SEMAPHORE_BUSY_bit                                = 1 << 19,
 300         INTERRUPT_BUSY_bit                                = 1 << 20,
 301         SURFACE_SYNC_BUSY_bit                             = 1 << 21,
 302         DMA_BUSY_bit                                      = 1 << 22,
 303         RCIU_BUSY_bit                                     = 1 << 23,
 304         CP_STAT__CP_BUSY_bit                              = 1 << 31,
 305
 306     CP_ME_CNTL                                            = 0x86d8,
 307         ME_STATMUX_mask                                   = 0xff << 0,
 308         ME_STATMUX_shift                                  = 0,
 309         ME_HALT_bit                                       = 1 << 28,
 310     CP_ME_STATUS                                          = 0x86dc,
 311
 312     CP_RB_RPTR                                            = 0x8700,
 313         RB_RPTR_mask                                      = 0xfffff << 0,
 314         RB_RPTR_shift                                     = 0,
 315     CP_RB_WPTR_DELAY                                      = 0x8704,
 316         PRE_WRITE_TIMER_mask                              = 0xfffffff << 0,
 317         PRE_WRITE_TIMER_shift                             = 0,
 318         PRE_WRITE_LIMIT_mask                              = 0x0f << 28,
 319         PRE_WRITE_LIMIT_shift                             = 28,
 320
 321     CP_ROQ_RB_STAT                                        = 0x8780,
 322         ROQ_RPTR_PRIMARY_mask                             = 0x3ff << 0,
 323         ROQ_RPTR_PRIMARY_shift                            = 0,
 324         ROQ_WPTR_PRIMARY_mask                             = 0x3ff << 16,
 325         ROQ_WPTR_PRIMARY_shift                            = 16,
 326     CP_ROQ_IB1_STAT                                       = 0x8784,
 327         ROQ_RPTR_INDIRECT1_mask                           = 0x3ff << 0,
 328         ROQ_RPTR_INDIRECT1_shift                          = 0,
 329         ROQ_WPTR_INDIRECT1_mask                           = 0x3ff << 16,
 330         ROQ_WPTR_INDIRECT1_shift                          = 16,
 331     CP_ROQ_IB2_STAT                                       = 0x8788,
 332         ROQ_RPTR_INDIRECT2_mask                           = 0x3ff << 0,
 333         ROQ_RPTR_INDIRECT2_shift                          = 0,
 334         ROQ_WPTR_INDIRECT2_mask                           = 0x3ff << 16,
 335         ROQ_WPTR_INDIRECT2_shift                          = 16,
 336
 337     CP_MEQ_STAT                                           = 0x8794,
 338         MEQ_RPTR_mask                                     = 0x3ff << 0,
 339         MEQ_RPTR_shift                                    = 0,
 340         MEQ_WPTR_mask                                     = 0x3ff << 16,
 341         MEQ_WPTR_shift                                    = 16,
 342
 343     CC_GC_SHADER_PIPE_CONFIG                              = 0x8950,
 344         INACTIVE_QD_PIPES_mask                            = 0xff << 8,
 345         INACTIVE_QD_PIPES_shift                           = 8,
 346             R6XX_MAX_QD_PIPES                             = 8,
 347         INACTIVE_SIMDS_mask                               = 0xff << 16,
 348         INACTIVE_SIMDS_shift                              = 16,
 349             R6XX_MAX_SIMDS                                = 8,
 350     GC_USER_SHADER_PIPE_CONFIG                            = 0x8954,
 351
 352     VC_ENHANCE                                            = 0x9714,
 353     DB_DEBUG                                              = 0x9830,
 354         PREZ_MUST_WAIT_FOR_POSTZ_DONE                     = 1 << 31,
 355
 356     DB_WATERMARKS                                         = 0x00009838,
 357         DEPTH_FREE_mask                                   = 0x1f << 0,
 358         DEPTH_FREE_shift                                  = 0,
 359         DEPTH_FLUSH_mask                                  = 0x3f << 5,
 360         DEPTH_FLUSH_shift                                 = 5,
 361         FORCE_SUMMARIZE_mask                              = 0x0f << 11,
 362         FORCE_SUMMARIZE_shift                             = 11,
 363         DEPTH_PENDING_FREE_mask                           = 0x1f << 15,
 364         DEPTH_PENDING_FREE_shift                          = 15,
 365         DEPTH_CACHELINE_FREE_mask                         = 0x1f << 20,
 366         DEPTH_CACHELINE_FREE_shift                        = 20,
 367         EARLY_Z_PANIC_DISABLE_bit                         = 1 << 25,
 368         LATE_Z_PANIC_DISABLE_bit                          = 1 << 26,
 369         RE_Z_PANIC_DISABLE_bit                            = 1 << 27,
 370         DB_EXTRA_DEBUG_mask                               = 0x0f << 28,
 371         DB_EXTRA_DEBUG_shift                              = 28,
 372
 373     CP_RB_BASE                                            = 0xc100,
 374     CP_RB_CNTL                                            = 0xc104,
 375         RB_BUFSZ_mask                                     = 0x3f << 0,
 376     CP_RB_WPTR                                            = 0xc114,
 377         RB_WPTR_mask                                      = 0xfffff << 0,
 378         RB_WPTR_shift                                     = 0,
 379     CP_RB_RPTR_WR                                         = 0xc108,
 380         RB_RPTR_WR_mask                                   = 0xfffff << 0,
 381         RB_RPTR_WR_shift                                  = 0,
 382
 383     CP_INT_STATUS                                         = 0xc128,
 384         DISABLE_CNTX_SWITCH_INT_STAT_bit                  = 1 << 0,
 385         ENABLE_CNTX_SWITCH_INT_STAT_bit                   = 1 << 1,
 386         SEM_SIGNAL_INT_STAT_bit                           = 1 << 18,
 387         CNTX_BUSY_INT_STAT_bit                            = 1 << 19,
 388         CNTX_EMPTY_INT_STAT_bit                           = 1 << 20,
 389         WAITMEM_SEM_INT_STAT_bit                          = 1 << 21,
 390         PRIV_INSTR_INT_STAT_bit                           = 1 << 22,
 391         PRIV_REG_INT_STAT_bit                             = 1 << 23,
 392         OPCODE_ERROR_INT_STAT_bit                         = 1 << 24,
 393         SCRATCH_INT_STAT_bit                              = 1 << 25,
 394         TIME_STAMP_INT_STAT_bit                           = 1 << 26,
 395         RESERVED_BIT_ERROR_INT_STAT_bit                   = 1 << 27,
 396         DMA_INT_STAT_bit                                  = 1 << 28,
 397         IB2_INT_STAT_bit                                  = 1 << 29,
 398         IB1_INT_STAT_bit                                  = 1 << 30,
 399         RB_INT_STAT_bit                                   = 1 << 31,
 400
 401 //  SX_ALPHA_TEST_CONTROL                                 = 0x00028410,
 402         ALPHA_FUNC__REF_NEVER                             = 0,
 403         ALPHA_FUNC__REF_ALWAYS                            = 7,
 404 //  DB_SHADER_CONTROL                                     = 0x0002880c,
 405         Z_ORDER__EARLY_Z_THEN_LATE_Z                      = 2,
 406 //  PA_SU_SC_MODE_CNTL                                    = 0x00028814,
 407 //      POLY_MODE_mask                                    = 0x03 << 3,
 408         POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE,
 409 //      POLYMODE_FRONT_PTYPE_mask                         = 0x07 << 5,
 410         POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES,
 411     PA_SC_AA_SAMPLE_LOCS_8S_WD1_M                         = 0x00028c20,
 412     DB_SRESULTS_COMPARE_STATE0                            = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */
 413 //  DB_SRESULTS_COMPARE_STATE1                            = 0x00028d2c,
 414     DB_ALPHA_TO_MASK                                      = 0x00028d44,
 415         ALPHA_TO_MASK_ENABLE                              = 1 << 0,
 416         ALPHA_TO_MASK_OFFSET0_mask                        = 0x03 << 8,
 417         ALPHA_TO_MASK_OFFSET0_shift                       = 8,
 418         ALPHA_TO_MASK_OFFSET1_mask                        = 0x03 << 10,
 419         ALPHA_TO_MASK_OFFSET1_shift                       = 10,
 420         ALPHA_TO_MASK_OFFSET2_mask                        = 0x03 << 12,
 421         ALPHA_TO_MASK_OFFSET2_shift                       = 12,
 422         ALPHA_TO_MASK_OFFSET3_mask                        = 0x03 << 14,
 423         ALPHA_TO_MASK_OFFSET3_shift                       = 14,
 424
 425 //  SQ_VTX_CONSTANT_WORD2_0                               = 0x00038008,
 426 //      SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask         = 0x3f << 20,
 427         FMT_INVALID=0,      FMT_8,          FMT_4_4,            FMT_3_3_2,
 428                             FMT_16=5,       FMT_16_FLOAT,       FMT_8_8,
 429         FMT_5_6_5,          FMT_6_5_5,      FMT_1_5_5_5,        FMT_4_4_4_4,
 430         FMT_5_5_5_1,        FMT_32,         FMT_32_FLOAT,       FMT_16_16,
 431         FMT_16_16_FLOAT=16, FMT_8_24,       FMT_8_24_FLOAT,     FMT_24_8,
 432         FMT_24_8_FLOAT,     FMT_10_11_11,   FMT_10_11_11_FLOAT, FMT_11_11_10,
 433         FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8,        FMT_10_10_10_2,
 434         FMT_X24_8_32_FLOAT, FMT_32_32,      FMT_32_32_FLOAT,    FMT_16_16_16_16,
 435         FMT_16_16_16_16_FLOAT=32,           FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
 436                             FMT_1 = 37,                         FMT_GB_GR=39,
 437         FMT_BG_RG,          FMT_32_AS_8,    FMT_32_AS_8_8,      FMT_5_9_9_9_SHAREDEXP,
 438         FMT_8_8_8,          FMT_16_16_16,   FMT_16_16_16_FLOAT, FMT_32_32_32,
 439         FMT_32_32_32_FLOAT=48,
 440
 441 //  High level register file lengths
 442     SQ_ALU_CONSTANT                                       = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */
 443     SQ_ALU_CONSTANT_ps_num                                = 256,
 444     SQ_ALU_CONSTANT_vs_num                                = 256,
 445     SQ_ALU_CONSTANT_all_num                               = 512,
 446     SQ_ALU_CONSTANT_offset                                = 16,
 447     SQ_ALU_CONSTANT_ps                                    = 0,
 448     SQ_ALU_CONSTANT_vs                                    = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num,
 449     SQ_TEX_RESOURCE                                       = SQ_TEX_RESOURCE_WORD0_0,    /* 160 PS, 160 VS, 16 FS, 160 GS */
 450     SQ_TEX_RESOURCE_ps_num                                = 160,
 451     SQ_TEX_RESOURCE_vs_num                                = 160,
 452     SQ_TEX_RESOURCE_fs_num                                = 16,
 453     SQ_TEX_RESOURCE_gs_num                                = 160,
 454     SQ_TEX_RESOURCE_all_num                               = 496,
 455     SQ_TEX_RESOURCE_offset                                = 28,
 456     SQ_TEX_RESOURCE_ps                                    = 0,
 457     SQ_TEX_RESOURCE_vs                                    = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num,
 458     SQ_TEX_RESOURCE_fs                                    = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num,
 459     SQ_TEX_RESOURCE_gs                                    = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num,
 460     SQ_VTX_RESOURCE                                       = SQ_VTX_CONSTANT_WORD0_0,    /* 160 PS, 160 VS, 16 FS, 160 GS */
 461     SQ_VTX_RESOURCE_ps_num                                = 160,
 462     SQ_VTX_RESOURCE_vs_num                                = 160,
 463     SQ_VTX_RESOURCE_fs_num                                = 16,
 464     SQ_VTX_RESOURCE_gs_num                                = 160,
 465     SQ_VTX_RESOURCE_all_num                               = 496,
 466     SQ_VTX_RESOURCE_offset                                = 28,
 467     SQ_VTX_RESOURCE_ps                                    = 0,
 468     SQ_VTX_RESOURCE_vs                                    = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num,
 469     SQ_VTX_RESOURCE_fs                                    = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num,
 470     SQ_VTX_RESOURCE_gs                                    = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num,
 471     SQ_TEX_SAMPLER_WORD                                   = SQ_TEX_SAMPLER_WORD0_0,     /* 18 per PS, VS, GS */
 472     SQ_TEX_SAMPLER_WORD_ps_num                            = 18,
 473     SQ_TEX_SAMPLER_WORD_vs_num                            = 18,
 474     SQ_TEX_SAMPLER_WORD_gs_num                            = 18,
 475     SQ_TEX_SAMPLER_WORD_all_num                           = 54,
 476     SQ_TEX_SAMPLER_WORD_offset                            = 12,
 477     SQ_TEX_SAMPLER_WORD_ps                                = 0,
 478     SQ_TEX_SAMPLER_WORD_vs                                = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num,
 479     SQ_TEX_SAMPLER_WORD_gs                                = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num,
 480     SQ_LOOP_CONST                                         = SQ_LOOP_CONST_0,            /* 32 per PS, VS, GS */
 481     SQ_LOOP_CONST_ps_num                                  = 32,
 482     SQ_LOOP_CONST_vs_num                                  = 32,
 483     SQ_LOOP_CONST_gs_num                                  = 32,
 484     SQ_LOOP_CONST_all_num                                 = 96,
 485     SQ_LOOP_CONST_offset                                  = 4,
 486     SQ_LOOP_CONST_ps                                      = 0,
 487     SQ_LOOP_CONST_vs                                      = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num,
 488     SQ_LOOP_CONST_gs                                      = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num,
 489 } ;
 490
 491
 492 #endif