src/mesa/drivers/dri/r600/r600_cmdbuf.h

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Nicolai Haehnle <prefect_@gmx.net>
  34  */
  35
  36 #ifndef __R600_CMDBUF_H__
  37 #define __R600_CMDBUF_H__
  38
  39 #include "r600_context.h"
  40
  41 #define RADEON_CP_PACKET3_NOP                       0xC0001000
  42 #define RADEON_CP_PACKET3_NEXT_CHAR                 0xC0001900
  43 #define RADEON_CP_PACKET3_PLY_NEXTSCAN              0xC0001D00
  44 #define RADEON_CP_PACKET3_SET_SCISSORS              0xC0001E00
  45 #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM     0xC0002300
  46 #define RADEON_CP_PACKET3_LOAD_MICROCODE            0xC0002400
  47 #define RADEON_CP_PACKET3_WAIT_FOR_IDLE             0xC0002600
  48 #define RADEON_CP_PACKET3_3D_DRAW_VBUF              0xC0002800
  49 #define RADEON_CP_PACKET3_3D_DRAW_IMMD              0xC0002900
  50 #define RADEON_CP_PACKET3_3D_DRAW_INDX              0xC0002A00
  51 #define RADEON_CP_PACKET3_LOAD_PALETTE              0xC0002C00
  52 #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR            0xC0002F00
  53 #define RADEON_CP_PACKET3_CNTL_PAINT                0xC0009100
  54 #define RADEON_CP_PACKET3_CNTL_BITBLT               0xC0009200
  55 #define RADEON_CP_PACKET3_CNTL_SMALLTEXT            0xC0009300
  56 #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT         0xC0009400
  57 #define RADEON_CP_PACKET3_CNTL_POLYLINE             0xC0009500
  58 #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES        0xC0009800
  59 #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI          0xC0009A00
  60 #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI         0xC0009B00
  61 #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT         0xC0009C00
  62
  63 /* r6xx/r7xx packet 3 type offsets */
  64 #define R600_SET_CONFIG_REG_OFFSET                  0x00008000
  65 #define R600_SET_CONFIG_REG_END                     0x0000ac00
  66 #define R600_SET_CONTEXT_REG_OFFSET                 0x00028000
  67 #define R600_SET_CONTEXT_REG_END                    0x00029000
  68 #define R600_SET_ALU_CONST_OFFSET                   0x00030000
  69 #define R600_SET_ALU_CONST_END                      0x00032000
  70 #define R600_SET_RESOURCE_OFFSET                    0x00038000
  71 #define R600_SET_RESOURCE_END                       0x0003c000
  72 #define R600_SET_SAMPLER_OFFSET                     0x0003c000
  73 #define R600_SET_SAMPLER_END                        0x0003cff0
  74 #define R600_SET_CTL_CONST_OFFSET                   0x0003cff0
  75 #define R600_SET_CTL_CONST_END                      0x0003e200
  76 #define R600_SET_LOOP_CONST_OFFSET                  0x0003e200
  77 #define R600_SET_LOOP_CONST_END                     0x0003e380
  78 #define R600_SET_BOOL_CONST_OFFSET                  0x0003e380
  79 #define R600_SET_BOOL_CONST_END                     0x00040000
  80
  81 /* r6xx/r7xx packet 3 types */
  82 #define R600_IT_INDIRECT_BUFFER_END               0x00001700
  83 #define R600_IT_SET_PREDICATION                   0x00002000
  84 #define R600_IT_REG_RMW                           0x00002100
  85 #define R600_IT_COND_EXEC                         0x00002200
  86 #define R600_IT_PRED_EXEC                         0x00002300
  87 #define R600_IT_START_3D_CMDBUF                   0x00002400
  88 #define R600_IT_DRAW_INDEX_2                      0x00002700
  89 #define R600_IT_CONTEXT_CONTROL                   0x00002800
  90 #define R600_IT_DRAW_INDEX_IMMD_BE                0x00002900
  91 #define R600_IT_INDEX_TYPE                        0x00002A00
  92 #define R600_IT_DRAW_INDEX                        0x00002B00
  93 #define R600_IT_DRAW_INDEX_AUTO                   0x00002D00
  94 #define R600_IT_DRAW_INDEX_IMMD                   0x00002E00
  95 #define R600_IT_NUM_INSTANCES                     0x00002F00
  96 #define R600_IT_STRMOUT_BUFFER_UPDATE             0x00003400
  97 #define R600_IT_INDIRECT_BUFFER_MP                0x00003800
  98 #define R600_IT_MEM_SEMAPHORE                     0x00003900
  99 #define R600_IT_MPEG_INDEX                        0x00003A00
 100 #define R600_IT_WAIT_REG_MEM                      0x00003C00
 101 #define R600_IT_MEM_WRITE                         0x00003D00
 102 #define R600_IT_INDIRECT_BUFFER                   0x00003200
 103 #define R600_IT_CP_INTERRUPT                      0x00004000
 104 #define R600_IT_SURFACE_SYNC                      0x00004300
 105 #define R600_IT_ME_INITIALIZE                     0x00004400
 106 #define R600_IT_COND_WRITE                        0x00004500
 107 #define R600_IT_EVENT_WRITE                       0x00004600
 108 #       define R600_EVENT_TYPE(x)                 ((x) << 0)
 109 #       define R600_EVENT_INDEX(x)                ((x) << 8)
 110 #define R600_IT_EVENT_WRITE_EOP                   0x00004700
 111 #define R600_IT_ONE_REG_WRITE                     0x00005700
 112 #define R600_IT_SET_CONFIG_REG                    0x00006800
 113 #define R600_IT_SET_CONTEXT_REG                   0x00006900
 114 #define R600_IT_SET_ALU_CONST                     0x00006A00
 115 #define R600_IT_SET_BOOL_CONST                    0x00006B00
 116 #define R600_IT_SET_LOOP_CONST                    0x00006C00
 117 #define R600_IT_SET_RESOURCE                      0x00006D00
 118 #define R600_IT_SET_SAMPLER                       0x00006E00
 119 #define R600_IT_SET_CTL_CONST                     0x00006F00
 120 #define R600_IT_SURFACE_BASE_UPDATE               0x00007300
 121
 122 struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_context *ctx);
 123
 124 /**
 125  * Write one dword to the command buffer.
 126  */
 127 #define R600_OUT_BATCH(data)                            \
 128 do {                                                    \
 129         radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);      \
 130 } while(0)
 131
 132 /**
 133  * Write n dwords from ptr to the command buffer.
 134  */
 135 #define R600_OUT_BATCH_TABLE(ptr,n)             \
 136 do {                                                 \
 137         radeon_cs_write_table(b_l_rmesa->cmdbuf.cs, ptr, n);    \
 138 } while(0)
 139
 140 /**
 141  * Write a relocated dword to the command buffer.
 142  */
 143 #define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags)   \
 144         do {                                                    \
 145         if (0 && offset) {                                      \
 146             fprintf(stderr, "(%s:%s:%d) offset : %d\n",         \
 147             __FILE__, __FUNCTION__, __LINE__, offset);          \
 148         }                                                       \
 149         radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs,             \
 150                               bo, rd, wd, flags);               \
 151         } while(0)
 152
 153 /* R600/R700 */
 154 #define R600_OUT_BATCH_REGS(reg, num)                                   \
 155 do {                                                            \
 156         if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
 157                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num)));      \
 158                 R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2);      \
 159         } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
 160                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num)));     \
 161                 R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2);     \
 162         } else if ((reg) >= R600_SET_ALU_CONST_OFFSET && (reg) < R600_SET_ALU_CONST_END) { \
 163                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, (num)));       \
 164                 R600_OUT_BATCH(((reg) - R600_SET_ALU_CONST_OFFSET) >> 2);       \
 165         } else if ((reg) >= R600_SET_RESOURCE_OFFSET && (reg) < R600_SET_RESOURCE_END) { \
 166                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num)));        \
 167                 R600_OUT_BATCH(((reg) - R600_SET_RESOURCE_OFFSET) >> 2);        \
 168         } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
 169                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \
 170                 R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \
 171         } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
 172                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num)));       \
 173                 R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2);       \
 174         } else if ((reg) >= R600_SET_LOOP_CONST_OFFSET && (reg) < R600_SET_LOOP_CONST_END) { \
 175                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num)));      \
 176                 R600_OUT_BATCH(((reg) - R600_SET_LOOP_CONST_OFFSET) >> 2);      \
 177         } else if ((reg) >= R600_SET_BOOL_CONST_OFFSET && (reg) < R600_SET_BOOL_CONST_END) { \
 178                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num)));      \
 179                 R600_OUT_BATCH(((reg) - R600_SET_BOOL_CONST_OFFSET) >> 2);      \
 180         } else {                                                        \
 181                 R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
 182         }                                                               \
 183 } while (0)
 184
 185 /** Single register write to command buffer; requires 3 dwords for most things. */
 186 #define R600_OUT_BATCH_REGVAL(reg, val)         \
 187         R600_OUT_BATCH_REGS((reg), 1);          \
 188         R600_OUT_BATCH((val))
 189
 190 /** Continuous register range write to command buffer; requires 1 dword,
 191  * expects count dwords afterwards for register contents. */
 192 #define R600_OUT_BATCH_REGSEQ(reg, count)       \
 193         R600_OUT_BATCH_REGS((reg), (count))
 194
 195 /* evergreen */
 196 #define EVERGREEN_OUT_BATCH_REGS(reg, num)                                      \
 197 do {                                                            \
 198         if ((reg) >= R600_SET_CONFIG_REG_OFFSET && (reg) < R600_SET_CONFIG_REG_END) { \
 199                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, (num)));      \
 200                 R600_OUT_BATCH(((reg) - R600_SET_CONFIG_REG_OFFSET) >> 2);      \
 201         } else if ((reg) >= R600_SET_CONTEXT_REG_OFFSET && (reg) < R600_SET_CONTEXT_REG_END) { \
 202                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONTEXT_REG, (num)));     \
 203                 R600_OUT_BATCH(((reg) - R600_SET_CONTEXT_REG_OFFSET) >> 2);     \
 204         } else if ((reg) >= EG_SET_RESOURCE_OFFSET && (reg) < EG_SET_RESOURCE_END) { \
 205                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, (num)));        \
 206                 R600_OUT_BATCH(((reg) - EG_SET_RESOURCE_OFFSET) >> 2);  \
 207     } else if ((reg) >= EG_SET_LOOP_CONST_OFFSET && (reg) < EG_SET_LOOP_CONST_END) { \
 208                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_LOOP_CONST, (num)));      \
 209                 R600_OUT_BATCH(((reg) - EG_SET_LOOP_CONST_OFFSET) >> 2);        \
 210         } else if ((reg) >= R600_SET_SAMPLER_OFFSET && (reg) < R600_SET_SAMPLER_END) { \
 211                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, (num))); \
 212                 R600_OUT_BATCH(((reg) - R600_SET_SAMPLER_OFFSET) >> 2); \
 213         } else if ((reg) >= R600_SET_CTL_CONST_OFFSET && (reg) < R600_SET_CTL_CONST_END) { \
 214                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, (num)));       \
 215                 R600_OUT_BATCH(((reg) - R600_SET_CTL_CONST_OFFSET) >> 2);       \
 216         } else if ((reg) >= EG_SET_BOOL_CONST_OFFSET && (reg) < EG_SET_BOOL_CONST_END) { \
 217                 R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_BOOL_CONST, (num)));      \
 218                 R600_OUT_BATCH(((reg) - EG_SET_BOOL_CONST_OFFSET) >> 2);        \
 219         } else {                                                        \
 220                 R600_OUT_BATCH(CP_PACKET0((reg), (num))); \
 221         }                                                               \
 222 } while (0)
 223
 224 /** Single register write to command buffer; requires 3 dwords for most things. */
 225 #define EVERGREEN_OUT_BATCH_REGVAL(reg, val)            \
 226         EVERGREEN_OUT_BATCH_REGS((reg), 1);             \
 227         R600_OUT_BATCH((val))
 228
 229 /** Continuous register range write to command buffer; requires 1 dword,
 230  * expects count dwords afterwards for register contents. */
 231 #define EVERGREEN_OUT_BATCH_REGSEQ(reg, count)  \
 232             EVERGREEN_OUT_BATCH_REGS((reg), (count))
 233
 234
 235 extern void r600InitCmdBuf(context_t *r600);
 236
 237 #endif                          /* __R600_CMDBUF_H__ */