src/mesa/drivers/dri/r600/r600_blit_shaders.h

   1 const uint32_t r6xx_vs[] =
   2 {
   3         0x00000004, // CF_DWORD0(ADDR(4))
   4         0x81000000, // SQ_CF_INST_VTX COUNT(1)
   5         0x0000203c, // CF_EXP_IMP CF_POS0 SQ_EXPORT_POS RW_GPR(0) ELEM_SIZE(0)
   6         0x94000b08, // SQ_CF_INST_EXPORT_DONE SWZ XY01 BARRIER(1)
   7         0x00004000, // CF_EXP_IMP 0 SQ_EXPORT_PARAM RW_GPR(0) ELEM_SIZE(0)
   8         0x14200b1a, // SQ_CF_INST_EXPORT_DONE SWZ ZW01 EOP(1) BARRIER(0)
   9         0x00000000,
  10         0x00000000,
  11         0x3c000000, // SQ_VTX_INST_FETCH BUFFER_ID(0) MEGA_FETCH_COUNT(16)
  12         0x68cd1000, // DST_GPR(0) DST_SWZ: XYZW DATA_FORMAT(35) SQ_NUM_FORMAT_SCALED SQ_FORMAT_COMP_SIGNED
  13 #ifdef MESA_BIG_ENDIAN
  14                 0x000a0000, // ENDIAN_SWAP(SQ_ENDIAN_8IN32) MEGA_FETCH(1)
  15 #else
  16         0x00080000, // ENDIAN_SWAP(SQ_ENDIAN_NONE) MEGA_FETCH(1)
  17 #endif
  18         0x00000000, // VTX_DWORD_PAD
  19 };
  20
  21 const uint32_t r6xx_ps[] =
  22 {
  23         0x00000002, // CF_DWORD0 AADR(2)
  24         0x80800000, // SQ_CF_INST_TEX COUNT(1)
  25         0x00000000, // CF_ALLOC_IMP_EXP0 SQ_EXPORT_PIXEL RW_GPR(0) ELEM_SIZE(0)
  26         0x94200688, // SQ_CF_INST_EXPORT_DONE EOP(1) BARRIER(1) SWZ: XYZW
  27         0x00000010, // SQ_TEX_INST_SAMPLE SRC_GPR(0) RESOURCE_ID(0)
  28         0x000d1000, // DST_GPR(0) SWZ: XYZW TEX_UNNORMALIZED
  29         0xb0800000, // SAMPLER_ID(0) SRC_SWZ XYZW
  30         0x00000000, // TEX_DWORD_PAD
  31 };
  32