src/mesa/drivers/dri/r600/evergreen_blit.c

   1 /*
   2  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "radeon_common.h"
  29 #include "r600_context.h"
  30
  31 #include "evergreen_off.h"
  32 #include "evergreen_diff.h"
  33
  34 #include "evergreen_blit.h"
  35 #include "evergreen_blit_shaders.h"
  36 #include "r600_cmdbuf.h"
  37
  38 /* common formats supported as both textures and render targets */
  39 unsigned evergreen_check_blit(gl_format mesa_format)
  40 {
  41     switch (mesa_format) {
  42     case MESA_FORMAT_RGBA8888:
  43     case MESA_FORMAT_SIGNED_RGBA8888:
  44     case MESA_FORMAT_RGBA8888_REV:
  45     case MESA_FORMAT_SIGNED_RGBA8888_REV:
  46     case MESA_FORMAT_ARGB8888:
  47     case MESA_FORMAT_XRGB8888:
  48     case MESA_FORMAT_ARGB8888_REV:
  49     case MESA_FORMAT_XRGB8888_REV:
  50     case MESA_FORMAT_RGB565:
  51     case MESA_FORMAT_RGB565_REV:
  52     case MESA_FORMAT_ARGB4444:
  53     case MESA_FORMAT_ARGB4444_REV:
  54     case MESA_FORMAT_ARGB1555:
  55     case MESA_FORMAT_ARGB1555_REV:
  56     case MESA_FORMAT_AL88:
  57     case MESA_FORMAT_AL88_REV:
  58     case MESA_FORMAT_RGB332:
  59     case MESA_FORMAT_A8:
  60     case MESA_FORMAT_I8:
  61     case MESA_FORMAT_CI8:
  62     case MESA_FORMAT_L8:
  63     case MESA_FORMAT_RGBA_FLOAT32:
  64     case MESA_FORMAT_RGBA_FLOAT16:
  65     case MESA_FORMAT_ALPHA_FLOAT32:
  66     case MESA_FORMAT_ALPHA_FLOAT16:
  67     case MESA_FORMAT_LUMINANCE_FLOAT32:
  68     case MESA_FORMAT_LUMINANCE_FLOAT16:
  69     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
  70     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
  71     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
  72     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
  73     case MESA_FORMAT_X8_Z24:
  74     case MESA_FORMAT_S8_Z24:
  75     case MESA_FORMAT_Z24_S8:
  76     case MESA_FORMAT_Z16:
  77     case MESA_FORMAT_Z32:
  78     case MESA_FORMAT_SARGB8:
  79     case MESA_FORMAT_SLA8:
  80     case MESA_FORMAT_SL8:
  81             break;
  82     default:
  83             return 0;
  84     }
  85
  86     /* ??? */
  87     /* not sure blit to depth works or not yet */
  88     if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0)
  89             return 0;
  90
  91     return 1;
  92 }
  93
  94 static inline void
  95 eg_set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_format,
  96                      int nPitchInPixel, int w, int h, intptr_t dst_offset)
  97 {
  98     uint32_t cb_color0_base, cb_color0_info = 0;
  99     uint32_t cb_color0_pitch = 0, cb_color0_slice = 0, cb_color0_attrib = 0;
 100     int id = 0;
 101     uint32_t endian, comp_swap, format, source_format, number_type;
 102     BATCH_LOCALS(&context->radeon);
 103
 104     cb_color0_base = dst_offset / 256;
 105     endian = ENDIAN_NONE;
 106
 107     /* pitch */
 108     SETfield(cb_color0_pitch, (nPitchInPixel / 8) - 1,
 109              EG_CB_COLOR0_PITCH__TILE_MAX_shift,
 110              EG_CB_COLOR0_PITCH__TILE_MAX_mask);
 111
 112     /* slice */
 113     SETfield(cb_color0_slice,
 114              ((nPitchInPixel * h) / 64) - 1,
 115              EG_CB_COLOR0_SLICE__TILE_MAX_shift,
 116              EG_CB_COLOR0_SLICE__TILE_MAX_mask);
 117
 118     /* CB_COLOR0_ATTRIB */ /* TODO : for z clear, this should be set to 0 */
 119     SETbit(cb_color0_attrib,
 120            EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit);
 121
 122     SETfield(cb_color0_info,
 123              ARRAY_LINEAR_GENERAL,
 124              EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
 125              EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
 126
 127     SETbit(cb_color0_info, EG_CB_COLOR0_INFO__BLEND_BYPASS_bit);
 128
 129     switch(mesa_format) {
 130     case MESA_FORMAT_RGBA8888:
 131 #ifdef MESA_BIG_ENDIAN
 132             endian = ENDIAN_8IN32;
 133 #endif
 134             format = COLOR_8_8_8_8;
 135             comp_swap = SWAP_STD_REV;
 136             number_type = NUMBER_UNORM;
 137             source_format = 1;
 138             break;
 139     case MESA_FORMAT_SIGNED_RGBA8888:
 140 #ifdef MESA_BIG_ENDIAN
 141             endian = ENDIAN_8IN32;
 142 #endif
 143             format = COLOR_8_8_8_8;
 144             comp_swap = SWAP_STD_REV;
 145             number_type = NUMBER_SNORM;
 146             source_format = 1;
 147             break;
 148     case MESA_FORMAT_RGBA8888_REV:
 149 #ifdef MESA_BIG_ENDIAN
 150             endian = ENDIAN_8IN32;
 151 #endif
 152             format = COLOR_8_8_8_8;
 153             comp_swap = SWAP_STD;
 154             number_type = NUMBER_UNORM;
 155             source_format = 1;
 156             break;
 157     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 158 #ifdef MESA_BIG_ENDIAN
 159             endian = ENDIAN_8IN32;
 160 #endif
 161             format = COLOR_8_8_8_8;
 162             comp_swap = SWAP_STD;
 163             number_type = NUMBER_SNORM;
 164             source_format = 1;
 165             break;
 166     case MESA_FORMAT_ARGB8888:
 167     case MESA_FORMAT_XRGB8888:
 168 #ifdef MESA_BIG_ENDIAN
 169             endian = ENDIAN_8IN32;
 170 #endif
 171             format = COLOR_8_8_8_8;
 172             comp_swap = SWAP_ALT;
 173             number_type = NUMBER_UNORM;
 174             source_format = 1;
 175             break;
 176     case MESA_FORMAT_ARGB8888_REV:
 177     case MESA_FORMAT_XRGB8888_REV:
 178 #ifdef MESA_BIG_ENDIAN
 179             endian = ENDIAN_8IN32;
 180 #endif
 181             format = COLOR_8_8_8_8;
 182             comp_swap = SWAP_ALT_REV;
 183             number_type = NUMBER_UNORM;
 184             source_format = 1;
 185             break;
 186     case MESA_FORMAT_RGB565:
 187 #ifdef MESA_BIG_ENDIAN
 188             endian = ENDIAN_8IN16;
 189 #endif
 190             format = COLOR_5_6_5;
 191             comp_swap = SWAP_STD_REV;
 192             number_type = NUMBER_UNORM;
 193             source_format = 1;
 194             break;
 195     case MESA_FORMAT_RGB565_REV:
 196 #ifdef MESA_BIG_ENDIAN
 197             endian = ENDIAN_8IN16;
 198 #endif
 199             format = COLOR_5_6_5;
 200             comp_swap = SWAP_STD;
 201             number_type = NUMBER_UNORM;
 202             source_format = 1;
 203             break;
 204     case MESA_FORMAT_ARGB4444:
 205 #ifdef MESA_BIG_ENDIAN
 206             endian = ENDIAN_8IN16;
 207 #endif
 208             format = COLOR_4_4_4_4;
 209             comp_swap = SWAP_ALT;
 210             number_type = NUMBER_UNORM;
 211             source_format = 1;
 212             break;
 213     case MESA_FORMAT_ARGB4444_REV:
 214 #ifdef MESA_BIG_ENDIAN
 215             endian = ENDIAN_8IN16;
 216 #endif
 217             format = COLOR_4_4_4_4;
 218             comp_swap = SWAP_ALT_REV;
 219             number_type = NUMBER_UNORM;
 220             source_format = 1;
 221             break;
 222     case MESA_FORMAT_ARGB1555:
 223 #ifdef MESA_BIG_ENDIAN
 224             endian = ENDIAN_8IN16;
 225 #endif
 226             format = COLOR_1_5_5_5;
 227             comp_swap = SWAP_ALT;
 228             number_type = NUMBER_UNORM;
 229             source_format = 1;
 230             break;
 231     case MESA_FORMAT_ARGB1555_REV:
 232 #ifdef MESA_BIG_ENDIAN
 233             endian = ENDIAN_8IN16;
 234 #endif
 235             format = COLOR_1_5_5_5;
 236             comp_swap = SWAP_ALT_REV;
 237             number_type = NUMBER_UNORM;
 238             source_format = 1;
 239             break;
 240     case MESA_FORMAT_AL88:
 241 #ifdef MESA_BIG_ENDIAN
 242             endian = ENDIAN_8IN16;
 243 #endif
 244             format = COLOR_8_8;
 245             comp_swap = SWAP_STD;
 246             number_type = NUMBER_UNORM;
 247             source_format = 1;
 248             break;
 249     case MESA_FORMAT_AL88_REV:
 250 #ifdef MESA_BIG_ENDIAN
 251             endian = ENDIAN_8IN16;
 252 #endif
 253             format = COLOR_8_8;
 254             comp_swap = SWAP_STD_REV;
 255             number_type = NUMBER_UNORM;
 256             source_format = 1;
 257             break;
 258     case MESA_FORMAT_RGB332:
 259             format = COLOR_3_3_2;
 260             comp_swap = SWAP_STD_REV;
 261             number_type = NUMBER_UNORM;
 262             source_format = 1;
 263             break;
 264     case MESA_FORMAT_A8:
 265             format = COLOR_8;
 266             comp_swap = SWAP_ALT_REV;
 267             number_type = NUMBER_UNORM;
 268             source_format = 1;
 269             break;
 270     case MESA_FORMAT_I8:
 271     case MESA_FORMAT_CI8:
 272             format = COLOR_8;
 273             comp_swap = SWAP_STD;
 274             number_type = NUMBER_UNORM;
 275             source_format = 1;
 276             break;
 277     case MESA_FORMAT_L8:
 278             format = COLOR_8;
 279             comp_swap = SWAP_ALT;
 280             number_type = NUMBER_UNORM;
 281             source_format = 1;
 282             break;
 283     case MESA_FORMAT_RGBA_FLOAT32:
 284 #ifdef MESA_BIG_ENDIAN
 285             endian = ENDIAN_8IN32;
 286 #endif
 287             format = COLOR_32_32_32_32_FLOAT;
 288             comp_swap = SWAP_STD;
 289             number_type = NUMBER_FLOAT;
 290             source_format = 0;
 291             break;
 292     case MESA_FORMAT_RGBA_FLOAT16:
 293 #ifdef MESA_BIG_ENDIAN
 294             endian = ENDIAN_8IN16;
 295 #endif
 296             format = COLOR_16_16_16_16_FLOAT;
 297             comp_swap = SWAP_STD;
 298             number_type = NUMBER_FLOAT;
 299             source_format = 0;
 300             break;
 301     case MESA_FORMAT_ALPHA_FLOAT32:
 302 #ifdef MESA_BIG_ENDIAN
 303             endian = ENDIAN_8IN32;
 304 #endif
 305             format = COLOR_32_FLOAT;
 306             comp_swap = SWAP_ALT_REV;
 307             number_type = NUMBER_FLOAT;
 308             source_format = 0;
 309             break;
 310     case MESA_FORMAT_ALPHA_FLOAT16:
 311 #ifdef MESA_BIG_ENDIAN
 312             endian = ENDIAN_8IN16;
 313 #endif
 314             format = COLOR_16_FLOAT;
 315             comp_swap = SWAP_ALT_REV;
 316             number_type = NUMBER_FLOAT;
 317             source_format = 0;
 318             break;
 319     case MESA_FORMAT_LUMINANCE_FLOAT32:
 320 #ifdef MESA_BIG_ENDIAN
 321             endian = ENDIAN_8IN32;
 322 #endif
 323             format = COLOR_32_FLOAT;
 324             comp_swap = SWAP_ALT;
 325             number_type = NUMBER_FLOAT;
 326             source_format = 0;
 327             break;
 328     case MESA_FORMAT_LUMINANCE_FLOAT16:
 329 #ifdef MESA_BIG_ENDIAN
 330             endian = ENDIAN_8IN16;
 331 #endif
 332             format = COLOR_16_FLOAT;
 333             comp_swap = SWAP_ALT;
 334             number_type = NUMBER_FLOAT;
 335             source_format = 0;
 336             break;
 337     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 338 #ifdef MESA_BIG_ENDIAN
 339             endian = ENDIAN_8IN32;
 340 #endif
 341             format = COLOR_32_32_FLOAT;
 342             comp_swap = SWAP_ALT_REV;
 343             number_type = NUMBER_FLOAT;
 344             source_format = 0;
 345             break;
 346     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 347 #ifdef MESA_BIG_ENDIAN
 348             endian = ENDIAN_8IN16;
 349 #endif
 350             format = COLOR_16_16_FLOAT;
 351             comp_swap = SWAP_ALT_REV;
 352             number_type = NUMBER_FLOAT;
 353             source_format = 0;
 354             break;
 355     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 356 #ifdef MESA_BIG_ENDIAN
 357             endian = ENDIAN_8IN32;
 358 #endif
 359             format = COLOR_32_FLOAT;
 360             comp_swap = SWAP_STD;
 361             number_type = NUMBER_FLOAT;
 362             source_format = 0;
 363             break;
 364     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 365 #ifdef MESA_BIG_ENDIAN
 366             endian = ENDIAN_8IN16;
 367 #endif
 368             format = COLOR_16_FLOAT;
 369             comp_swap = SWAP_STD;
 370             number_type = NUMBER_UNORM;
 371             source_format = 0;
 372             break;
 373     case MESA_FORMAT_X8_Z24:
 374     case MESA_FORMAT_S8_Z24:
 375 #ifdef MESA_BIG_ENDIAN
 376             endian = ENDIAN_8IN32;
 377 #endif
 378             format = COLOR_8_24;
 379             comp_swap = SWAP_STD;
 380             number_type = NUMBER_UNORM;
 381             SETfield(cb_color0_info,
 382                      ARRAY_1D_TILED_THIN1,
 383                      EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
 384                      EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
 385             source_format = 0;
 386             break;
 387     case MESA_FORMAT_Z24_S8:
 388 #ifdef MESA_BIG_ENDIAN
 389             endian = ENDIAN_8IN32;
 390 #endif
 391             format = COLOR_24_8;
 392             comp_swap = SWAP_STD;
 393             number_type = NUMBER_UNORM;
 394             SETfield(cb_color0_info,
 395                      ARRAY_1D_TILED_THIN1,
 396                      EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
 397                      EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
 398             source_format = 0;
 399             break;
 400     case MESA_FORMAT_Z16:
 401 #ifdef MESA_BIG_ENDIAN
 402             endian = ENDIAN_8IN16;
 403 #endif
 404             format = COLOR_16;
 405             comp_swap = SWAP_STD;
 406             number_type = NUMBER_UNORM;
 407             SETfield(cb_color0_info,
 408                      ARRAY_1D_TILED_THIN1,
 409                      EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
 410                      EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
 411             source_format = 0;
 412             break;
 413     case MESA_FORMAT_Z32:
 414 #ifdef MESA_BIG_ENDIAN
 415             endian = ENDIAN_8IN32;
 416 #endif
 417             format = COLOR_32;
 418             comp_swap = SWAP_STD;
 419             number_type = NUMBER_UNORM;
 420             SETfield(cb_color0_info,
 421                      ARRAY_1D_TILED_THIN1,
 422                      EG_CB_COLOR0_INFO__ARRAY_MODE_shift,
 423                      EG_CB_COLOR0_INFO__ARRAY_MODE_mask);
 424             source_format = 0;
 425             break;
 426     case MESA_FORMAT_SARGB8:
 427 #ifdef MESA_BIG_ENDIAN
 428             endian = ENDIAN_8IN32;
 429 #endif
 430             format = COLOR_8_8_8_8;
 431             comp_swap = SWAP_ALT;
 432             number_type = NUMBER_SRGB;
 433             source_format = 1;
 434             break;
 435     case MESA_FORMAT_SLA8:
 436 #ifdef MESA_BIG_ENDIAN
 437             endian = ENDIAN_8IN16;
 438 #endif
 439             format = COLOR_8_8;
 440             comp_swap = SWAP_ALT_REV;
 441             number_type = NUMBER_SRGB;
 442             source_format = 1;
 443             break;
 444     case MESA_FORMAT_SL8:
 445             format = COLOR_8;
 446             comp_swap = SWAP_ALT_REV;
 447             number_type = NUMBER_SRGB;
 448             source_format = 1;
 449             break;
 450     default:
 451             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
 452             assert("Invalid format for US output\n");
 453             return;
 454     }
 455
 456     SETfield(cb_color0_info,
 457              endian,
 458              EG_CB_COLOR0_INFO__ENDIAN_shift,
 459              EG_CB_COLOR0_INFO__ENDIAN_mask);
 460     SETfield(cb_color0_info,
 461              format,
 462              EG_CB_COLOR0_INFO__FORMAT_shift,
 463              EG_CB_COLOR0_INFO__FORMAT_mask);
 464     SETfield(cb_color0_info,
 465              comp_swap,
 466              EG_CB_COLOR0_INFO__COMP_SWAP_shift,
 467              EG_CB_COLOR0_INFO__COMP_SWAP_mask);
 468     SETfield(cb_color0_info,
 469              number_type,
 470              EG_CB_COLOR0_INFO__NUMBER_TYPE_shift,
 471              EG_CB_COLOR0_INFO__NUMBER_TYPE_mask);
 472     SETfield(cb_color0_info,
 473              source_format,
 474              EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift,
 475              EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask);
 476
 477     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 478     EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_BASE + (4 * id), 1);
 479     R600_OUT_BATCH(cb_color0_base);
 480     R600_OUT_BATCH_RELOC(cb_color0_base,
 481                          bo,
 482                          cb_color0_base,
 483                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 484     END_BATCH();
 485
 486     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 487     EVERGREEN_OUT_BATCH_REGVAL(EG_CB_COLOR0_INFO, cb_color0_info);
 488     R600_OUT_BATCH_RELOC(cb_color0_info,
 489                          bo,
 490                          cb_color0_info,
 491                          0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 492     END_BATCH();
 493
 494     BEGIN_BATCH_NO_AUTOSTATE(5);
 495     EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_PITCH, 3);
 496     R600_OUT_BATCH(cb_color0_pitch);
 497     R600_OUT_BATCH(cb_color0_slice);
 498     R600_OUT_BATCH(0);
 499     END_BATCH();
 500
 501     BEGIN_BATCH_NO_AUTOSTATE(4);
 502     EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2);
 503     R600_OUT_BATCH(cb_color0_attrib);
 504     R600_OUT_BATCH(0);
 505     /*
 506     R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK.u32All);
 507     R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_CMASK_SLICE.u32All);
 508     R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK.u32All);
 509     R600_OUT_BATCH(evergreen->render_target[id].CB_COLOR0_FMASK_SLICE.u32All);
 510     */
 511     END_BATCH();
 512
 513     COMMIT_BATCH();
 514
 515 }
 516
 517 static inline void eg_load_shaders(struct gl_context * ctx)
 518 {
 519
 520     radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
 521     context_t *context = EVERGREEN_CONTEXT(ctx);
 522     int i, size;
 523     uint32_t *shader;
 524
 525     if (context->blit_bo_loaded == 1)
 526         return;
 527
 528     size = 4096;
 529     context->blit_bo = radeon_bo_open(radeonctx->radeonScreen->bom, 0,
 530                                       size, 256, RADEON_GEM_DOMAIN_GTT, 0);
 531     radeon_bo_map(context->blit_bo, 1);
 532     shader = context->blit_bo->ptr;
 533
 534     for(i=0; i<sizeof(evergreen_vs)/4; i++) {
 535             shader[128+i] = CPU_TO_LE32(evergreen_vs[i]);
 536     }
 537     for(i=0; i<sizeof(evergreen_ps)/4; i++) {
 538             shader[256+i] = CPU_TO_LE32(evergreen_ps[i]);
 539     }
 540
 541     radeon_bo_unmap(context->blit_bo);
 542     context->blit_bo_loaded = 1;
 543
 544 }
 545
 546 static inline void
 547 eg_set_shaders(context_t *context)
 548 {
 549     struct radeon_bo * pbo = context->blit_bo;
 550     uint32_t sq_pgm_start_fs = (512 >> 8);
 551     uint32_t sq_pgm_resources_fs = 0;
 552
 553     uint32_t sq_pgm_start_vs = (512 >> 8);
 554     uint32_t sq_pgm_resources_vs = (2 << NUM_GPRS_shift);
 555
 556     uint32_t sq_pgm_start_ps = (1024 >> 8);
 557     uint32_t sq_pgm_resources_ps = (1 << NUM_GPRS_shift);
 558     uint32_t sq_pgm_exports_ps = (1 << 1);
 559     BATCH_LOCALS(&context->radeon);
 560
 561     r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 562
 563     /* FS */
 564     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 565     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_FS, 1);
 566     R600_OUT_BATCH(sq_pgm_start_fs);
 567     R600_OUT_BATCH_RELOC(sq_pgm_start_fs,
 568                          pbo,
 569                          sq_pgm_start_fs,
 570                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 571     END_BATCH();
 572
 573     BEGIN_BATCH_NO_AUTOSTATE(3);
 574     EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_PGM_RESOURCES_FS, sq_pgm_resources_fs);
 575     END_BATCH();
 576
 577     /* VS */
 578     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 579     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_VS, 1);
 580     R600_OUT_BATCH(sq_pgm_start_vs);
 581     R600_OUT_BATCH_RELOC(sq_pgm_start_vs,
 582                          pbo,
 583                          sq_pgm_start_vs,
 584                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 585     END_BATCH();
 586
 587     BEGIN_BATCH_NO_AUTOSTATE(4);
 588     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_VS, 2);
 589     R600_OUT_BATCH(sq_pgm_resources_vs);
 590     R600_OUT_BATCH(0);
 591     END_BATCH();
 592
 593     /* PS */
 594     BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
 595     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_START_PS, 1);
 596     R600_OUT_BATCH(sq_pgm_start_ps);
 597     R600_OUT_BATCH_RELOC(sq_pgm_start_ps,
 598                          pbo,
 599                          sq_pgm_start_ps,
 600                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 601     END_BATCH();
 602
 603     BEGIN_BATCH_NO_AUTOSTATE(5);
 604     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_PGM_RESOURCES_PS, 3);
 605     R600_OUT_BATCH(sq_pgm_resources_ps);
 606     R600_OUT_BATCH(0);
 607     R600_OUT_BATCH(sq_pgm_exports_ps);
 608     END_BATCH();
 609
 610     COMMIT_BATCH();
 611
 612 }
 613
 614 static inline void
 615 eg_set_vtx_resource(context_t *context)
 616 {
 617     struct radeon_bo *bo = context->blit_bo;
 618     uint32_t sq_vtx_constant_word3 = 0;
 619     uint32_t sq_vtx_constant_word2 = 0;
 620     BATCH_LOCALS(&context->radeon);
 621
 622     BEGIN_BATCH_NO_AUTOSTATE(6);
 623     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 624     R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
 625     R600_OUT_BATCH(0);
 626
 627     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
 628     R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
 629     R600_OUT_BATCH(0);
 630     END_BATCH();
 631
 632     if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR)
 633             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
 634     else
 635             r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 636
 637     SETfield(sq_vtx_constant_word3, SQ_SEL_X,
 638              EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift,
 639         EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask);
 640     SETfield(sq_vtx_constant_word3, SQ_SEL_Y,
 641              EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift,
 642              EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask);
 643     SETfield(sq_vtx_constant_word3, SQ_SEL_Z,
 644              EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift,
 645              EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask);
 646     SETfield(sq_vtx_constant_word3, SQ_SEL_W,
 647              EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift,
 648              EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask);
 649
 650     sq_vtx_constant_word2 = 0
 651 #ifdef MESA_BIG_ENDIAN
 652             | (SQ_ENDIAN_8IN32 << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)
 653 #endif
 654             | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
 655
 656     BEGIN_BATCH_NO_AUTOSTATE(10 + 2);
 657
 658     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
 659     R600_OUT_BATCH(EG_SQ_FETCH_RESOURCE_VS_OFFSET * EG_FETCH_RESOURCE_STRIDE);
 660     R600_OUT_BATCH(0);
 661     R600_OUT_BATCH(48 - 1);
 662     R600_OUT_BATCH(sq_vtx_constant_word2);
 663     R600_OUT_BATCH(sq_vtx_constant_word3);
 664     R600_OUT_BATCH(0);
 665     R600_OUT_BATCH(0);
 666     R600_OUT_BATCH(0);
 667     R600_OUT_BATCH(SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift);
 668     R600_OUT_BATCH_RELOC(0,
 669                          bo,
 670                          0,
 671                          RADEON_GEM_DOMAIN_GTT, 0, 0);
 672     END_BATCH();
 673     COMMIT_BATCH();
 674
 675 }
 676
 677 static inline void
 678 eg_set_tex_resource(context_t * context,
 679                     gl_format mesa_format, struct radeon_bo *bo, int w, int h,
 680                     int TexelPitch, intptr_t src_offset)
 681 {
 682     uint32_t sq_tex_resource0, sq_tex_resource1, sq_tex_resource2, sq_tex_resource4, sq_tex_resource7;
 683
 684     sq_tex_resource0 = sq_tex_resource1 = sq_tex_resource2 = sq_tex_resource4 = sq_tex_resource7 = 0;
 685     BATCH_LOCALS(&context->radeon);
 686
 687     SETfield(sq_tex_resource0, SQ_TEX_DIM_2D, DIM_shift, DIM_mask);
 688     SETfield(sq_tex_resource0, ARRAY_LINEAR_GENERAL,
 689                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
 690                  SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
 691
 692     switch (mesa_format) {
 693     case MESA_FORMAT_RGBA8888:
 694     case MESA_FORMAT_SIGNED_RGBA8888:
 695             SETfield(sq_tex_resource7, FMT_8_8_8_8,
 696                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 697                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 698             SETfield(sq_tex_resource4, SQ_SEL_W,
 699                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 700             SETfield(sq_tex_resource4, SQ_SEL_Z,
 701                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 702             SETfield(sq_tex_resource4, SQ_SEL_Y,
 703                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 704             SETfield(sq_tex_resource4, SQ_SEL_X,
 705                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 706             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
 707                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 708                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 709                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 710                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 711                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 712                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 713                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 714                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 715             }
 716             break;
 717     case MESA_FORMAT_RGBA8888_REV:
 718     case MESA_FORMAT_SIGNED_RGBA8888_REV:
 719             SETfield(sq_tex_resource7, FMT_8_8_8_8,
 720                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 721                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 722             SETfield(sq_tex_resource4, SQ_SEL_X,
 723                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 724             SETfield(sq_tex_resource4, SQ_SEL_Y,
 725                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 726             SETfield(sq_tex_resource4, SQ_SEL_Z,
 727                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 728             SETfield(sq_tex_resource4, SQ_SEL_W,
 729                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 730             if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
 731                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 732                              FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
 733                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 734                              FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
 735                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 736                              FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
 737                     SETfield(sq_tex_resource4, SQ_FORMAT_COMP_SIGNED,
 738                              FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
 739             }
 740             break;
 741     case MESA_FORMAT_ARGB8888:
 742             SETfield(sq_tex_resource7, FMT_8_8_8_8,
 743                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 744                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 745             SETfield(sq_tex_resource4, SQ_SEL_Z,
 746                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 747             SETfield(sq_tex_resource4, SQ_SEL_Y,
 748                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 749             SETfield(sq_tex_resource4, SQ_SEL_X,
 750                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 751             SETfield(sq_tex_resource4, SQ_SEL_W,
 752                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 753             break;
 754     case MESA_FORMAT_XRGB8888:
 755             SETfield(sq_tex_resource7, FMT_8_8_8_8,
 756                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 757                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 758             SETfield(sq_tex_resource4, SQ_SEL_Z,
 759                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 760             SETfield(sq_tex_resource4, SQ_SEL_Y,
 761                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 762             SETfield(sq_tex_resource4, SQ_SEL_X,
 763                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 764             SETfield(sq_tex_resource4, SQ_SEL_1,
 765                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 766             break;
 767     case MESA_FORMAT_ARGB8888_REV:
 768             SETfield(sq_tex_resource7, FMT_8_8_8_8,
 769                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 770                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 771             SETfield(sq_tex_resource4, SQ_SEL_Y,
 772                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 773             SETfield(sq_tex_resource4, SQ_SEL_Z,
 774                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 775             SETfield(sq_tex_resource4, SQ_SEL_W,
 776                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 777             SETfield(sq_tex_resource4, SQ_SEL_X,
 778                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 779             break;
 780     case MESA_FORMAT_XRGB8888_REV:
 781             SETfield(sq_tex_resource7, FMT_8_8_8_8,
 782                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 783                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 784             SETfield(sq_tex_resource4, SQ_SEL_1,
 785                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 786             SETfield(sq_tex_resource4, SQ_SEL_Z,
 787                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 788             SETfield(sq_tex_resource4, SQ_SEL_W,
 789                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 790             SETfield(sq_tex_resource4, SQ_SEL_X,
 791                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 792             break;
 793     case MESA_FORMAT_RGB565:
 794             SETfield(sq_tex_resource7, FMT_5_6_5,
 795                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 796                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 797             SETfield(sq_tex_resource4, SQ_SEL_Z,
 798                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 799             SETfield(sq_tex_resource4, SQ_SEL_Y,
 800                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 801             SETfield(sq_tex_resource4, SQ_SEL_X,
 802                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 803             SETfield(sq_tex_resource4, SQ_SEL_1,
 804                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 805             break;
 806     case MESA_FORMAT_RGB565_REV:
 807             SETfield(sq_tex_resource7, FMT_5_6_5,
 808                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 809                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 810             SETfield(sq_tex_resource4, SQ_SEL_X,
 811                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 812             SETfield(sq_tex_resource4, SQ_SEL_Y,
 813                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 814             SETfield(sq_tex_resource4, SQ_SEL_Z,
 815                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 816             SETfield(sq_tex_resource4, SQ_SEL_1,
 817                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 818             break;
 819     case MESA_FORMAT_ARGB4444:
 820             SETfield(sq_tex_resource7, FMT_4_4_4_4,
 821                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 822                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 823             SETfield(sq_tex_resource4, SQ_SEL_Z,
 824                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 825             SETfield(sq_tex_resource4, SQ_SEL_Y,
 826                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 827             SETfield(sq_tex_resource4, SQ_SEL_X,
 828                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 829             SETfield(sq_tex_resource4, SQ_SEL_W,
 830                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 831             break;
 832     case MESA_FORMAT_ARGB4444_REV:
 833             SETfield(sq_tex_resource7, FMT_4_4_4_4,
 834                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 835                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 836             SETfield(sq_tex_resource4, SQ_SEL_Y,
 837                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 838             SETfield(sq_tex_resource4, SQ_SEL_Z,
 839                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 840             SETfield(sq_tex_resource4, SQ_SEL_W,
 841                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 842             SETfield(sq_tex_resource4, SQ_SEL_X,
 843                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 844             break;
 845     case MESA_FORMAT_ARGB1555:
 846             SETfield(sq_tex_resource7, FMT_1_5_5_5,
 847                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 848                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 849             SETfield(sq_tex_resource4, SQ_SEL_Z,
 850                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 851             SETfield(sq_tex_resource4, SQ_SEL_Y,
 852                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 853             SETfield(sq_tex_resource4, SQ_SEL_X,
 854                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 855             SETfield(sq_tex_resource4, SQ_SEL_W,
 856                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 857             break;
 858     case MESA_FORMAT_ARGB1555_REV:
 859             SETfield(sq_tex_resource7, FMT_1_5_5_5,
 860                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 861                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 862             SETfield(sq_tex_resource4, SQ_SEL_Y,
 863                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 864             SETfield(sq_tex_resource4, SQ_SEL_Z,
 865                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 866             SETfield(sq_tex_resource4, SQ_SEL_W,
 867                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 868             SETfield(sq_tex_resource4, SQ_SEL_X,
 869                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 870             break;
 871     case MESA_FORMAT_AL88:
 872     case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
 873             SETfield(sq_tex_resource7, FMT_8_8,
 874                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 875                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 876             SETfield(sq_tex_resource4, SQ_SEL_X,
 877                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 878             SETfield(sq_tex_resource4, SQ_SEL_X,
 879                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 880             SETfield(sq_tex_resource4, SQ_SEL_X,
 881                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 882             SETfield(sq_tex_resource4, SQ_SEL_Y,
 883                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 884             break;
 885     case MESA_FORMAT_RGB332:
 886             SETfield(sq_tex_resource7, FMT_3_3_2,
 887                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 888                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 889             SETfield(sq_tex_resource4, SQ_SEL_Z,
 890                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 891             SETfield(sq_tex_resource4, SQ_SEL_Y,
 892                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 893             SETfield(sq_tex_resource4, SQ_SEL_X,
 894                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 895             SETfield(sq_tex_resource4, SQ_SEL_1,
 896                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 897             break;
 898     case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
 899             SETfield(sq_tex_resource7, FMT_8,
 900                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 901                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 902             SETfield(sq_tex_resource4, SQ_SEL_0,
 903                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 904             SETfield(sq_tex_resource4, SQ_SEL_0,
 905                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 906             SETfield(sq_tex_resource4, SQ_SEL_0,
 907                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 908             SETfield(sq_tex_resource4, SQ_SEL_X,
 909                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 910             break;
 911     case MESA_FORMAT_L8: /* X, X, X, ONE */
 912             SETfield(sq_tex_resource7, FMT_8,
 913                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 914                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 915             SETfield(sq_tex_resource4, SQ_SEL_X,
 916                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 917             SETfield(sq_tex_resource4, SQ_SEL_X,
 918                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 919             SETfield(sq_tex_resource4, SQ_SEL_X,
 920                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 921             SETfield(sq_tex_resource4, SQ_SEL_1,
 922                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 923             break;
 924     case MESA_FORMAT_I8: /* X, X, X, X */
 925     case MESA_FORMAT_CI8:
 926             SETfield(sq_tex_resource7, FMT_8,
 927                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 928                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 929             SETfield(sq_tex_resource4, SQ_SEL_X,
 930                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 931             SETfield(sq_tex_resource4, SQ_SEL_X,
 932                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 933             SETfield(sq_tex_resource4, SQ_SEL_X,
 934                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 935             SETfield(sq_tex_resource4, SQ_SEL_X,
 936                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 937             break;
 938     case MESA_FORMAT_RGBA_FLOAT32:
 939             SETfield(sq_tex_resource7, FMT_32_32_32_32_FLOAT,
 940                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 941                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 942             SETfield(sq_tex_resource4, SQ_SEL_X,
 943                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 944             SETfield(sq_tex_resource4, SQ_SEL_Y,
 945                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 946             SETfield(sq_tex_resource4, SQ_SEL_Z,
 947                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 948             SETfield(sq_tex_resource4, SQ_SEL_W,
 949                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 950             break;
 951     case MESA_FORMAT_RGBA_FLOAT16:
 952             SETfield(sq_tex_resource7, FMT_16_16_16_16_FLOAT,
 953                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 954                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 955             SETfield(sq_tex_resource4, SQ_SEL_X,
 956                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 957             SETfield(sq_tex_resource4, SQ_SEL_Y,
 958                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 959             SETfield(sq_tex_resource4, SQ_SEL_Z,
 960                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 961             SETfield(sq_tex_resource4, SQ_SEL_W,
 962                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 963             break;
 964     case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
 965             SETfield(sq_tex_resource7, FMT_32_FLOAT,
 966                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 967                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 968             SETfield(sq_tex_resource4, SQ_SEL_0,
 969                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 970             SETfield(sq_tex_resource4, SQ_SEL_0,
 971                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 972             SETfield(sq_tex_resource4, SQ_SEL_0,
 973                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 974             SETfield(sq_tex_resource4, SQ_SEL_X,
 975                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 976             break;
 977     case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
 978             SETfield(sq_tex_resource7, FMT_16_FLOAT,
 979                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 980                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 981             SETfield(sq_tex_resource4, SQ_SEL_0,
 982                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 983             SETfield(sq_tex_resource4, SQ_SEL_0,
 984                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 985             SETfield(sq_tex_resource4, SQ_SEL_0,
 986                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
 987             SETfield(sq_tex_resource4, SQ_SEL_X,
 988                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 989             break;
 990     case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
 991             SETfield(sq_tex_resource7, FMT_32_FLOAT,
 992                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
 993                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
 994             SETfield(sq_tex_resource4, SQ_SEL_X,
 995                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
 996             SETfield(sq_tex_resource4, SQ_SEL_X,
 997                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
 998             SETfield(sq_tex_resource4, SQ_SEL_X,
 999                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1000             SETfield(sq_tex_resource4, SQ_SEL_1,
1001                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1002             break;
1003     case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
1004             SETfield(sq_tex_resource7, FMT_16_FLOAT,
1005                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1006                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1007             SETfield(sq_tex_resource4, SQ_SEL_X,
1008                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1009             SETfield(sq_tex_resource4, SQ_SEL_X,
1010                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1011             SETfield(sq_tex_resource4, SQ_SEL_X,
1012                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1013             SETfield(sq_tex_resource4, SQ_SEL_1,
1014                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1015             break;
1016     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
1017             SETfield(sq_tex_resource7, FMT_32_32_FLOAT,
1018                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1019                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1020             SETfield(sq_tex_resource4, SQ_SEL_X,
1021                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1022             SETfield(sq_tex_resource4, SQ_SEL_X,
1023                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1024             SETfield(sq_tex_resource4, SQ_SEL_X,
1025                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1026             SETfield(sq_tex_resource4, SQ_SEL_Y,
1027                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1028             break;
1029     case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
1030             SETfield(sq_tex_resource7, FMT_16_16_FLOAT,
1031                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1032                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1033             SETfield(sq_tex_resource4, SQ_SEL_X,
1034                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1035             SETfield(sq_tex_resource4, SQ_SEL_X,
1036                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1037             SETfield(sq_tex_resource4, SQ_SEL_X,
1038                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1039             SETfield(sq_tex_resource4, SQ_SEL_Y,
1040                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1041             break;
1042     case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
1043             SETfield(sq_tex_resource7, FMT_32_FLOAT,
1044                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1045                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1046             SETfield(sq_tex_resource4, SQ_SEL_X,
1047                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1048             SETfield(sq_tex_resource4, SQ_SEL_X,
1049                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1050             SETfield(sq_tex_resource4, SQ_SEL_X,
1051                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1052             SETfield(sq_tex_resource4, SQ_SEL_X,
1053                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1054             break;
1055     case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
1056             SETfield(sq_tex_resource7, FMT_16_FLOAT,
1057                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1058                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1059             SETfield(sq_tex_resource4, SQ_SEL_X,
1060                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1061             SETfield(sq_tex_resource4, SQ_SEL_X,
1062                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1063             SETfield(sq_tex_resource4, SQ_SEL_X,
1064                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1065             SETfield(sq_tex_resource4, SQ_SEL_X,
1066                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1067             break;
1068     case MESA_FORMAT_Z16:
1069             /* ??? */
1070             CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1071             SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1072                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1073                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1074             SETfield(sq_tex_resource7, FMT_16,
1075                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1076                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1077             SETfield(sq_tex_resource4, SQ_SEL_X,
1078                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1079             SETfield(sq_tex_resource4, SQ_SEL_X,
1080                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1081             SETfield(sq_tex_resource4, SQ_SEL_X,
1082                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1083             SETfield(sq_tex_resource4, SQ_SEL_X,
1084                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1085             break;
1086     case MESA_FORMAT_X8_Z24:
1087             /* ??? */
1088             CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1089             SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1090                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1091                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1092             SETfield(sq_tex_resource7, FMT_8_24,
1093                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1094                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1095             SETfield(sq_tex_resource4, SQ_SEL_X,
1096                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1097             SETfield(sq_tex_resource4, SQ_SEL_1,
1098                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1099             SETfield(sq_tex_resource4, SQ_SEL_0,
1100                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1101             SETfield(sq_tex_resource4, SQ_SEL_1,
1102                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1103             break;
1104     case MESA_FORMAT_S8_Z24:
1105             /* ??? */
1106             CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1107             SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1108                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1109                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1110             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1111             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1112                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1113                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1114             SETfield(sq_tex_resource7, FMT_8_24,
1115                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1116                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1117             SETfield(sq_tex_resource4, SQ_SEL_X,
1118                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1119             SETfield(sq_tex_resource4, SQ_SEL_Y,
1120                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1121             SETfield(sq_tex_resource4, SQ_SEL_0,
1122                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1123             SETfield(sq_tex_resource4, SQ_SEL_1,
1124                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1125             break;
1126     case MESA_FORMAT_Z24_S8:
1127             /* ??? */
1128             CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1129             SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1130                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1131                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1132             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1133             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1134                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1135                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1136             SETfield(sq_tex_resource7, FMT_24_8,
1137                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1138                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1139             SETfield(sq_tex_resource4, SQ_SEL_X,
1140                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1141             SETfield(sq_tex_resource4, SQ_SEL_Y,
1142                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1143             SETfield(sq_tex_resource4, SQ_SEL_0,
1144                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1145             SETfield(sq_tex_resource4, SQ_SEL_1,
1146                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1147             break;
1148     case MESA_FORMAT_Z32:
1149             /* ??? */
1150             CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1151             SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1152                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1153                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1154             SETbit(sq_tex_resource0, TILE_TYPE_bit);
1155             SETfield(sq_tex_resource0, ARRAY_1D_TILED_THIN1,
1156                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_shift,
1157                      SQ_TEX_RESOURCE_WORD0_0__TILE_MODE_mask);
1158             SETfield(sq_tex_resource7, FMT_32,
1159                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1160                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1161             SETfield(sq_tex_resource4, SQ_SEL_X,
1162                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1163             SETfield(sq_tex_resource4, SQ_SEL_X,
1164                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1165             SETfield(sq_tex_resource4, SQ_SEL_X,
1166                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1167             SETfield(sq_tex_resource4, SQ_SEL_X,
1168                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1169             break;
1170     case MESA_FORMAT_S8:
1171             /* ??? */
1172             CLEARbit(sq_tex_resource0, EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit);
1173             SETfield(sq_tex_resource1, ARRAY_1D_TILED_THIN1,
1174                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift,
1175                      EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask);
1176             SETfield(sq_tex_resource7, FMT_8,
1177                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1178                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1179             SETfield(sq_tex_resource4, SQ_SEL_X,
1180                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1181             SETfield(sq_tex_resource4, SQ_SEL_X,
1182                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1183             SETfield(sq_tex_resource4, SQ_SEL_X,
1184                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1185             SETfield(sq_tex_resource4, SQ_SEL_X,
1186                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1187             break;
1188     case MESA_FORMAT_SARGB8:
1189             SETfield(sq_tex_resource7, FMT_8_8_8_8,
1190                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1191                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1192             SETfield(sq_tex_resource4, SQ_SEL_Z,
1193                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1194             SETfield(sq_tex_resource4, SQ_SEL_Y,
1195                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1196             SETfield(sq_tex_resource4, SQ_SEL_X,
1197                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1198             SETfield(sq_tex_resource4, SQ_SEL_W,
1199                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1200             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1201             break;
1202     case MESA_FORMAT_SLA8:
1203             SETfield(sq_tex_resource7, FMT_8_8,
1204                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1205                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1206             SETfield(sq_tex_resource4, SQ_SEL_X,
1207                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1208             SETfield(sq_tex_resource4, SQ_SEL_X,
1209                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1210             SETfield(sq_tex_resource4, SQ_SEL_X,
1211                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1212             SETfield(sq_tex_resource4, SQ_SEL_Y,
1213                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1214             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1215             break;
1216     case MESA_FORMAT_SL8: /* X, X, X, ONE */
1217             SETfield(sq_tex_resource7, FMT_8,
1218                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift,
1219                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
1220             SETfield(sq_tex_resource4, SQ_SEL_X,
1221                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
1222             SETfield(sq_tex_resource4, SQ_SEL_X,
1223                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
1224             SETfield(sq_tex_resource4, SQ_SEL_X,
1225                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
1226             SETfield(sq_tex_resource4, SQ_SEL_1,
1227                      SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
1228             SETbit(sq_tex_resource4, SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA_bit);
1229             break;
1230     default:
1231             fprintf(stderr,"Invalid format for copy %s\n",_mesa_get_format_name(mesa_format));
1232             assert("Invalid format for US output\n");
1233             return;
1234     };
1235
1236     SETfield(sq_tex_resource0, (TexelPitch/8)-1,
1237              EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift,
1238              EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask);
1239     SETfield(sq_tex_resource0, w - 1,
1240              EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift,
1241              EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask);
1242     SETfield(sq_tex_resource1, h - 1,
1243              EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift,
1244              EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask);
1245
1246     sq_tex_resource2 = src_offset / 256;
1247
1248     SETfield(sq_tex_resource7, SQ_TEX_VTX_VALID_TEXTURE,
1249              SQ_TEX_RESOURCE_WORD6_0__TYPE_shift,
1250              SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
1251
1252     r700SyncSurf(context, bo,
1253                  RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
1254                  0, TC_ACTION_ENA_bit);
1255
1256     BEGIN_BATCH_NO_AUTOSTATE(10 + 4);
1257     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 8));
1258     R600_OUT_BATCH(0 * 7);
1259     R600_OUT_BATCH(sq_tex_resource0);
1260     R600_OUT_BATCH(sq_tex_resource1);
1261     R600_OUT_BATCH(sq_tex_resource2);
1262     R600_OUT_BATCH(0);
1263     R600_OUT_BATCH(sq_tex_resource4);
1264     R600_OUT_BATCH(0);
1265     R600_OUT_BATCH(0);
1266     R600_OUT_BATCH(sq_tex_resource7);
1267     R600_OUT_BATCH_RELOC(0,
1268                      bo,
1269                      0,
1270                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1271     R600_OUT_BATCH_RELOC(0,
1272                      bo,
1273                      0,
1274                      RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
1275     END_BATCH();
1276     COMMIT_BATCH();
1277 }
1278
1279 static inline void
1280 eg_set_tex_sampler(context_t * context)
1281 {
1282     uint32_t sq_tex_sampler_word0 = 0, sq_tex_sampler_word1 = 0, sq_tex_sampler_word2 = 0;
1283     int i = 0;
1284
1285     SETbit(sq_tex_sampler_word2, EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
1286
1287     BATCH_LOCALS(&context->radeon);
1288
1289     BEGIN_BATCH_NO_AUTOSTATE(5);
1290     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
1291     R600_OUT_BATCH(i * 3);
1292     R600_OUT_BATCH(sq_tex_sampler_word0);
1293     R600_OUT_BATCH(sq_tex_sampler_word1);
1294     R600_OUT_BATCH(sq_tex_sampler_word2);
1295     END_BATCH();
1296
1297 }
1298
1299 static inline void
1300 eg_set_scissors(context_t *context, int x1, int y1, int x2, int y2)
1301 {
1302     BATCH_LOCALS(&context->radeon);
1303
1304     BEGIN_BATCH_NO_AUTOSTATE(17);
1305     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_SCREEN_SCISSOR_TL, 2);
1306     R600_OUT_BATCH((x1 << 0) | (y1 << 16));
1307     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1308
1309     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_WINDOW_OFFSET, 3);
1310     R600_OUT_BATCH(0); //PA_SC_WINDOW_OFFSET
1311     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit)); //PA_SC_WINDOW_SCISSOR_TL
1312     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1313
1314     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_GENERIC_SCISSOR_TL, 2);
1315     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1316     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1317
1318     /* XXX 16 of these PA_SC_VPORT_SCISSOR_0_TL_num ... */
1319     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_SCISSOR_0_TL, 2);
1320     R600_OUT_BATCH((x1 << 0) | (y1 << 16) | (WINDOW_OFFSET_DISABLE_bit));
1321     R600_OUT_BATCH((x2 << 0) | (y2 << 16));
1322     END_BATCH();
1323
1324     COMMIT_BATCH();
1325
1326 }
1327
1328 static inline void
1329 eg_set_vb_data(context_t * context, int src_x, int src_y, int dst_x, int dst_y,
1330                int w, int h, int src_h, unsigned flip_y)
1331 {
1332     float *vb;
1333     radeon_bo_map(context->blit_bo, 1);
1334     vb = context->blit_bo->ptr;
1335
1336     vb[0] = (float)(dst_x);
1337     vb[1] = (float)(dst_y);
1338     vb[2] = (float)(src_x);
1339     vb[3] = (flip_y) ? (float)(src_h - src_y) : (float)src_y;
1340
1341     vb[4] = (float)(dst_x);
1342     vb[5] = (float)(dst_y + h);
1343     vb[6] = (float)(src_x);
1344     vb[7] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1345
1346     vb[8] = (float)(dst_x + w);
1347     vb[9] = (float)(dst_y + h);
1348     vb[10] = (float)(src_x + w);
1349     vb[11] = (flip_y) ? (float)(src_h - (src_y + h)) : (float)(src_y + h);
1350
1351     radeon_bo_unmap(context->blit_bo);
1352
1353 }
1354
1355 static inline void
1356 eg_draw_auto(context_t *context)
1357 {
1358     BATCH_LOCALS(&context->radeon);
1359     uint32_t vgt_primitive_type = 0, vgt_index_type = 0, vgt_draw_initiator = 0, vgt_num_indices;
1360
1361     SETfield(vgt_primitive_type, DI_PT_RECTLIST,
1362              VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift,
1363              VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
1364     SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift,
1365              INDEX_TYPE_mask);
1366     SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift,
1367              MAJOR_MODE_mask);
1368     SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift,
1369              SOURCE_SELECT_mask);
1370
1371     vgt_num_indices = 3;
1372
1373     BEGIN_BATCH_NO_AUTOSTATE(10);
1374     // prim
1375     EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_PRIMITIVE_TYPE, 1);
1376     R600_OUT_BATCH(vgt_primitive_type);
1377     // index type
1378     R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
1379     R600_OUT_BATCH(vgt_index_type);
1380     // num instances
1381     R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
1382     R600_OUT_BATCH(1);
1383     //
1384     R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
1385     R600_OUT_BATCH(vgt_num_indices);
1386     R600_OUT_BATCH(vgt_draw_initiator);
1387
1388     END_BATCH();
1389     COMMIT_BATCH();
1390 }
1391
1392 static inline void
1393 eg_set_default_state(context_t *context)
1394 {
1395     int num_ps_gprs;
1396     int num_vs_gprs;
1397     int num_gs_gprs;
1398     int num_es_gprs;
1399     int num_hs_gprs;
1400     int num_ls_gprs;
1401     int num_temp_gprs;
1402     int num_ps_threads;
1403     int num_vs_threads;
1404     int num_gs_threads;
1405     int num_es_threads;
1406     int num_hs_threads;
1407     int num_ls_threads;
1408     int num_ps_stack_entries;
1409     int num_vs_stack_entries;
1410     int num_gs_stack_entries;
1411     int num_es_stack_entries;
1412     int num_hs_stack_entries;
1413     int num_ls_stack_entries;
1414     uint32_t sq_config = 0, sq_gpr_resource_mgmt_1 = 0, sq_gpr_resource_mgmt_2 = 0;
1415     uint32_t sq_gpr_resource_mgmt_3 = 0;
1416     uint32_t sq_thread_resource_mgmt = 0, sq_thread_resource_mgmt_2 = 0;
1417     uint32_t sq_stack_resource_mgmt_1 = 0, sq_stack_resource_mgmt_2 = 0, sq_stack_resource_mgmt_3 = 0;
1418     BATCH_LOCALS(&context->radeon);
1419
1420     switch (context->radeon.radeonScreen->chip_family) {
1421     case CHIP_FAMILY_CEDAR:
1422     default:
1423             num_ps_gprs = 93;
1424             num_vs_gprs = 46;
1425             num_temp_gprs = 4;
1426             num_gs_gprs = 31;
1427             num_es_gprs = 31;
1428             num_hs_gprs = 23;
1429             num_ls_gprs = 23;
1430             num_ps_threads = 96;
1431             num_vs_threads = 16;
1432             num_gs_threads = 16;
1433             num_es_threads = 16;
1434             num_hs_threads = 16;
1435             num_ls_threads = 16;
1436             num_ps_stack_entries = 42;
1437             num_vs_stack_entries = 42;
1438             num_gs_stack_entries = 42;
1439             num_es_stack_entries = 42;
1440             num_hs_stack_entries = 42;
1441             num_ls_stack_entries = 42;
1442             break;
1443     case CHIP_FAMILY_REDWOOD:
1444             num_ps_gprs = 93;
1445             num_vs_gprs = 46;
1446             num_temp_gprs = 4;
1447             num_gs_gprs = 31;
1448             num_es_gprs = 31;
1449             num_hs_gprs = 23;
1450             num_ls_gprs = 23;
1451             num_ps_threads = 128;
1452             num_vs_threads = 20;
1453             num_gs_threads = 20;
1454             num_es_threads = 20;
1455             num_hs_threads = 20;
1456             num_ls_threads = 20;
1457             num_ps_stack_entries = 42;
1458             num_vs_stack_entries = 42;
1459             num_gs_stack_entries = 42;
1460             num_es_stack_entries = 42;
1461             num_hs_stack_entries = 42;
1462             num_ls_stack_entries = 42;
1463             break;
1464     case CHIP_FAMILY_JUNIPER:
1465             num_ps_gprs = 93;
1466             num_vs_gprs = 46;
1467             num_temp_gprs = 4;
1468             num_gs_gprs = 31;
1469             num_es_gprs = 31;
1470             num_hs_gprs = 23;
1471             num_ls_gprs = 23;
1472             num_ps_threads = 128;
1473             num_vs_threads = 20;
1474             num_gs_threads = 20;
1475             num_es_threads = 20;
1476             num_hs_threads = 20;
1477             num_ls_threads = 20;
1478             num_ps_stack_entries = 85;
1479             num_vs_stack_entries = 85;
1480             num_gs_stack_entries = 85;
1481             num_es_stack_entries = 85;
1482             num_hs_stack_entries = 85;
1483             num_ls_stack_entries = 85;
1484             break;
1485     case CHIP_FAMILY_CYPRESS:
1486     case CHIP_FAMILY_HEMLOCK:
1487             num_ps_gprs = 93;
1488             num_vs_gprs = 46;
1489             num_temp_gprs = 4;
1490             num_gs_gprs = 31;
1491             num_es_gprs = 31;
1492             num_hs_gprs = 23;
1493             num_ls_gprs = 23;
1494             num_ps_threads = 128;
1495             num_vs_threads = 20;
1496             num_gs_threads = 20;
1497             num_es_threads = 20;
1498             num_hs_threads = 20;
1499             num_ls_threads = 20;
1500             num_ps_stack_entries = 85;
1501             num_vs_stack_entries = 85;
1502             num_gs_stack_entries = 85;
1503             num_es_stack_entries = 85;
1504             num_hs_stack_entries = 85;
1505             num_ls_stack_entries = 85;
1506             break;
1507     case CHIP_FAMILY_PALM:
1508             num_ps_gprs = 93;
1509             num_vs_gprs = 46;
1510             num_temp_gprs = 4;
1511             num_gs_gprs = 31;
1512             num_es_gprs = 31;
1513             num_hs_gprs = 23;
1514             num_ls_gprs = 23;
1515             num_ps_threads = 96;
1516             num_vs_threads = 16;
1517             num_gs_threads = 16;
1518             num_es_threads = 16;
1519             num_hs_threads = 16;
1520             num_ls_threads = 16;
1521             num_ps_stack_entries = 42;
1522             num_vs_stack_entries = 42;
1523             num_gs_stack_entries = 42;
1524             num_es_stack_entries = 42;
1525             num_hs_stack_entries = 42;
1526             num_ls_stack_entries = 42;
1527             break;
1528     case CHIP_FAMILY_SUMO:
1529             num_ps_gprs = 93;
1530             num_vs_gprs = 46;
1531             num_temp_gprs = 4;
1532             num_gs_gprs = 31;
1533             num_es_gprs = 31;
1534             num_hs_gprs = 23;
1535             num_ls_gprs = 23;
1536             num_ps_threads = 96;
1537             num_vs_threads = 25;
1538             num_gs_threads = 25;
1539             num_es_threads = 25;
1540             num_hs_threads = 25;
1541             num_ls_threads = 25;
1542             num_ps_stack_entries = 42;
1543             num_vs_stack_entries = 42;
1544             num_gs_stack_entries = 42;
1545             num_es_stack_entries = 42;
1546             num_hs_stack_entries = 42;
1547             num_ls_stack_entries = 42;
1548             break;
1549     case CHIP_FAMILY_SUMO2:
1550             num_ps_gprs = 93;
1551             num_vs_gprs = 46;
1552             num_temp_gprs = 4;
1553             num_gs_gprs = 31;
1554             num_es_gprs = 31;
1555             num_hs_gprs = 23;
1556             num_ls_gprs = 23;
1557             num_ps_threads = 96;
1558             num_vs_threads = 25;
1559             num_gs_threads = 25;
1560             num_es_threads = 25;
1561             num_hs_threads = 25;
1562             num_ls_threads = 25;
1563             num_ps_stack_entries = 85;
1564             num_vs_stack_entries = 85;
1565             num_gs_stack_entries = 85;
1566             num_es_stack_entries = 85;
1567             num_hs_stack_entries = 85;
1568             num_ls_stack_entries = 85;
1569             break;
1570     case CHIP_FAMILY_BARTS:
1571             num_ps_gprs = 93;
1572             num_vs_gprs = 46;
1573             num_temp_gprs = 4;
1574             num_gs_gprs = 31;
1575             num_es_gprs = 31;
1576             num_hs_gprs = 23;
1577             num_ls_gprs = 23;
1578             num_ps_threads = 128;
1579             num_vs_threads = 20;
1580             num_gs_threads = 20;
1581             num_es_threads = 20;
1582             num_hs_threads = 20;
1583             num_ls_threads = 20;
1584             num_ps_stack_entries = 85;
1585             num_vs_stack_entries = 85;
1586             num_gs_stack_entries = 85;
1587             num_es_stack_entries = 85;
1588             num_hs_stack_entries = 85;
1589             num_ls_stack_entries = 85;
1590             break;
1591     case CHIP_FAMILY_TURKS:
1592             num_ps_gprs = 93;
1593             num_vs_gprs = 46;
1594             num_temp_gprs = 4;
1595             num_gs_gprs = 31;
1596             num_es_gprs = 31;
1597             num_hs_gprs = 23;
1598             num_ls_gprs = 23;
1599             num_ps_threads = 128;
1600             num_vs_threads = 20;
1601             num_gs_threads = 20;
1602             num_es_threads = 20;
1603             num_hs_threads = 20;
1604             num_ls_threads = 20;
1605             num_ps_stack_entries = 42;
1606             num_vs_stack_entries = 42;
1607             num_gs_stack_entries = 42;
1608             num_es_stack_entries = 42;
1609             num_hs_stack_entries = 42;
1610             num_ls_stack_entries = 42;
1611             break;
1612     case CHIP_FAMILY_CAICOS:
1613             num_ps_gprs = 93;
1614             num_vs_gprs = 46;
1615             num_temp_gprs = 4;
1616             num_gs_gprs = 31;
1617             num_es_gprs = 31;
1618             num_hs_gprs = 23;
1619             num_ls_gprs = 23;
1620             num_ps_threads = 128;
1621             num_vs_threads = 10;
1622             num_gs_threads = 10;
1623             num_es_threads = 10;
1624             num_hs_threads = 10;
1625             num_ls_threads = 10;
1626             num_ps_stack_entries = 42;
1627             num_vs_stack_entries = 42;
1628             num_gs_stack_entries = 42;
1629             num_es_stack_entries = 42;
1630             num_hs_stack_entries = 42;
1631             num_ls_stack_entries = 42;
1632             break;
1633     }
1634
1635     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) ||
1636         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_PALM) ||
1637         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO) ||
1638         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_SUMO2) ||
1639         (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CAICOS))
1640             CLEARbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit);
1641     else
1642             SETbit(sq_config, EG_SQ_CONFIG__VC_ENABLE_bit);
1643     SETbit(sq_config, EG_SQ_CONFIG__EXPORT_SRC_C_bit);
1644
1645     SETfield(sq_config, 0,
1646              EG_SQ_CONFIG__PS_PRIO_shift,
1647              EG_SQ_CONFIG__PS_PRIO_mask);
1648     SETfield(sq_config, 1,
1649              EG_SQ_CONFIG__VS_PRIO_shift,
1650              EG_SQ_CONFIG__VS_PRIO_mask);
1651     SETfield(sq_config, 2,
1652              EG_SQ_CONFIG__GS_PRIO_shift,
1653              EG_SQ_CONFIG__GS_PRIO_mask);
1654     SETfield(sq_config, 3,
1655              EG_SQ_CONFIG__ES_PRIO_shift,
1656              EG_SQ_CONFIG__ES_PRIO_mask);
1657
1658
1659     SETfield(sq_gpr_resource_mgmt_1, num_ps_gprs,
1660              NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1661     SETfield(sq_gpr_resource_mgmt_1, num_vs_gprs,
1662              NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1663     SETfield(sq_gpr_resource_mgmt_1, num_temp_gprs,
1664                  NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
1665     SETfield(sq_gpr_resource_mgmt_2, num_gs_gprs,
1666              NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
1667     SETfield(sq_gpr_resource_mgmt_2, num_es_gprs,
1668              NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
1669     SETfield(sq_gpr_resource_mgmt_3, num_hs_gprs,
1670              NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
1671     SETfield(sq_gpr_resource_mgmt_3, num_ls_gprs,
1672              NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
1673
1674     SETfield(sq_thread_resource_mgmt, num_ps_threads,
1675              NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1676     SETfield(sq_thread_resource_mgmt, num_vs_threads,
1677              NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1678     SETfield(sq_thread_resource_mgmt, num_gs_threads,
1679              NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
1680     SETfield(sq_thread_resource_mgmt, num_es_threads,
1681              NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
1682     SETfield(sq_thread_resource_mgmt_2, num_hs_threads,
1683              NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
1684     SETfield(sq_thread_resource_mgmt_2, num_ls_threads,
1685              NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
1686
1687     SETfield(sq_stack_resource_mgmt_1, num_ps_stack_entries,
1688              NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1689     SETfield(sq_stack_resource_mgmt_1, num_vs_stack_entries,
1690              NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1691     SETfield(sq_stack_resource_mgmt_2, num_gs_stack_entries,
1692              NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
1693     SETfield(sq_stack_resource_mgmt_2, num_es_stack_entries,
1694              NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
1695     SETfield(sq_stack_resource_mgmt_3, num_hs_stack_entries,
1696              NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
1697     SETfield(sq_stack_resource_mgmt_3, num_ls_stack_entries,
1698              NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
1699
1700
1701     BEGIN_BATCH_NO_AUTOSTATE(196);
1702     //3
1703     EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1704     //6
1705     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_CONFIG, 4);
1706     R600_OUT_BATCH(sq_config);
1707     R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
1708     R600_OUT_BATCH(sq_gpr_resource_mgmt_2);
1709     R600_OUT_BATCH(sq_gpr_resource_mgmt_3);
1710     //7
1711     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_THREAD_RESOURCE_MGMT, 5);
1712     R600_OUT_BATCH(sq_thread_resource_mgmt);
1713     R600_OUT_BATCH(sq_thread_resource_mgmt_2);
1714     R600_OUT_BATCH(sq_stack_resource_mgmt_1);
1715     R600_OUT_BATCH(sq_stack_resource_mgmt_2);
1716     R600_OUT_BATCH(sq_stack_resource_mgmt_3);
1717     //3
1718     R600_OUT_BATCH(CP_PACKET3(R600_IT_CONTEXT_CONTROL, 1));
1719     R600_OUT_BATCH(0x80000000);
1720     R600_OUT_BATCH(0x80000000);
1721     //3
1722     EVERGREEN_OUT_BATCH_REGVAL(EG_SQ_LDS_ALLOC_PS, 0);
1723     //8
1724     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_ESGS_RING_ITEMSIZE, 6);
1725     R600_OUT_BATCH(0);
1726     R600_OUT_BATCH(0);
1727     R600_OUT_BATCH(0);
1728     R600_OUT_BATCH(0);
1729     R600_OUT_BATCH(0);
1730     R600_OUT_BATCH(0);
1731     //6
1732     EVERGREEN_OUT_BATCH_REGSEQ(EG_SQ_GS_VERT_ITEMSIZE, 4);
1733     R600_OUT_BATCH(0);
1734     R600_OUT_BATCH(0);
1735     R600_OUT_BATCH(0);
1736     R600_OUT_BATCH(0);
1737     //3
1738     EVERGREEN_OUT_BATCH_REGVAL(EG_DB_DEPTH_CONTROL, 0);
1739     //7
1740     EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_RENDER_CONTROL, 5);
1741     R600_OUT_BATCH(0x00000060);
1742     R600_OUT_BATCH(0);
1743     R600_OUT_BATCH(0);
1744     R600_OUT_BATCH(0x0000002a);
1745     R600_OUT_BATCH(0);
1746     //4
1747     EVERGREEN_OUT_BATCH_REGSEQ(EG_DB_STENCIL_CLEAR, 2);
1748     R600_OUT_BATCH(0);
1749     R600_OUT_BATCH(0);
1750     //3
1751     EVERGREEN_OUT_BATCH_REGVAL(EG_DB_ALPHA_TO_MASK, 0x0000aa00);
1752     //15
1753     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_CLIPRECT_RULE, 13);
1754     R600_OUT_BATCH(0x0000ffff);
1755     R600_OUT_BATCH(0x00000000);
1756     R600_OUT_BATCH(0x20002000);
1757     R600_OUT_BATCH(0x00000000);
1758     R600_OUT_BATCH(0x20002000);
1759     R600_OUT_BATCH(0x00000000);
1760     R600_OUT_BATCH(0x20002000);
1761     R600_OUT_BATCH(0x00000000);
1762     R600_OUT_BATCH(0x20002000);
1763     R600_OUT_BATCH(0xaaaaaaaa);
1764     R600_OUT_BATCH(0);
1765     R600_OUT_BATCH(0x0000000f);
1766     R600_OUT_BATCH(0x0000000f);
1767     //4
1768     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_VPORT_ZMIN_0, 2);
1769     R600_OUT_BATCH(0);
1770     R600_OUT_BATCH(0x3f800000);
1771     //3
1772     EVERGREEN_OUT_BATCH_REGVAL(EG_SX_MISC, 0);
1773     //4
1774     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_MODE_CNTL_0, 2);
1775     R600_OUT_BATCH(0);
1776     R600_OUT_BATCH(0);
1777     //18
1778     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SC_LINE_CNTL, 16);
1779     R600_OUT_BATCH(0);
1780     R600_OUT_BATCH(0);
1781     R600_OUT_BATCH(0x00000005);
1782     R600_OUT_BATCH(0x3f800000);
1783     R600_OUT_BATCH(0x3f800000);
1784     R600_OUT_BATCH(0x3f800000);
1785     R600_OUT_BATCH(0x3f800000);
1786     R600_OUT_BATCH(0);
1787     R600_OUT_BATCH(0);
1788     R600_OUT_BATCH(0);
1789     R600_OUT_BATCH(0);
1790     R600_OUT_BATCH(0);
1791     R600_OUT_BATCH(0);
1792     R600_OUT_BATCH(0);
1793     R600_OUT_BATCH(0);
1794     R600_OUT_BATCH(0xffffffff);
1795     //15
1796     EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR_CONTROL, 13);
1797     R600_OUT_BATCH(0x00cc0010);
1798     R600_OUT_BATCH(0x00000210);
1799     R600_OUT_BATCH(0x00010000);
1800     R600_OUT_BATCH(0x00000004);
1801     R600_OUT_BATCH(0x00000100);
1802     R600_OUT_BATCH(0);
1803     R600_OUT_BATCH(0);
1804     R600_OUT_BATCH(0);
1805     R600_OUT_BATCH(0);
1806     R600_OUT_BATCH(0);
1807     R600_OUT_BATCH(0);
1808     R600_OUT_BATCH(0);
1809     R600_OUT_BATCH(0);
1810     //8
1811     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 6);
1812     R600_OUT_BATCH(0);
1813     R600_OUT_BATCH(0);
1814     R600_OUT_BATCH(0);
1815     R600_OUT_BATCH(0);
1816     R600_OUT_BATCH(0);
1817     R600_OUT_BATCH(0);
1818     //11
1819     EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_MAX_VTX_INDX, 9);
1820     R600_OUT_BATCH(0x00ffffff);
1821     R600_OUT_BATCH(0);
1822     R600_OUT_BATCH(0);
1823     R600_OUT_BATCH(0);
1824     R600_OUT_BATCH(0);
1825     R600_OUT_BATCH(0);
1826     R600_OUT_BATCH(0);
1827     R600_OUT_BATCH(0);
1828     R600_OUT_BATCH(0);
1829     //4
1830     EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_INSTANCE_STEP_RATE_0, 2);
1831     R600_OUT_BATCH(0);
1832     R600_OUT_BATCH(0);
1833     //4
1834     EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_REUSE_OFF, 2);
1835     R600_OUT_BATCH(0);
1836     R600_OUT_BATCH(0);
1837     //19
1838     EVERGREEN_OUT_BATCH_REGSEQ(EG_PA_SU_POINT_SIZE, 17);
1839     R600_OUT_BATCH(0);
1840     R600_OUT_BATCH(0);
1841     R600_OUT_BATCH(0x00000008);
1842     R600_OUT_BATCH(0);
1843     R600_OUT_BATCH(0);
1844     R600_OUT_BATCH(0);
1845     R600_OUT_BATCH(0);
1846     R600_OUT_BATCH(0);
1847     R600_OUT_BATCH(0);
1848     R600_OUT_BATCH(0);
1849     R600_OUT_BATCH(0);
1850     R600_OUT_BATCH(0);
1851     R600_OUT_BATCH(0);
1852     R600_OUT_BATCH(0);
1853     R600_OUT_BATCH(0);
1854     R600_OUT_BATCH(0);
1855     R600_OUT_BATCH(0);
1856     //3
1857     EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_PRIMITIVEID_EN, 0);
1858     //3
1859     EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_MULTI_PRIM_IB_RESET_EN, 0);
1860     //3
1861     EVERGREEN_OUT_BATCH_REGVAL(EG_VGT_SHADER_STAGES_EN, 0);
1862     //4
1863     EVERGREEN_OUT_BATCH_REGSEQ(EG_VGT_STRMOUT_CONFIG, 2);
1864     R600_OUT_BATCH(0);
1865     R600_OUT_BATCH(0);
1866     //3
1867     EVERGREEN_OUT_BATCH_REGVAL(EG_CB_BLEND0_CONTROL, 0);
1868     //3
1869     EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_CONFIG, 0);
1870     //3
1871     EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_VS_OUT_ID_0, 0);
1872     //3
1873     EVERGREEN_OUT_BATCH_REGVAL(EG_SPI_PS_INPUT_CNTL_0, 0);
1874     //13
1875     EVERGREEN_OUT_BATCH_REGSEQ(EG_SPI_PS_IN_CONTROL_0, 11);
1876     R600_OUT_BATCH(0x20000001);
1877     R600_OUT_BATCH(0);
1878     R600_OUT_BATCH(0);
1879     R600_OUT_BATCH(0);
1880     R600_OUT_BATCH(0);
1881     R600_OUT_BATCH(0x00100000);
1882     R600_OUT_BATCH(0);
1883     R600_OUT_BATCH(0);
1884     R600_OUT_BATCH(0);
1885     R600_OUT_BATCH(0);
1886     R600_OUT_BATCH(0);
1887
1888     END_BATCH();
1889     COMMIT_BATCH();
1890 }
1891
1892 static GLboolean eg_validate_buffers(context_t *rmesa,
1893                                      struct radeon_bo *src_bo,
1894                                      struct radeon_bo *dst_bo)
1895 {
1896     int ret;
1897
1898     radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
1899
1900     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1901                                         src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
1902     if (ret)
1903         return GL_FALSE;
1904
1905     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1906                                         dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
1907     if (ret)
1908         return GL_FALSE;
1909
1910     ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs,
1911                                         rmesa->blit_bo,
1912                                         RADEON_GEM_DOMAIN_GTT, 0);
1913     if (ret)
1914         return GL_FALSE;
1915
1916     return GL_TRUE;
1917 }
1918
1919 unsigned evergreen_blit(struct gl_context *ctx,
1920                         struct radeon_bo *src_bo,
1921                         intptr_t src_offset,
1922                         gl_format src_mesaformat,
1923                         unsigned src_pitch,
1924                         unsigned src_width,
1925                         unsigned src_height,
1926                         unsigned src_x,
1927                         unsigned src_y,
1928                         struct radeon_bo *dst_bo,
1929                         intptr_t dst_offset,
1930                         gl_format dst_mesaformat,
1931                         unsigned dst_pitch,
1932                         unsigned dst_width,
1933                         unsigned dst_height,
1934                         unsigned dst_x,
1935                         unsigned dst_y,
1936                         unsigned w,
1937                         unsigned h,
1938                         unsigned flip_y)
1939 {
1940     context_t *context = EVERGREEN_CONTEXT(ctx);
1941     int id = 0;
1942
1943     if (!evergreen_check_blit(dst_mesaformat))
1944         return GL_FALSE;
1945
1946     if (src_bo == dst_bo) {
1947         return GL_FALSE;
1948     }
1949
1950     if (src_offset % 256 || dst_offset % 256) {
1951         return GL_FALSE;
1952     }
1953
1954     if (0) {
1955         fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
1956                 src_width, src_height, src_pitch,
1957                 _mesa_format_row_stride(src_mesaformat, src_width),
1958                 _mesa_get_format_name(src_mesaformat));
1959         fprintf(stderr, "dst: width %d, height %d, pitch %d, format %s\n",
1960                 dst_width, dst_height,
1961                 _mesa_format_row_stride(dst_mesaformat, dst_width),
1962                 _mesa_get_format_name(dst_mesaformat));
1963     }
1964
1965     /* Flush is needed to make sure that source buffer has correct data */
1966     radeonFlush(ctx);
1967
1968     rcommonEnsureCmdBufSpace(&context->radeon, 327, __FUNCTION__);
1969
1970     /* load shaders */
1971     eg_load_shaders(context->radeon.glCtx);
1972
1973     if (!eg_validate_buffers(context, src_bo, dst_bo))
1974         return GL_FALSE;
1975
1976     /* set clear state */
1977     /* 196 */
1978     eg_set_default_state(context);
1979
1980     /* shaders */
1981     /* 34 */
1982     eg_set_shaders(context);
1983
1984     /* src */
1985     /* 21 */
1986     eg_set_tex_resource(context, src_mesaformat, src_bo,
1987                         src_width, src_height, src_pitch, src_offset);
1988
1989     /* 5 */
1990     eg_set_tex_sampler(context);
1991
1992     /* dst */
1993     /* 19 */
1994     eg_set_render_target(context, dst_bo, dst_mesaformat,
1995                          dst_pitch, dst_width, dst_height, dst_offset);
1996     /* scissors */
1997     /* 17 */
1998     eg_set_scissors(context, dst_x, dst_y, dst_x + dst_width, dst_y + dst_height);
1999
2000     eg_set_vb_data(context, src_x, src_y, dst_x, dst_y, w, h, src_height, flip_y);
2001     /* Vertex buffer setup */
2002     /* 18 */
2003     eg_set_vtx_resource(context);
2004
2005     /* draw */
2006     /* 10 */
2007     eg_draw_auto(context);
2008
2009     /* 7 */
2010     r700SyncSurf(context, dst_bo, 0,
2011                  RADEON_GEM_DOMAIN_VRAM|RADEON_GEM_DOMAIN_GTT,
2012                  CB_ACTION_ENA_bit | (1 << (id + 6)));
2013
2014     radeonFlush(ctx);
2015
2016     return GL_TRUE;
2017 }