2 Copyright (C) The Weather Channel, Inc. 2002.
3 Copyright (C) 2004 Nicolai Haehnle.
6 The Weather Channel (TM) funded Tungsten Graphics to develop the
7 initial release of the Radeon 8500 driver under the XFree86 license.
8 This notice must be preserved.
10 Permission is hereby granted, free of charge, to any person obtaining
11 a copy of this software and associated documentation files (the
12 "Software"), to deal in the Software without restriction, including
13 without limitation the rights to use, copy, modify, merge, publish,
14 distribute, sublicense, and/or sell copies of the Software, and to
15 permit persons to whom the Software is furnished to do so, subject to
16 the following conditions:
18 The above copyright notice and this permission notice (including the
19 next paragraph) shall be included in all copies or substantial
20 portions of the Software.
22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 **************************************************************************/
34 * Nicolai Haehnle <prefect_@gmx.net>
43 #include "simple_list.h"
45 #include "api_arrayelt.h"
46 #include "swrast/swrast.h"
47 #include "swrast_setup/swrast_setup.h"
48 #include "array_cache/acache.h"
51 #include "radeon_ioctl.h"
52 #include "r300_context.h"
53 #include "r300_ioctl.h"
54 #include "r300_state.h"
56 #include "r300_program.h"
60 * Called by Mesa after an internal state update.
62 static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
64 r300ContextPtr r300 = R300_CONTEXT(ctx);
66 _swrast_InvalidateState(ctx, new_state);
67 _swsetup_InvalidateState(ctx, new_state);
68 _ac_InvalidateState(ctx, new_state);
69 _tnl_InvalidateState(ctx, new_state);
70 _ae_invalidate_state(ctx, new_state);
72 /* Go inefficiency! */
73 r300ResetHwState(r300);
78 * Completely recalculates hardware state based on the Mesa state.
80 void r300ResetHwState(r300ContextPtr r300)
84 if (RADEON_DEBUG & DEBUG_STATE)
85 fprintf(stderr, "%s\n", __FUNCTION__);
88 __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
89 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
90 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
91 const GLfloat *v = r300->radeon.glCtx->Viewport._WindowMap.m;
93 r300->hw.vpt.cmd[R300_VPT_XSCALE] =
94 r300PackFloat32(v[MAT_SX]);
95 r300->hw.vpt.cmd[R300_VPT_XOFFSET] =
96 r300PackFloat32(v[MAT_TX] + xoffset);
97 r300->hw.vpt.cmd[R300_VPT_YSCALE] =
98 r300PackFloat32(-v[MAT_SY]);
99 r300->hw.vpt.cmd[R300_VPT_YOFFSET] =
100 r300PackFloat32(-v[MAT_TY] + yoffset);
101 r300->hw.vpt.cmd[R300_VPT_YSCALE] =
102 r300PackFloat32(v[MAT_SZ]);
103 r300->hw.vpt.cmd[R300_VPT_YOFFSET] =
104 r300PackFloat32(v[MAT_TZ]);
108 r300->hw.unk2080.cmd[1] = 0x0030045A;
110 r300->hw.ovf.cmd[R300_OVF_FMT_0] = 0x00000003;
111 r300->hw.ovf.cmd[R300_OVF_FMT_1] = 0x00000000;
113 r300->hw.unk20B0.cmd[1] = 0x0000040A;
114 r300->hw.unk20B0.cmd[2] = 0x00000008;
116 r300->hw.unk2134.cmd[1] = 0x00FFFFFF;
117 r300->hw.unk2134.cmd[2] = 0x00000000;
119 r300->hw.unk2140.cmd[1] = 0x00000000;
121 ((drm_r300_cmd_header_t*)r300->hw.vir[0].cmd)->unchecked_state.count = 1;
122 r300->hw.vir[0].cmd[1] = 0x21030003;
124 ((drm_r300_cmd_header_t*)r300->hw.vir[1].cmd)->unchecked_state.count = 1;
125 r300->hw.vir[1].cmd[1] = 0xF688F688;
127 r300->hw.vic.cmd[R300_VIR_CNTL_0] = 0x00000001;
128 r300->hw.vic.cmd[R300_VIR_CNTL_1] = 0x00000405;
130 r300->hw.unk21DC.cmd[1] = 0xAAAAAAAA;
132 r300->hw.unk221C.cmd[1] = R300_221C_NORMAL;
134 r300->hw.unk2220.cmd[1] = r300PackFloat32(1.0);
135 r300->hw.unk2220.cmd[2] = r300PackFloat32(1.0);
136 r300->hw.unk2220.cmd[3] = r300PackFloat32(1.0);
137 r300->hw.unk2220.cmd[4] = r300PackFloat32(1.0);
139 if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
140 r300->hw.unk2288.cmd[1] = R300_2288_R300;
142 r300->hw.unk2288.cmd[1] = R300_2288_RV350;
144 r300->hw.pvs.cmd[R300_PVS_CNTL_1] = 0;
145 r300->hw.pvs.cmd[R300_PVS_CNTL_2] = 0;
146 r300->hw.pvs.cmd[R300_PVS_CNTL_3] = 0;
148 r300->hw.unk4008.cmd[1] = 0x00000007;
150 r300->hw.unk4010.cmd[1] = 0x66666666;
151 r300->hw.unk4010.cmd[2] = 0x06666666;
152 if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
153 r300->hw.unk4010.cmd[3] = 0x00000017;
155 r300->hw.unk4010.cmd[3] = 0x00000011;
156 r300->hw.unk4010.cmd[4] = 0x00000000;
157 r300->hw.unk4010.cmd[5] = 0x00000000;
159 r300->hw.txe.cmd[R300_TXE_ENABLE] = 0;
161 r300->hw.unk4200.cmd[1] = r300PackFloat32(0.0);
162 r300->hw.unk4200.cmd[2] = r300PackFloat32(0.0);
163 r300->hw.unk4200.cmd[3] = r300PackFloat32(1.0);
164 r300->hw.unk4200.cmd[4] = r300PackFloat32(1.0);
166 r300->hw.unk4214.cmd[1] = 0x00050005;
168 r300->hw.unk4230.cmd[1] = 0x01800000;
169 r300->hw.unk4230.cmd[2] = 0x00020006;
170 r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0);
172 r300->hw.unk4260.cmd[1] = 0;
173 r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0);
174 r300->hw.unk4260.cmd[3] = r300PackFloat32(1.0);
176 r300->hw.unk4274.cmd[1] = 0x00000002;
177 r300->hw.unk4274.cmd[2] = 0x0003AAAA;
178 r300->hw.unk4274.cmd[3] = 0x00000000;
179 r300->hw.unk4274.cmd[4] = 0x00000000;
181 r300->hw.unk4288.cmd[1] = 0x00000000;
182 r300->hw.unk4288.cmd[2] = 0x00000001;
183 r300->hw.unk4288.cmd[3] = 0x00000000;
184 r300->hw.unk4288.cmd[4] = 0x00000000;
185 r300->hw.unk4288.cmd[5] = 0x00000000;
187 r300->hw.unk42A0.cmd[1] = 0x00000000;
189 r300->hw.unk42B4.cmd[1] = 0x00000000;
190 r300->hw.unk42B4.cmd[2] = 0x00000000;
192 r300->hw.unk42C0.cmd[1] = 0x4B7FFFFF;
193 r300->hw.unk42C0.cmd[2] = 0x00000000;
195 r300->hw.rc.cmd[1] = R300_RS_CNTL_0_UNKNOWN_7;
196 r300->hw.rc.cmd[2] = 0;
198 for(i = 1; i <= 8; ++i)
199 r300->hw.ri.cmd[i] = 0;
201 ((drm_r300_cmd_header_t*)r300->hw.rr.cmd)->unchecked_state.count = 1;
202 for(i = 1; i <= 8; ++i)
203 r300->hw.rr.cmd[1] = 0;
205 r300->hw.unk43A4.cmd[1] = 0x0000001C;
206 r300->hw.unk43A4.cmd[2] = 0x2DA49525;
208 r300->hw.unk43E0.cmd[1] = 0x00000000;
209 r300->hw.unk43E0.cmd[2] = 0x03FFFFFF;
210 r300->hw.unk43E0.cmd[3] = 0x00FFFFFF;
212 r300->hw.fp.cmd[R300_FP_CNTL0] = 0;
213 r300->hw.fp.cmd[R300_FP_CNTL1] = 0;
214 r300->hw.fp.cmd[R300_FP_CNTL2] = 0;
215 r300->hw.fp.cmd[R300_FP_NODE0] = 0;
216 r300->hw.fp.cmd[R300_FP_NODE1] = 0;
217 r300->hw.fp.cmd[R300_FP_NODE2] = 0;
218 r300->hw.fp.cmd[R300_FP_NODE3] = 0;
220 r300->hw.unk46A4.cmd[1] = 0x00001B01;
221 r300->hw.unk46A4.cmd[2] = 0x00001B0F;
222 r300->hw.unk46A4.cmd[3] = 0x00001B0F;
223 r300->hw.unk46A4.cmd[4] = 0x00001B0F;
224 r300->hw.unk46A4.cmd[5] = 0x00000001;
226 for(i = 1; i <= 64; ++i) {
227 /* create NOP instructions */
228 r300->hw.fpi[0].cmd[i] = FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO));
229 r300->hw.fpi[1].cmd[i] = FP_SELC(0,XYZ,NO,FP_TMP(0),0,0);
230 r300->hw.fpi[2].cmd[i] = FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO));
231 r300->hw.fpi[3].cmd[i] = FP_SELA(0,W,NO,FP_TMP(0),0,0);
234 r300->hw.unk4BC0.cmd[1] = 0;
236 r300->hw.unk4BC8.cmd[1] = 0;
237 r300->hw.unk4BC8.cmd[2] = 0;
238 r300->hw.unk4BC8.cmd[3] = 0;
240 r300->hw.at.cmd[R300_AT_ALPHA_TEST] = 0;
242 r300->hw.unk4BD8.cmd[1] = 0;
244 r300->hw.unk4E00.cmd[1] = 0;
246 r300->hw.bld.cmd[R300_BLD_CBLEND] = 0;
247 r300->hw.bld.cmd[R300_BLD_ABLEND] = 0;
249 r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0xF;
251 r300->hw.unk4E10.cmd[1] = 0;
252 r300->hw.unk4E10.cmd[2] = 0;
253 r300->hw.unk4E10.cmd[3] = 0;
255 r300->hw.cb.cmd[R300_CB_OFFSET] =
256 r300->radeon.radeonScreen->backOffset +
257 r300->radeon.radeonScreen->fbLocation;
258 r300->hw.cb.cmd[R300_CB_PITCH] = r300->radeon.radeonScreen->backPitch
259 | R300_COLOR_UNKNOWN_22_23;
261 r300->hw.unk4E50.cmd[1] = 0;
262 r300->hw.unk4E50.cmd[2] = 0;
263 r300->hw.unk4E50.cmd[3] = 0;
264 r300->hw.unk4E50.cmd[4] = 0;
265 r300->hw.unk4E50.cmd[5] = 0;
266 r300->hw.unk4E50.cmd[6] = 0;
267 r300->hw.unk4E50.cmd[7] = 0;
268 r300->hw.unk4E50.cmd[8] = 0;
269 r300->hw.unk4E50.cmd[9] = 0;
271 r300->hw.unk4E88.cmd[1] = 0;
273 r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0;
274 r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0;
276 r300->hw.unk4F08.cmd[1] = 0x00FFFF00;
277 r300->hw.unk4F08.cmd[2] = 0x00000002;
278 r300->hw.unk4F08.cmd[3] = 0x00000000;
279 r300->hw.unk4F08.cmd[4] = 0x00000003;
280 r300->hw.unk4F08.cmd[5] = 0x00000000;
282 r300->hw.zb.cmd[R300_ZB_OFFSET] =
283 r300->radeon.radeonScreen->depthOffset +
284 r300->radeon.radeonScreen->fbLocation;
285 r300->hw.zb.cmd[R300_ZB_PITCH] = r300->radeon.radeonScreen->depthPitch;
287 r300->hw.unk4F28.cmd[1] = 0;
289 r300->hw.unk4F30.cmd[1] = 0;
290 r300->hw.unk4F30.cmd[2] = 0;
292 r300->hw.unk4F44.cmd[1] = 0;
294 r300->hw.unk4F54.cmd[1] = 0;
296 ((drm_r300_cmd_header_t*)r300->hw.vpi.cmd)->vpu.count = 0;
297 for(i = 1; i < R300_VPI_CMDSIZE; i += 4) {
299 r300->hw.vpi.cmd[i+0] = VP_OUT(ADD,TMP,0,XYZW);
300 r300->hw.vpi.cmd[i+1] = VP_IN(TMP,0);
301 r300->hw.vpi.cmd[i+2] = VP_ZERO();
302 r300->hw.vpi.cmd[i+3] = VP_ZERO();
305 ((drm_r300_cmd_header_t*)r300->hw.vpp.cmd)->vpu.count = 0;
306 for(i = 1; i < R300_VPP_CMDSIZE; ++i)
307 r300->hw.vpp.cmd[i] = 0;
310 r300->hw.all_dirty = GL_TRUE;
315 * Calculate initial hardware state and register state functions.
316 * Assumes that the command buffer and state atoms have been
317 * initialized already.
319 void r300InitState(r300ContextPtr r300)
321 struct dd_function_table* functions;
323 r300ResetHwState(r300);
325 /* Setup state functions */
326 functions = &r300->radeon.glCtx->Driver;
327 functions->UpdateState = r300InvalidateState;