src/mesa/drivers/dri/r300/r300_state.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.
   3 Copyright (C) 2004 Nicolai Haehnle.
   4 All Rights Reserved.
   5
   6 The Weather Channel (TM) funded Tungsten Graphics to develop the
   7 initial release of the Radeon 8500 driver under the XFree86 license.
   8 This notice must be preserved.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining
  11 a copy of this software and associated documentation files (the
  12 "Software"), to deal in the Software without restriction, including
  13 without limitation the rights to use, copy, modify, merge, publish,
  14 distribute, sublicense, and/or sell copies of the Software, and to
  15 permit persons to whom the Software is furnished to do so, subject to
  16 the following conditions:
  17
  18 The above copyright notice and this permission notice (including the
  19 next paragraph) shall be included in all copies or substantial
  20 portions of the Software.
  21
  22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  29
  30 **************************************************************************/
  31
  32 /*
  33  * Authors:
  34  *   Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #include "glheader.h"
  38 #include "state.h"
  39 #include "imports.h"
  40 #include "enums.h"
  41 #include "macros.h"
  42 #include "context.h"
  43 #include "dd.h"
  44 #include "simple_list.h"
  45
  46 #include "api_arrayelt.h"
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "array_cache/acache.h"
  50 #include "tnl/tnl.h"
  51
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "r300_context.h"
  55 #include "r300_ioctl.h"
  56 #include "r300_state.h"
  57 #include "r300_reg.h"
  58 #include "r300_program.h"
  59
  60
  61 /**
  62  * Handle glEnable()/glDisable().
  63  */
  64 static void r300Enable(GLcontext* ctx, GLenum cap, GLboolean state)
  65 {
  66         if (RADEON_DEBUG & DEBUG_STATE)
  67                 fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
  68                         _mesa_lookup_enum_by_nr(cap),
  69                         state ? "GL_TRUE" : "GL_FALSE");
  70
  71         switch (cap) {
  72         default:
  73                 radeonEnable(ctx, cap, state);
  74                 return;
  75         }
  76 }
  77
  78
  79 /**
  80  * Called by Mesa after an internal state update.
  81  */
  82 static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
  83 {
  84         r300ContextPtr r300 = R300_CONTEXT(ctx);
  85
  86         _swrast_InvalidateState(ctx, new_state);
  87         _swsetup_InvalidateState(ctx, new_state);
  88         _ac_InvalidateState(ctx, new_state);
  89         _tnl_InvalidateState(ctx, new_state);
  90         _ae_invalidate_state(ctx, new_state);
  91
  92         /* Go inefficiency! */
  93         r300ResetHwState(r300);
  94 }
  95
  96
  97 /**
  98  * Completely recalculates hardware state based on the Mesa state.
  99  */
 100 void r300ResetHwState(r300ContextPtr r300)
 101 {
 102         int i;
 103
 104         if (RADEON_DEBUG & DEBUG_STATE)
 105                 fprintf(stderr, "%s\n", __FUNCTION__);
 106
 107         {
 108                 __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
 109                 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
 110                 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
 111                 const GLfloat *v = r300->radeon.glCtx->Viewport._WindowMap.m;
 112
 113                 r300->hw.vpt.cmd[R300_VPT_XSCALE] =
 114                         r300PackFloat32(v[MAT_SX]);
 115                 r300->hw.vpt.cmd[R300_VPT_XOFFSET] =
 116                         r300PackFloat32(v[MAT_TX] + xoffset);
 117                 r300->hw.vpt.cmd[R300_VPT_YSCALE] =
 118                         r300PackFloat32(-v[MAT_SY]);
 119                 r300->hw.vpt.cmd[R300_VPT_YOFFSET] =
 120                         r300PackFloat32(-v[MAT_TY] + yoffset);
 121                 r300->hw.vpt.cmd[R300_VPT_YSCALE] =
 122                         r300PackFloat32(v[MAT_SZ]);
 123                 r300->hw.vpt.cmd[R300_VPT_YOFFSET] =
 124                         r300PackFloat32(v[MAT_TZ]);
 125         }
 126
 127 //BEGIN: TODO
 128         r300->hw.unk2080.cmd[1] = 0x0030045A;
 129
 130         r300->hw.ovf.cmd[R300_OVF_FMT_0] = 0x00000003;
 131         r300->hw.ovf.cmd[R300_OVF_FMT_1] = 0x00000000;
 132
 133         r300->hw.unk20B0.cmd[1] = 0x0000040A;
 134         r300->hw.unk20B0.cmd[2] = 0x00000008;
 135
 136         r300->hw.unk2134.cmd[1] = 0x00FFFFFF;
 137         r300->hw.unk2134.cmd[2] = 0x00000000;
 138
 139         r300->hw.unk2140.cmd[1] = 0x00000000;
 140
 141         ((drm_r300_cmd_header_t*)r300->hw.vir[0].cmd)->unchecked_state.count = 1;
 142         r300->hw.vir[0].cmd[1] = 0x21030003;
 143
 144         ((drm_r300_cmd_header_t*)r300->hw.vir[1].cmd)->unchecked_state.count = 1;
 145         r300->hw.vir[1].cmd[1] = 0xF688F688;
 146
 147         r300->hw.vic.cmd[R300_VIR_CNTL_0] = 0x00000001;
 148         r300->hw.vic.cmd[R300_VIR_CNTL_1] = 0x00000405;
 149
 150         r300->hw.unk21DC.cmd[1] = 0xAAAAAAAA;
 151
 152         r300->hw.unk221C.cmd[1] = R300_221C_NORMAL;
 153
 154         r300->hw.unk2220.cmd[1] = r300PackFloat32(1.0);
 155         r300->hw.unk2220.cmd[2] = r300PackFloat32(1.0);
 156         r300->hw.unk2220.cmd[3] = r300PackFloat32(1.0);
 157         r300->hw.unk2220.cmd[4] = r300PackFloat32(1.0);
 158
 159         if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
 160                 r300->hw.unk2288.cmd[1] = R300_2288_R300;
 161         else
 162                 r300->hw.unk2288.cmd[1] = R300_2288_RV350;
 163
 164         r300->hw.pvs.cmd[R300_PVS_CNTL_1] = 0;
 165         r300->hw.pvs.cmd[R300_PVS_CNTL_2] = 0;
 166         r300->hw.pvs.cmd[R300_PVS_CNTL_3] = 0;
 167
 168         r300->hw.unk4008.cmd[1] = 0x00000007;
 169
 170         r300->hw.unk4010.cmd[1] = 0x66666666;
 171         r300->hw.unk4010.cmd[2] = 0x06666666;
 172         if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
 173                 r300->hw.unk4010.cmd[3] = 0x00000017;
 174         else
 175                 r300->hw.unk4010.cmd[3] = 0x00000011;
 176         r300->hw.unk4010.cmd[4] = 0x00000000;
 177         r300->hw.unk4010.cmd[5] = 0x00000000;
 178
 179         r300->hw.txe.cmd[R300_TXE_ENABLE] = 0;
 180
 181         r300->hw.unk4200.cmd[1] = r300PackFloat32(0.0);
 182         r300->hw.unk4200.cmd[2] = r300PackFloat32(0.0);
 183         r300->hw.unk4200.cmd[3] = r300PackFloat32(1.0);
 184         r300->hw.unk4200.cmd[4] = r300PackFloat32(1.0);
 185
 186         r300->hw.unk4214.cmd[1] = 0x00050005;
 187
 188         r300->hw.ps.cmd[R300_PS_POINTSIZE] = (6 << R300_POINTSIZE_X_SHIFT) |
 189                                              (6 << R300_POINTSIZE_Y_SHIFT);
 190
 191         r300->hw.unk4230.cmd[1] = 0x01800000;
 192         r300->hw.unk4230.cmd[2] = 0x00020006;
 193         r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0);
 194
 195         r300->hw.unk4260.cmd[1] = 0;
 196         r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0);
 197         r300->hw.unk4260.cmd[3] = r300PackFloat32(1.0);
 198
 199         r300->hw.unk4274.cmd[1] = 0x00000002;
 200         r300->hw.unk4274.cmd[2] = 0x0003AAAA;
 201         r300->hw.unk4274.cmd[3] = 0x00000000;
 202         r300->hw.unk4274.cmd[4] = 0x00000000;
 203
 204         r300->hw.unk4288.cmd[1] = 0x00000000;
 205         r300->hw.unk4288.cmd[2] = 0x00000001;
 206         r300->hw.unk4288.cmd[3] = 0x00000000;
 207         r300->hw.unk4288.cmd[4] = 0x00000000;
 208         r300->hw.unk4288.cmd[5] = 0x00000000;
 209
 210         r300->hw.unk42A0.cmd[1] = 0x00000000;
 211
 212         r300->hw.unk42B4.cmd[1] = 0x00000000;
 213         r300->hw.unk42B4.cmd[2] = 0x00000000;
 214
 215         r300->hw.unk42C0.cmd[1] = 0x4B7FFFFF;
 216         r300->hw.unk42C0.cmd[2] = 0x00000000;
 217
 218         r300->hw.rc.cmd[1] = R300_RS_CNTL_0_UNKNOWN_7;
 219         r300->hw.rc.cmd[2] = 0;
 220
 221         for(i = 1; i <= 8; ++i)
 222                 r300->hw.ri.cmd[i] = 0;
 223
 224         ((drm_r300_cmd_header_t*)r300->hw.rr.cmd)->unchecked_state.count = 1;
 225         for(i = 1; i <= 8; ++i)
 226                 r300->hw.rr.cmd[1] = 0;
 227
 228         r300->hw.unk43A4.cmd[1] = 0x0000001C;
 229         r300->hw.unk43A4.cmd[2] = 0x2DA49525;
 230
 231         r300->hw.unk43E8.cmd[1] = 0x00FFFFFF;
 232
 233         r300->hw.fp.cmd[R300_FP_CNTL0] = 0;
 234         r300->hw.fp.cmd[R300_FP_CNTL1] = 0;
 235         r300->hw.fp.cmd[R300_FP_CNTL2] = 0;
 236         r300->hw.fp.cmd[R300_FP_NODE0] = 0;
 237         r300->hw.fp.cmd[R300_FP_NODE1] = 0;
 238         r300->hw.fp.cmd[R300_FP_NODE2] = 0;
 239         r300->hw.fp.cmd[R300_FP_NODE3] = 0;
 240
 241         r300->hw.unk46A4.cmd[1] = 0x00001B01;
 242         r300->hw.unk46A4.cmd[2] = 0x00001B0F;
 243         r300->hw.unk46A4.cmd[3] = 0x00001B0F;
 244         r300->hw.unk46A4.cmd[4] = 0x00001B0F;
 245         r300->hw.unk46A4.cmd[5] = 0x00000001;
 246
 247         for(i = 1; i <= 64; ++i) {
 248                 /* create NOP instructions */
 249                 r300->hw.fpi[0].cmd[i] = FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO));
 250                 r300->hw.fpi[1].cmd[i] = FP_SELC(0,XYZ,NO,FP_TMP(0),0,0);
 251                 r300->hw.fpi[2].cmd[i] = FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO));
 252                 r300->hw.fpi[3].cmd[i] = FP_SELA(0,W,NO,FP_TMP(0),0,0);
 253         }
 254
 255         r300->hw.unk4BC0.cmd[1] = 0;
 256
 257         r300->hw.unk4BC8.cmd[1] = 0;
 258         r300->hw.unk4BC8.cmd[2] = 0;
 259         r300->hw.unk4BC8.cmd[3] = 0;
 260
 261         r300->hw.at.cmd[R300_AT_ALPHA_TEST] = 0;
 262
 263         r300->hw.unk4BD8.cmd[1] = 0;
 264
 265         r300->hw.unk4E00.cmd[1] = 0;
 266
 267         r300->hw.bld.cmd[R300_BLD_CBLEND] = 0;
 268         r300->hw.bld.cmd[R300_BLD_ABLEND] = 0;
 269
 270         r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0xF;
 271
 272         r300->hw.unk4E10.cmd[1] = 0;
 273         r300->hw.unk4E10.cmd[2] = 0;
 274         r300->hw.unk4E10.cmd[3] = 0;
 275
 276         r300->hw.cb.cmd[R300_CB_OFFSET] =
 277                 r300->radeon.radeonScreen->backOffset +
 278                 r300->radeon.radeonScreen->fbLocation;
 279         r300->hw.cb.cmd[R300_CB_PITCH] = r300->radeon.radeonScreen->backPitch
 280                 | R300_COLOR_UNKNOWN_22_23;
 281
 282         r300->hw.unk4E50.cmd[1] = 0;
 283         r300->hw.unk4E50.cmd[2] = 0;
 284         r300->hw.unk4E50.cmd[3] = 0;
 285         r300->hw.unk4E50.cmd[4] = 0;
 286         r300->hw.unk4E50.cmd[5] = 0;
 287         r300->hw.unk4E50.cmd[6] = 0;
 288         r300->hw.unk4E50.cmd[7] = 0;
 289         r300->hw.unk4E50.cmd[8] = 0;
 290         r300->hw.unk4E50.cmd[9] = 0;
 291
 292         r300->hw.unk4E88.cmd[1] = 0;
 293
 294         r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0;
 295         r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0;
 296
 297         r300->hw.unk4F08.cmd[1] = 0x00FFFF00;
 298
 299         r300->hw.unk4F10.cmd[1] = 0x00000002; // depthbuffer format?
 300         r300->hw.unk4F10.cmd[2] = 0x00000000;
 301         r300->hw.unk4F10.cmd[3] = 0x00000003;
 302         r300->hw.unk4F10.cmd[4] = 0x00000000;
 303
 304         r300->hw.zb.cmd[R300_ZB_OFFSET] =
 305                 r300->radeon.radeonScreen->depthOffset +
 306                 r300->radeon.radeonScreen->fbLocation;
 307         r300->hw.zb.cmd[R300_ZB_PITCH] = r300->radeon.radeonScreen->depthPitch;
 308
 309         r300->hw.unk4F28.cmd[1] = 0;
 310
 311         r300->hw.unk4F30.cmd[1] = 0;
 312         r300->hw.unk4F30.cmd[2] = 0;
 313
 314         r300->hw.unk4F44.cmd[1] = 0;
 315
 316         r300->hw.unk4F54.cmd[1] = 0;
 317
 318         ((drm_r300_cmd_header_t*)r300->hw.vpi.cmd)->vpu.count = 0;
 319         for(i = 1; i < R300_VPI_CMDSIZE; i += 4) {
 320                 /* MOV t0, t0 */
 321                 r300->hw.vpi.cmd[i+0] = VP_OUT(ADD,TMP,0,XYZW);
 322                 r300->hw.vpi.cmd[i+1] = VP_IN(TMP,0);
 323                 r300->hw.vpi.cmd[i+2] = VP_ZERO();
 324                 r300->hw.vpi.cmd[i+3] = VP_ZERO();
 325         }
 326
 327         ((drm_r300_cmd_header_t*)r300->hw.vpp.cmd)->vpu.count = 0;
 328         for(i = 1; i < R300_VPP_CMDSIZE; ++i)
 329                 r300->hw.vpp.cmd[i] = 0;
 330
 331         r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;
 332         r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0;
 333         r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0);
 334         r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
 335 //END: TODO
 336
 337         r300->hw.all_dirty = GL_TRUE;
 338 }
 339
 340
 341
 342 /**
 343  * Calculate initial hardware state and register state functions.
 344  * Assumes that the command buffer and state atoms have been
 345  * initialized already.
 346  */
 347 void r300InitState(r300ContextPtr r300)
 348 {
 349         radeonInitState(&r300->radeon);
 350
 351         r300ResetHwState(r300);
 352 }
 353
 354
 355 /**
 356  * Initialize driver's state callback functions
 357  */
 358 void r300InitStateFuncs(struct dd_function_table* functions)
 359 {
 360         radeonInitStateFuncs(functions);
 361
 362         functions->UpdateState = r300InvalidateState;
 363         functions->Enable= r300Enable;
 364 }
 365