src/mesa/drivers/dri/r300/r300_state.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.
   3 Copyright (C) 2004 Nicolai Haehnle.
   4 All Rights Reserved.
   5
   6 The Weather Channel (TM) funded Tungsten Graphics to develop the
   7 initial release of the Radeon 8500 driver under the XFree86 license.
   8 This notice must be preserved.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining
  11 a copy of this software and associated documentation files (the
  12 "Software"), to deal in the Software without restriction, including
  13 without limitation the rights to use, copy, modify, merge, publish,
  14 distribute, sublicense, and/or sell copies of the Software, and to
  15 permit persons to whom the Software is furnished to do so, subject to
  16 the following conditions:
  17
  18 The above copyright notice and this permission notice (including the
  19 next paragraph) shall be included in all copies or substantial
  20 portions of the Software.
  21
  22 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  25 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  26 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  27 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  28 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  29
  30 **************************************************************************/
  31
  32 /*
  33  * Authors:
  34  *   Nicolai Haehnle <prefect_@gmx.net>
  35  */
  36
  37 #include "glheader.h"
  38 #include "state.h"
  39 #include "imports.h"
  40 #include "enums.h"
  41 #include "macros.h"
  42 #include "context.h"
  43 #include "dd.h"
  44 #include "simple_list.h"
  45
  46 #include "api_arrayelt.h"
  47 #include "swrast/swrast.h"
  48 #include "swrast_setup/swrast_setup.h"
  49 #include "array_cache/acache.h"
  50 #include "tnl/tnl.h"
  51
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "r300_context.h"
  55 #include "r300_ioctl.h"
  56 #include "r300_state.h"
  57 #include "r300_reg.h"
  58 #include "r300_program.h"
  59
  60
  61 /**
  62  * Handle glEnable()/glDisable().
  63  */
  64 static void r300Enable(GLcontext* ctx, GLenum cap, GLboolean state)
  65 {
  66         if (RADEON_DEBUG & DEBUG_STATE)
  67                 fprintf(stderr, "%s( %s = %s )\n", __FUNCTION__,
  68                         _mesa_lookup_enum_by_nr(cap),
  69                         state ? "GL_TRUE" : "GL_FALSE");
  70
  71         switch (cap) {
  72         default:
  73                 radeonEnable(ctx, cap, state);
  74                 return;
  75         }
  76 }
  77
  78
  79 /**
  80  * Handle glColorMask()
  81  */
  82 static void r300ColorMask(GLcontext* ctx,
  83                           GLboolean r, GLboolean g, GLboolean b, GLboolean a)
  84 {
  85         r300ContextPtr r300 = R300_CONTEXT(ctx);
  86         int mask = (b << 0) | (g << 1) | (r << 2) | (a << 3);
  87
  88         if (mask != r300->hw.cmk.cmd[R300_CMK_COLORMASK]) {
  89                 R300_STATECHANGE(r300, cmk);
  90                 r300->hw.cmk.cmd[R300_CMK_COLORMASK] = mask;
  91         }
  92 }
  93
  94
  95 /**
  96  * Called by Mesa after an internal state update.
  97  */
  98 static void r300InvalidateState(GLcontext * ctx, GLuint new_state)
  99 {
 100         r300ContextPtr r300 = R300_CONTEXT(ctx);
 101
 102         _swrast_InvalidateState(ctx, new_state);
 103         _swsetup_InvalidateState(ctx, new_state);
 104         _ac_InvalidateState(ctx, new_state);
 105         _tnl_InvalidateState(ctx, new_state);
 106         _ae_invalidate_state(ctx, new_state);
 107
 108         /* Go inefficiency! */
 109         r300ResetHwState(r300);
 110 }
 111
 112
 113 /**
 114  * Completely recalculates hardware state based on the Mesa state.
 115  */
 116 void r300ResetHwState(r300ContextPtr r300)
 117 {
 118         GLcontext* ctx = r300->radeon.glCtx;
 119         int i;
 120
 121         if (RADEON_DEBUG & DEBUG_STATE)
 122                 fprintf(stderr, "%s\n", __FUNCTION__);
 123
 124         {
 125                 __DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
 126                 GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0;
 127                 GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0;
 128                 const GLfloat *v = ctx->Viewport._WindowMap.m;
 129
 130                 r300->hw.vpt.cmd[R300_VPT_XSCALE] =
 131                         r300PackFloat32(v[MAT_SX]);
 132                 r300->hw.vpt.cmd[R300_VPT_XOFFSET] =
 133                         r300PackFloat32(v[MAT_TX] + xoffset);
 134                 r300->hw.vpt.cmd[R300_VPT_YSCALE] =
 135                         r300PackFloat32(-v[MAT_SY]);
 136                 r300->hw.vpt.cmd[R300_VPT_YOFFSET] =
 137                         r300PackFloat32(-v[MAT_TY] + yoffset);
 138                 r300->hw.vpt.cmd[R300_VPT_YSCALE] =
 139                         r300PackFloat32(v[MAT_SZ]);
 140                 r300->hw.vpt.cmd[R300_VPT_YOFFSET] =
 141                         r300PackFloat32(v[MAT_TZ]);
 142         }
 143
 144         r300->hw.cmk.cmd[R300_CMK_COLORMASK] =
 145                 (ctx->Color.ColorMask[BCOMP] ? R300_COLORMASK0_B : 0) |
 146                 (ctx->Color.ColorMask[GCOMP] ? R300_COLORMASK0_G : 0) |
 147                 (ctx->Color.ColorMask[RCOMP] ? R300_COLORMASK0_R : 0) |
 148                 (ctx->Color.ColorMask[ACOMP] ? R300_COLORMASK0_A : 0);
 149
 150 //BEGIN: TODO
 151         r300->hw.unk2080.cmd[1] = 0x0030045A;
 152
 153         r300->hw.ovf.cmd[R300_OVF_FMT_0] = 0x00000003;
 154         r300->hw.ovf.cmd[R300_OVF_FMT_1] = 0x00000000;
 155
 156         r300->hw.unk20B0.cmd[1] = 0x0000040A;
 157         r300->hw.unk20B0.cmd[2] = 0x00000008;
 158
 159         r300->hw.unk2134.cmd[1] = 0x00FFFFFF;
 160         r300->hw.unk2134.cmd[2] = 0x00000000;
 161
 162         r300->hw.unk2140.cmd[1] = 0x00000000;
 163
 164         ((drm_r300_cmd_header_t*)r300->hw.vir[0].cmd)->unchecked_state.count = 1;
 165         r300->hw.vir[0].cmd[1] = 0x21030003;
 166
 167         ((drm_r300_cmd_header_t*)r300->hw.vir[1].cmd)->unchecked_state.count = 1;
 168         r300->hw.vir[1].cmd[1] = 0xF688F688;
 169
 170         r300->hw.vic.cmd[R300_VIR_CNTL_0] = 0x00000001;
 171         r300->hw.vic.cmd[R300_VIR_CNTL_1] = 0x00000405;
 172
 173         r300->hw.unk21DC.cmd[1] = 0xAAAAAAAA;
 174
 175         r300->hw.unk221C.cmd[1] = R300_221C_NORMAL;
 176
 177         r300->hw.unk2220.cmd[1] = r300PackFloat32(1.0);
 178         r300->hw.unk2220.cmd[2] = r300PackFloat32(1.0);
 179         r300->hw.unk2220.cmd[3] = r300PackFloat32(1.0);
 180         r300->hw.unk2220.cmd[4] = r300PackFloat32(1.0);
 181
 182         if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
 183                 r300->hw.unk2288.cmd[1] = R300_2288_R300;
 184         else
 185                 r300->hw.unk2288.cmd[1] = R300_2288_RV350;
 186
 187         r300->hw.pvs.cmd[R300_PVS_CNTL_1] = 0;
 188         r300->hw.pvs.cmd[R300_PVS_CNTL_2] = 0;
 189         r300->hw.pvs.cmd[R300_PVS_CNTL_3] = 0;
 190
 191         r300->hw.unk4008.cmd[1] = 0x00000007;
 192
 193         r300->hw.unk4010.cmd[1] = 0x66666666;
 194         r300->hw.unk4010.cmd[2] = 0x06666666;
 195         if (GET_CHIP(r300->radeon.radeonScreen) == RADEON_CHIP_R300)
 196                 r300->hw.unk4010.cmd[3] = 0x00000017;
 197         else
 198                 r300->hw.unk4010.cmd[3] = 0x00000011;
 199         r300->hw.unk4010.cmd[4] = 0x00000000;
 200         r300->hw.unk4010.cmd[5] = 0x00000000;
 201
 202         r300->hw.txe.cmd[R300_TXE_ENABLE] = 0;
 203
 204         r300->hw.unk4200.cmd[1] = r300PackFloat32(0.0);
 205         r300->hw.unk4200.cmd[2] = r300PackFloat32(0.0);
 206         r300->hw.unk4200.cmd[3] = r300PackFloat32(1.0);
 207         r300->hw.unk4200.cmd[4] = r300PackFloat32(1.0);
 208
 209         r300->hw.unk4214.cmd[1] = 0x00050005;
 210
 211         r300->hw.ps.cmd[R300_PS_POINTSIZE] = (6 << R300_POINTSIZE_X_SHIFT) |
 212                                              (6 << R300_POINTSIZE_Y_SHIFT);
 213
 214         r300->hw.unk4230.cmd[1] = 0x01800000;
 215         r300->hw.unk4230.cmd[2] = 0x00020006;
 216         r300->hw.unk4230.cmd[3] = r300PackFloat32(1.0 / 192.0);
 217
 218         r300->hw.unk4260.cmd[1] = 0;
 219         r300->hw.unk4260.cmd[2] = r300PackFloat32(0.0);
 220         r300->hw.unk4260.cmd[3] = r300PackFloat32(1.0);
 221
 222         r300->hw.unk4274.cmd[1] = 0x00000002;
 223         r300->hw.unk4274.cmd[2] = 0x0003AAAA;
 224         r300->hw.unk4274.cmd[3] = 0x00000000;
 225         r300->hw.unk4274.cmd[4] = 0x00000000;
 226
 227         r300->hw.unk4288.cmd[1] = 0x00000000;
 228         r300->hw.unk4288.cmd[2] = 0x00000001;
 229         r300->hw.unk4288.cmd[3] = 0x00000000;
 230         r300->hw.unk4288.cmd[4] = 0x00000000;
 231         r300->hw.unk4288.cmd[5] = 0x00000000;
 232
 233         r300->hw.unk42A0.cmd[1] = 0x00000000;
 234
 235         r300->hw.unk42B4.cmd[1] = 0x00000000;
 236         r300->hw.unk42B4.cmd[2] = 0x00000000;
 237
 238         r300->hw.unk42C0.cmd[1] = 0x4B7FFFFF;
 239         r300->hw.unk42C0.cmd[2] = 0x00000000;
 240
 241         r300->hw.rc.cmd[1] = R300_RS_CNTL_0_UNKNOWN_7;
 242         r300->hw.rc.cmd[2] = 0;
 243
 244         for(i = 1; i <= 8; ++i)
 245                 r300->hw.ri.cmd[i] = 0;
 246
 247         ((drm_r300_cmd_header_t*)r300->hw.rr.cmd)->unchecked_state.count = 1;
 248         for(i = 1; i <= 8; ++i)
 249                 r300->hw.rr.cmd[1] = 0;
 250
 251         r300->hw.unk43A4.cmd[1] = 0x0000001C;
 252         r300->hw.unk43A4.cmd[2] = 0x2DA49525;
 253
 254         r300->hw.unk43E8.cmd[1] = 0x00FFFFFF;
 255
 256         r300->hw.fp.cmd[R300_FP_CNTL0] = 0;
 257         r300->hw.fp.cmd[R300_FP_CNTL1] = 0;
 258         r300->hw.fp.cmd[R300_FP_CNTL2] = 0;
 259         r300->hw.fp.cmd[R300_FP_NODE0] = 0;
 260         r300->hw.fp.cmd[R300_FP_NODE1] = 0;
 261         r300->hw.fp.cmd[R300_FP_NODE2] = 0;
 262         r300->hw.fp.cmd[R300_FP_NODE3] = 0;
 263
 264         r300->hw.unk46A4.cmd[1] = 0x00001B01;
 265         r300->hw.unk46A4.cmd[2] = 0x00001B0F;
 266         r300->hw.unk46A4.cmd[3] = 0x00001B0F;
 267         r300->hw.unk46A4.cmd[4] = 0x00001B0F;
 268         r300->hw.unk46A4.cmd[5] = 0x00000001;
 269
 270         for(i = 1; i <= 64; ++i) {
 271                 /* create NOP instructions */
 272                 r300->hw.fpi[0].cmd[i] = FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO));
 273                 r300->hw.fpi[1].cmd[i] = FP_SELC(0,XYZ,NO,FP_TMP(0),0,0);
 274                 r300->hw.fpi[2].cmd[i] = FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO));
 275                 r300->hw.fpi[3].cmd[i] = FP_SELA(0,W,NO,FP_TMP(0),0,0);
 276         }
 277
 278         r300->hw.unk4BC0.cmd[1] = 0;
 279
 280         r300->hw.unk4BC8.cmd[1] = 0;
 281         r300->hw.unk4BC8.cmd[2] = 0;
 282         r300->hw.unk4BC8.cmd[3] = 0;
 283
 284         r300->hw.at.cmd[R300_AT_ALPHA_TEST] = 0;
 285
 286         r300->hw.unk4BD8.cmd[1] = 0;
 287
 288         r300->hw.unk4E00.cmd[1] = 0;
 289
 290         r300->hw.bld.cmd[R300_BLD_CBLEND] = 0;
 291         r300->hw.bld.cmd[R300_BLD_ABLEND] = 0;
 292
 293         r300->hw.unk4E10.cmd[1] = 0;
 294         r300->hw.unk4E10.cmd[2] = 0;
 295         r300->hw.unk4E10.cmd[3] = 0;
 296
 297         r300->hw.cb.cmd[R300_CB_OFFSET] =
 298                 r300->radeon.radeonScreen->backOffset +
 299                 r300->radeon.radeonScreen->fbLocation;
 300         r300->hw.cb.cmd[R300_CB_PITCH] = r300->radeon.radeonScreen->backPitch
 301                 | R300_COLOR_UNKNOWN_22_23;
 302
 303         r300->hw.unk4E50.cmd[1] = 0;
 304         r300->hw.unk4E50.cmd[2] = 0;
 305         r300->hw.unk4E50.cmd[3] = 0;
 306         r300->hw.unk4E50.cmd[4] = 0;
 307         r300->hw.unk4E50.cmd[5] = 0;
 308         r300->hw.unk4E50.cmd[6] = 0;
 309         r300->hw.unk4E50.cmd[7] = 0;
 310         r300->hw.unk4E50.cmd[8] = 0;
 311         r300->hw.unk4E50.cmd[9] = 0;
 312
 313         r300->hw.unk4E88.cmd[1] = 0;
 314
 315         r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0;
 316         r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0;
 317
 318         r300->hw.unk4F08.cmd[1] = 0x00FFFF00;
 319
 320         r300->hw.unk4F10.cmd[1] = 0x00000002; // depthbuffer format?
 321         r300->hw.unk4F10.cmd[2] = 0x00000000;
 322         r300->hw.unk4F10.cmd[3] = 0x00000003;
 323         r300->hw.unk4F10.cmd[4] = 0x00000000;
 324
 325         r300->hw.zb.cmd[R300_ZB_OFFSET] =
 326                 r300->radeon.radeonScreen->depthOffset +
 327                 r300->radeon.radeonScreen->fbLocation;
 328         r300->hw.zb.cmd[R300_ZB_PITCH] = r300->radeon.radeonScreen->depthPitch;
 329
 330         r300->hw.unk4F28.cmd[1] = 0;
 331
 332         r300->hw.unk4F30.cmd[1] = 0;
 333         r300->hw.unk4F30.cmd[2] = 0;
 334
 335         r300->hw.unk4F44.cmd[1] = 0;
 336
 337         r300->hw.unk4F54.cmd[1] = 0;
 338
 339         ((drm_r300_cmd_header_t*)r300->hw.vpi.cmd)->vpu.count = 0;
 340         for(i = 1; i < R300_VPI_CMDSIZE; i += 4) {
 341                 /* MOV t0, t0 */
 342                 r300->hw.vpi.cmd[i+0] = VP_OUT(ADD,TMP,0,XYZW);
 343                 r300->hw.vpi.cmd[i+1] = VP_IN(TMP,0);
 344                 r300->hw.vpi.cmd[i+2] = VP_ZERO();
 345                 r300->hw.vpi.cmd[i+3] = VP_ZERO();
 346         }
 347
 348         ((drm_r300_cmd_header_t*)r300->hw.vpp.cmd)->vpu.count = 0;
 349         for(i = 1; i < R300_VPP_CMDSIZE; ++i)
 350                 r300->hw.vpp.cmd[i] = 0;
 351
 352         r300->hw.vps.cmd[R300_VPS_ZERO_0] = 0;
 353         r300->hw.vps.cmd[R300_VPS_ZERO_1] = 0;
 354         r300->hw.vps.cmd[R300_VPS_POINTSIZE] = r300PackFloat32(1.0);
 355         r300->hw.vps.cmd[R300_VPS_ZERO_3] = 0;
 356 //END: TODO
 357
 358         r300->hw.all_dirty = GL_TRUE;
 359 }
 360
 361
 362
 363 /**
 364  * Calculate initial hardware state and register state functions.
 365  * Assumes that the command buffer and state atoms have been
 366  * initialized already.
 367  */
 368 void r300InitState(r300ContextPtr r300)
 369 {
 370         radeonInitState(&r300->radeon);
 371
 372         r300ResetHwState(r300);
 373 }
 374
 375
 376 /**
 377  * Initialize driver's state callback functions
 378  */
 379 void r300InitStateFuncs(struct dd_function_table* functions)
 380 {
 381         radeonInitStateFuncs(functions);
 382
 383         functions->UpdateState = r300InvalidateState;
 384         functions->Enable = r300Enable;
 385         functions->ColorMask = r300ColorMask;
 386 }
 387