5 This file contains registers and constants for the R300. They have been
6 found mostly by examining command buffers captured using glxtest, as well
7 as by extrapolating some known registers and constants from the R200.
9 I am fairly certain that they are correct unless stated otherwise in comments.
12 #define R300_SE_VPORT_XSCALE 0x1D98
13 #define R300_SE_VPORT_XOFFSET 0x1D9C
14 #define R300_SE_VPORT_YSCALE 0x1DA0
15 #define R300_SE_VPORT_YOFFSET 0x1DA4
16 #define R300_SE_VPORT_ZSCALE 0x1DA8
17 #define R300_SE_VPORT_ZOFFSET 0x1DAC
20 /* This register is written directly and also starts data section in many 3d CP_PACKET3's */
21 #define R300_VAP_VF_CNTL 0x2084
23 # define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0
24 # define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)
25 # define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)
26 # define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)
27 # define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)
28 # define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)
29 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)
30 # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)
31 # define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)
32 # define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)
33 # define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)
34 # define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)
36 # define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4
37 /* State based - direct writes to registers trigger vertex generation */
38 # define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)
39 # define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)
40 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)
41 # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)
43 /* I don't think I saw these three used.. */
44 # define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6
45 # define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9
46 # define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10
48 /* index size - when not set the indices are assumed to be 16 bit */
49 # define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)
50 /* number of vertices */
51 # define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16
53 /* BEGIN: Wild guesses */
54 #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090
55 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)
56 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)
57 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */
58 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */
59 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */
60 # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */
62 #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094
63 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
64 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
65 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
66 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
67 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
68 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
69 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
70 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
73 #define R300_SE_VTE_CNTL 0x20b0
74 # define R300_VPORT_X_SCALE_ENA 0x00000001
75 # define R300_VPORT_X_OFFSET_ENA 0x00000002
76 # define R300_VPORT_Y_SCALE_ENA 0x00000004
77 # define R300_VPORT_Y_OFFSET_ENA 0x00000008
78 # define R300_VPORT_Z_SCALE_ENA 0x00000010
79 # define R300_VPORT_Z_OFFSET_ENA 0x00000020
80 # define R300_VTX_XY_FMT 0x00000100
81 # define R300_VTX_Z_FMT 0x00000200
82 # define R300_VTX_W0_FMT 0x00000400
83 # define R300_VTX_W0_NORMALIZE 0x00000800
84 # define R300_VTX_ST_DENORMALIZED 0x00001000
86 /* BEGIN: Vertex data assembly - lots of uncertainties */
88 /* Where do we get our vertex data?
90 // Vertex data either comes either from immediate mode registers or from
92 // There appears to be no mixed mode (though we can force the pitch of
93 // vertex arrays to 0, effectively reusing the same element over and over
96 // Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
97 // if these registers influence vertex array processing.
99 // Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
101 // In both cases, vertex attributes are then passed through INPUT_ROUTE.
103 // Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
104 // into the vertex processor's input registers.
105 // The first word routes the first input, the second word the second, etc.
106 // The corresponding input is routed into the register with the given index.
107 // The list is ended by a word with INPUT_ROUTE_END set.
109 // Always set COMPONENTS_4 in immediate mode. */
111 #define R300_VAP_INPUT_ROUTE_0_0 0x2150
112 # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)
113 # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)
114 # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)
115 # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)
116 # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */
117 # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8
118 # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */
119 # define R300_VAP_INPUT_ROUTE_END (1 << 13)
120 # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */
121 # define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */
122 # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */
123 # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */
124 #define R300_VAP_INPUT_ROUTE_0_1 0x2154
125 #define R300_VAP_INPUT_ROUTE_0_2 0x2158
126 #define R300_VAP_INPUT_ROUTE_0_3 0x215C
130 // - always set up to produce at least two attributes:
131 // if vertex program uses only position, fglrx will set normal, too
132 // - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal */
133 #define R300_VAP_INPUT_CNTL_0 0x2180
134 # define R300_INPUT_CNTL_0_COLOR 0x00000001
135 #define R300_VAP_INPUT_CNTL_1 0x2184
136 # define R300_INPUT_CNTL_POS 0x00000001
137 # define R300_INPUT_CNTL_NORMAL 0x00000002
138 # define R300_INPUT_CNTL_COLOR 0x00000004
139 # define R300_INPUT_CNTL_TC0 0x00000400
140 # define R300_INPUT_CNTL_TC1 0x00000800
141 # define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */
142 # define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */
143 # define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */
144 # define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */
145 # define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */
146 # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */
149 /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
150 // are set to a swizzling bit pattern, other words are 0.
152 // In immediate mode, the pattern is always set to xyzw. In vertex array
153 // mode, the swizzling pattern is e.g. used to set zw components in texture
154 // coordinates with only tweo components. */
155 #define R300_VAP_INPUT_ROUTE_1_0 0x21E0
156 # define R300_INPUT_ROUTE_SELECT_X 0
157 # define R300_INPUT_ROUTE_SELECT_Y 1
158 # define R300_INPUT_ROUTE_SELECT_Z 2
159 # define R300_INPUT_ROUTE_SELECT_W 3
160 # define R300_INPUT_ROUTE_SELECT_ZERO 4
161 # define R300_INPUT_ROUTE_SELECT_ONE 5
162 # define R300_INPUT_ROUTE_SELECT_MASK 7
163 # define R300_INPUT_ROUTE_X_SHIFT 0
164 # define R300_INPUT_ROUTE_Y_SHIFT 3
165 # define R300_INPUT_ROUTE_Z_SHIFT 6
166 # define R300_INPUT_ROUTE_W_SHIFT 9
167 # define R300_INPUT_ROUTE_ENABLE (15 << 12)
168 #define R300_VAP_INPUT_ROUTE_1_1 0x21E4
169 #define R300_VAP_INPUT_ROUTE_1_2 0x21E8
170 #define R300_VAP_INPUT_ROUTE_1_3 0x21EC
175 /* BEGIN: Upload vertex program and data
176 // The programmable vertex shader unit has a memory bank of unknown size
177 // that can be written to in 16 byte units by writing the address into
178 // UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
180 // Pointers into the memory bank are always in multiples of 16 bytes.
182 // The memory bank is divided into areas with fixed meaning.
184 // Starting at address UPLOAD_PROGRAM: Vertex program instructions.
185 // Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
186 // whereas the difference between known addresses suggests size 512.
188 // Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
189 // Native reported limits and the VPI layout suggest size 256, whereas
190 // difference between known addresses suggests size 512.
192 // At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
193 // floating point pointsize. The exact purpose of this state is uncertain,
194 // as there is also the R300_RE_POINTSIZE register.
196 // Multiple vertex programs and parameter sets can be loaded at once,
197 // which could explain the size discrepancy. */
198 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200
199 # define R300_PVS_UPLOAD_PROGRAM 0x00000000
200 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200
201 # define R300_PVS_UPLOAD_POINTSIZE 0x00000406
203 #define R300_VAP_PVS_UPLOAD_DATA 0x2208
207 /* I do not know the purpose of this register. However, I do know that
208 // it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
209 // for normal rendering. */
210 #define R300_VAP_UNKNOWN_221C 0x221C
211 # define R300_221C_NORMAL 0x00000000
212 # define R300_221C_CLEAR 0x0001C000
215 /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
216 // rendering commands and overwriting vertex program parameters.
217 // Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
218 // avoids bugs caused by still running shaders reading bad data from memory. */
219 #define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */
221 /* Absolutely no clue what this register is about. */
222 #define R300_VAP_UNKNOWN_2288 0x2288
223 # define R300_2288_R300 0x00750000 /* -- nh */
224 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
227 /* Addresses are relative to the vertex program instruction area of the
228 // memory bank. PROGRAM_END points to the last instruction of the active
231 // The meaning of the two UNKNOWN fields is obviously not known. However,
232 // experiments so far have shown that both *must* point to an instruction
233 // inside the vertex program, otherwise the GPU locks up.
234 // fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
235 // CNTL_1_UNKNOWN somewhere in the middle, but the criteria are not clear. */
236 #define R300_VAP_PVS_CNTL_1 0x22D0
237 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0
238 # define R300_PVS_CNTL_1_UNKNOWN_SHIFT 10
239 # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20
240 /* Addresses are relative the the vertex program parameters area. */
241 #define R300_VAP_PVS_CNTL_2 0x22D4
242 # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
243 # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16
244 #define R300_VAP_PVS_CNTL_3 0x22D8
245 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10
246 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0
248 /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
249 // immediate vertices */
250 #define R300_VAP_VTX_COLOR_R 0x2464
251 #define R300_VAP_VTX_COLOR_G 0x2468
252 #define R300_VAP_VTX_COLOR_B 0x246C
253 #define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */
254 #define R300_VAP_VTX_POS_0_Y_1 0x2494
255 #define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */
256 #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */
257 #define R300_VAP_VTX_POS_0_Y_2 0x24A4
258 #define R300_VAP_VTX_POS_0_Z_2 0x24A8
259 #define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */
263 /* These are values from r300_reg/r300_reg.h - they are known to be correct
264 and are here so we can use one register file instead of several
266 #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000
267 # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)
268 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
269 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
270 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
271 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
272 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)
273 # define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)
275 #define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004
276 /* each of the following is 3 bits wide, specifies number
278 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
279 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
280 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
281 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
282 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
283 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
284 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
285 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
287 #define R300_GB_ENABLE 0x4008
288 # define R300_GB_POINT_STUFF_ENABLE (1<<0)
289 # define R300_GB_LINE_STUFF_ENABLE (1<<1)
290 # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2)
291 # define R300_GB_STENCIL_AUTO_ENABLE (1<<4)
292 /* each of the following is 2 bits wide */
293 #define R300_GB_TEX_REPLICATE 0
294 #define R300_GB_TEX_ST 1
295 #define R300_GB_TEX_STR 2
296 # define R300_GB_TEX0_SOURCE_SHIFT 16
297 # define R300_GB_TEX1_SOURCE_SHIFT 18
298 # define R300_GB_TEX2_SOURCE_SHIFT 20
299 # define R300_GB_TEX3_SOURCE_SHIFT 22
300 # define R300_GB_TEX4_SOURCE_SHIFT 24
301 # define R300_GB_TEX5_SOURCE_SHIFT 26
302 # define R300_GB_TEX6_SOURCE_SHIFT 28
303 # define R300_GB_TEX7_SOURCE_SHIFT 30
305 /* MSPOS - positions for multisample antialiasing (?) */
306 #define R300_GB_MSPOS0 0x4010
307 /* shifts - each of the fields is 4 bits */
308 # define R300_GB_MSPOS0__MS_X0_SHIFT 0
309 # define R300_GB_MSPOS0__MS_Y0_SHIFT 4
310 # define R300_GB_MSPOS0__MS_X1_SHIFT 8
311 # define R300_GB_MSPOS0__MS_Y1_SHIFT 12
312 # define R300_GB_MSPOS0__MS_X2_SHIFT 16
313 # define R300_GB_MSPOS0__MS_Y2_SHIFT 20
314 # define R300_GB_MSPOS0__MSBD0_Y 24
315 # define R300_GB_MSPOS0__MSBD0_X 28
317 #define R300_GB_MSPOS1 0x4014
318 # define R300_GB_MSPOS1__MS_X3_SHIFT 0
319 # define R300_GB_MSPOS1__MS_Y3_SHIFT 4
320 # define R300_GB_MSPOS1__MS_X4_SHIFT 8
321 # define R300_GB_MSPOS1__MS_Y4_SHIFT 12
322 # define R300_GB_MSPOS1__MS_X5_SHIFT 16
323 # define R300_GB_MSPOS1__MS_Y5_SHIFT 20
324 # define R300_GB_MSPOS1__MSBD1 24
327 #define R300_GB_TILE_CONFIG 0x4018
328 # define R300_GB_TILE_ENABLE (1<<0)
329 # define R300_GB_TILE_PIPE_COUNT_RV300 0
330 # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)
331 # define R300_GB_TILE_SIZE_8 0
332 # define R300_GB_TILE_SIZE_16 (1<<4)
333 # define R300_GB_TILE_SIZE_32 (2<<4)
334 # define R300_GB_SUPER_SIZE_1 (0<<6)
335 # define R300_GB_SUPER_SIZE_2 (1<<6)
336 # define R300_GB_SUPER_SIZE_4 (2<<6)
337 # define R300_GB_SUPER_SIZE_8 (3<<6)
338 # define R300_GB_SUPER_SIZE_16 (4<<6)
339 # define R300_GB_SUPER_SIZE_32 (5<<6)
340 # define R300_GB_SUPER_SIZE_64 (6<<6)
341 # define R300_GB_SUPER_SIZE_128 (7<<6)
342 # define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */
343 # define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */
344 # define R300_GB_SUPER_TILE_A 0
345 # define R300_GB_SUPER_TILE_B (1<<15)
346 # define R300_GB_SUBPIXEL_1_12 0
347 # define R300_GB_SUBPIXEL_1_16 (1<<16)
349 #define R300_GB_FIFO_SIZE 0x4024
350 /* each of the following is 2 bits wide */
351 #define R300_GB_FIFO_SIZE_32 0
352 #define R300_GB_FIFO_SIZE_64 1
353 #define R300_GB_FIFO_SIZE_128 2
354 #define R300_GB_FIFO_SIZE_256 3
355 # define R300_SC_IFIFO_SIZE_SHIFT 0
356 # define R300_SC_TZFIFO_SIZE_SHIFT 2
357 # define R300_SC_BFIFO_SIZE_SHIFT 4
359 # define R300_US_OFIFO_SIZE_SHIFT 12
360 # define R300_US_WFIFO_SIZE_SHIFT 14
361 /* the following use the same constants as above, but meaning is
362 is times 2 (i.e. instead of 32 words it means 64 */
363 # define R300_RS_TFIFO_SIZE_SHIFT 6
364 # define R300_RS_CFIFO_SIZE_SHIFT 8
365 # define R300_US_RAM_SIZE_SHIFT 10
366 /* watermarks, 3 bits wide */
367 # define R300_RS_HIGHWATER_COL_SHIFT 16
368 # define R300_RS_HIGHWATER_TEX_SHIFT 19
369 # define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */
370 # define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24
372 #define R300_GB_SELECT 0x401C
373 # define R300_GB_FOG_SELECT_C0A 0
374 # define R300_GB_FOG_SELECT_C1A 1
375 # define R300_GB_FOG_SELECT_C2A 2
376 # define R300_GB_FOG_SELECT_C3A 3
377 # define R300_GB_FOG_SELECT_1_1_W 4
378 # define R300_GB_FOG_SELECT_Z 5
379 # define R300_GB_DEPTH_SELECT_Z 0
380 # define R300_GB_DEPTH_SELECT_1_1_W (1<<3)
381 # define R300_GB_W_SELECT_1_W 0
382 # define R300_GB_W_SELECT_1 (1<<4)
384 #define R300_GB_AA_CONFIG 0x4020
385 # define R300_AA_ENABLE 0x01
386 # define R300_AA_SUBSAMPLES_2 0
387 # define R300_AA_SUBSAMPLES_3 (1<<1)
388 # define R300_AA_SUBSAMPLES_4 (2<<1)
389 # define R300_AA_SUBSAMPLES_6 (3<<1)
394 /* The upper enable bits are guessed, based on fglrx reported limits. */
395 #define R300_TX_ENABLE 0x4104
396 # define R300_TX_ENABLE_0 (1 << 0)
397 # define R300_TX_ENABLE_1 (1 << 1)
398 # define R300_TX_ENABLE_2 (1 << 2)
399 # define R300_TX_ENABLE_3 (1 << 3)
400 # define R300_TX_ENABLE_4 (1 << 4)
401 # define R300_TX_ENABLE_5 (1 << 5)
402 # define R300_TX_ENABLE_6 (1 << 6)
403 # define R300_TX_ENABLE_7 (1 << 7)
404 # define R300_TX_ENABLE_8 (1 << 8)
405 # define R300_TX_ENABLE_9 (1 << 9)
406 # define R300_TX_ENABLE_10 (1 << 10)
407 # define R300_TX_ENABLE_11 (1 << 11)
408 # define R300_TX_ENABLE_12 (1 << 12)
409 # define R300_TX_ENABLE_13 (1 << 13)
410 # define R300_TX_ENABLE_14 (1 << 14)
411 # define R300_TX_ENABLE_15 (1 << 15)
413 /* The pointsize is given in multiples of 6. The pointsize can be
414 // enormous: Clear() renders a single point that fills the entire
416 #define R300_RE_POINTSIZE 0x421C
417 # define R300_POINTSIZE_Y_SHIFT 0
418 # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */
419 # define R300_POINTSIZE_X_SHIFT 16
420 # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */
422 /* This register needs to be set to (1<<1) for RV350 to correctly
423 perform depth test (see --vb-triangles in r300_demo)
424 Don't know about other chips. - Vladimir
426 #define R300_RE_OCCLUSION_CNTL 0x42B4
427 # define R300_OCCLUSION_ON (1<<1)
429 #define R300_RE_CULL_CNTL 0x42B8
430 # define R300_CULL_FRONT (1 << 0)
431 # define R300_CULL_BACK (1 << 1)
432 # define R300_FRONT_FACE_CCW (0 << 2)
433 # define R300_FRONT_FACE_CW (1 << 2)
436 /* BEGIN: Rasterization / Interpolators - many guesses
437 // So far, 0_UNKOWN_7 has always been set.
438 // 0_UNKNOWN_18 has always been set except for clear operations.
439 // TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
440 // on the vertex program, *not* the fragment program) */
441 #define R300_RS_CNTL_0 0x4300
442 # define R300_RS_CNTL_TC_CNT_SHIFT 2
443 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2)
444 # define R300_RS_CNTL_0_UNKNOWN_7 (1 << 7)
445 # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)
446 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */
447 #define R300_RS_CNTL_1 0x4304
450 /* Only used for texture coordinates (color seems to be always interpolated).
451 // Use the source field to route texture coordinate input from the vertex program
452 // to the desired interpolator. Note that the source field is relative to the
453 // outputs the vertex program *actually* writes. If a vertex program only writes
454 // texcoord[1], this will be source index 0.
455 // Set INTERP_USED on all interpolators that produce data used by the
456 // fragment program. INTERP_USED looks like a swizzling mask, but
457 // I haven't seen it used that way.
459 // Note: The _UNKNOWN constants are always set in their respective register.
460 // I don't know if this is necessary. */
461 #define R300_RS_INTERP_0 0x4310
462 #define R300_RS_INTERP_1 0x4314
463 # define R300_RS_INTERP_1_UNKNOWN 0x40
464 #define R300_RS_INTERP_2 0x4318
465 # define R300_RS_INTERP_2_UNKNOWN 0x80
466 #define R300_RS_INTERP_3 0x431C
467 # define R300_RS_INTERP_3_UNKNOWN 0xC0
468 #define R300_RS_INTERP_4 0x4320
469 #define R300_RS_INTERP_5 0x4324
470 #define R300_RS_INTERP_6 0x4328
471 #define R300_RS_INTERP_7 0x432C
472 # define R300_RS_INTERP_SRC_SHIFT 2
473 # define R300_RS_INTERP_SRC_MASK (7 << 2)
474 # define R300_RS_INTERP_USED 0x00D10000
476 /* These DWORDs control how vertex data is routed into fragment program
477 // registers, after interpolators. */
478 #define R300_RS_ROUTE_0 0x4330
479 #define R300_RS_ROUTE_1 0x4334
480 #define R300_RS_ROUTE_2 0x4338
481 #define R300_RS_ROUTE_3 0x433C /* GUESS */
482 #define R300_RS_ROUTE_4 0x4340 /* GUESS */
483 #define R300_RS_ROUTE_5 0x4344 /* GUESS */
484 #define R300_RS_ROUTE_6 0x4348 /* GUESS */
485 #define R300_RS_ROUTE_7 0x434C /* GUESS */
486 # define R300_RS_ROUTE_SOURCE_INTERP_0 0
487 # define R300_RS_ROUTE_SOURCE_INTERP_1 1
488 # define R300_RS_ROUTE_SOURCE_INTERP_2 2
489 # define R300_RS_ROUTE_SOURCE_INTERP_3 3
490 # define R300_RS_ROUTE_SOURCE_INTERP_4 4
491 # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */
492 # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */
493 # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */
494 # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */
495 # define R300_RS_ROUTE_DEST_SHIFT 6
496 # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */
498 /* Special handling for color: When the fragment program uses color,
499 // the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the
500 // color register index. */
501 # define R300_RS_ROUTE_0_COLOR (1 << 14)
502 # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT (1 << 17)
503 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 6) /* GUESS */
506 /* BEGIN: Scissors and cliprects
507 // There are four clipping rectangles. Their corner coordinates are inclusive.
508 // Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
509 // on whether the pixel is inside cliprects 0-3, respectively. For example,
510 // if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
511 // the number 3 (binary 0011).
512 // Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
513 // the pixel is rasterized.
515 // In addition to this, there is a scissors rectangle. Only pixels inside the
516 // scissors rectangle are drawn. (coordinates are inclusive)
518 // For some reason, the top-left corner of the framebuffer is at (1440, 1440)
519 // for the purpose of clipping and scissors. */
520 #define R300_RE_CLIPRECT_TL_0 0x43B0
521 #define R300_RE_CLIPRECT_BR_0 0x43B4
522 #define R300_RE_CLIPRECT_TL_1 0x43B8
523 #define R300_RE_CLIPRECT_BR_1 0x43BC
524 #define R300_RE_CLIPRECT_TL_2 0x43C0
525 #define R300_RE_CLIPRECT_BR_2 0x43C4
526 #define R300_RE_CLIPRECT_TL_3 0x43C8
527 #define R300_RE_CLIPRECT_BR_3 0x43CC
528 # define R300_CLIPRECT_OFFSET 1440
529 # define R300_CLIPRECT_MASK 0x1FFF
530 # define R300_CLIPRECT_X_SHIFT 0
531 # define R300_CLIPRECT_X_MASK (0x1FFF << 0)
532 # define R300_CLIPRECT_Y_SHIFT 13
533 # define R300_CLIPRECT_Y_MASK (0x1FFF << 13)
534 #define R300_RE_CLIPRECT_CNTL 0x43D0
535 # define R300_CLIP_OUT (1 << 0)
536 # define R300_CLIP_0 (1 << 1)
537 # define R300_CLIP_1 (1 << 2)
538 # define R300_CLIP_10 (1 << 3)
539 # define R300_CLIP_2 (1 << 4)
540 # define R300_CLIP_20 (1 << 5)
541 # define R300_CLIP_21 (1 << 6)
542 # define R300_CLIP_210 (1 << 7)
543 # define R300_CLIP_3 (1 << 8)
544 # define R300_CLIP_30 (1 << 9)
545 # define R300_CLIP_31 (1 << 10)
546 # define R300_CLIP_310 (1 << 11)
547 # define R300_CLIP_32 (1 << 12)
548 # define R300_CLIP_320 (1 << 13)
549 # define R300_CLIP_321 (1 << 14)
550 # define R300_CLIP_3210 (1 << 15)
553 #define R300_RE_SCISSORS_TL 0x43E0
554 #define R300_RE_SCISSORS_BR 0x43E4
555 # define R300_SCISSORS_OFFSET 1440
556 # define R300_SCISSORS_X_SHIFT 0
557 # define R300_SCISSORS_X_MASK (0x1FFF << 0)
558 # define R300_SCISSORS_Y_SHIFT 13
559 # define R300_SCISSORS_Y_MASK (0x1FFF << 13)
562 /* BEGIN: Texture specification
563 // The texture specification dwords are grouped by meaning and not by texture unit.
564 // This means that e.g. the offset for texture image unit N is found in register
565 // TX_OFFSET_0 + (4*N) */
566 #define R300_TX_FILTER_0 0x4400
567 # define R300_TX_REPEAT 0
568 # define R300_TX_CLAMP_TO_EDGE 1
569 # define R300_TX_CLAMP 2
570 # define R300_TX_CLAMP_TO_BORDER 3
572 # define R300_TX_WRAP_S_SHIFT 1
573 # define R300_TX_WRAP_S_MASK (3 << 1)
574 # define R300_TX_WRAP_T_SHIFT 4
575 # define R300_TX_WRAP_T_MASK (3 << 4)
576 # define R300_TX_MAG_FILTER_NEAREST (1 << 9)
577 # define R300_TX_MAG_FILTER_LINEAR (2 << 9)
578 # define R300_TX_MAG_FILTER_MASK (3 << 9)
579 # define R300_TX_MIN_FILTER_NEAREST (1 << 11)
580 # define R300_TX_MIN_FILTER_LINEAR (2 << 11)
581 #define R300_TX_UNK1_0 0x4440
582 #define R300_TX_SIZE_0 0x4480
583 # define R300_TX_WIDTHMASK_SHIFT 0
584 # define R300_TX_WIDTHMASK_MASK (2047 << 0)
585 # define R300_TX_HEIGHTMASK_SHIFT 11
586 # define R300_TX_HEIGHTMASK_MASK (2047 << 11)
587 # define R300_TX_SIZE_SHIFT 26 /* largest of width, height */
588 # define R300_TX_SIZE_MASK (15 << 26)
589 #define R300_TX_FORMAT_0 0x44C0
590 /* Note - other bits are not known yet.. */
591 # define R300_TX_FORMAT_WIDTH_SHIFT 12
592 # define R300_TX_FORMAT_WIDTH_MASK (0xf<<R300_TX_FORMAT_WIDTH_SHIFT)
593 # define R300_TX_FORMAT_HEIGHT_SHIFT 16
594 # define R300_TX_FORMAT_HEIGHT_MASK (0xf<<R300_TX_FORMAT_HEIGHT_SHIFT)
595 #define R300_TX_OFFSET_0 0x4540
596 /* BEGIN: Guess from R200 */
597 # define R300_TXO_ENDIAN_NO_SWAP (0 << 0)
598 # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)
599 # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)
600 # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
601 # define R300_TXO_OFFSET_MASK 0xffffffe0
602 # define R300_TXO_OFFSET_SHIFT 5
604 #define R300_TX_UNK4_0 0x4580
605 #define R300_TX_UNK5_0 0x45C0
608 /* BEGIN: Fragment program instruction set
609 // Fragment programs are written directly into register space.
610 // There are separate instruction streams for texture instructions and ALU
612 // In order to synchronize these streams, the program is divided into up
613 // to 4 nodes. Each node begins with a number of TEX operations, followed
614 // by a number of ALU operations.
615 // The first node can have zero TEX ops, all subsequent nodes must have at least
617 // All nodes must have at least one ALU op.
619 // The index of the last node is stored in PFS_CNTL_0: A value of 0 means
620 // 1 node, a value of 3 means 4 nodes.
621 // The total amount of instructions is defined in PFS_CNTL_2. The offsets are
622 // offsets into the respective instruction streams, while *_END points to the
623 // last instruction relative to this offset. */
624 #define R300_PFS_CNTL_0 0x4600
625 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0
626 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)
627 # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)
628 #define R300_PFS_CNTL_1 0x4604
629 /* There is an unshifted value here which has so far always been equal to the
630 // index of the highest used temporary register. */
631 #define R300_PFS_CNTL_2 0x4608
632 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0
633 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)
634 # define R300_PFS_CNTL_ALU_END_SHIFT 6
635 # define R300_PFS_CNTL_ALU_END_MASK (63 << 0)
636 # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12
637 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */
638 # define R300_PFS_CNTL_TEX_END_SHIFT 18
639 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */
642 /* Nodes are stored backwards. The last active node is always stored in
644 // Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
645 // first node is stored in NODE_2, the second node is stored in NODE_3.
647 // Offsets are relative to the master offset from PFS_CNTL_2.
648 // LAST_NODE is set for the last node, and only for the last node. */
649 #define R300_PFS_NODE_0 0x4610
650 #define R300_PFS_NODE_1 0x4614
651 #define R300_PFS_NODE_2 0x4618
652 #define R300_PFS_NODE_3 0x461C
653 # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0
654 # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0)
655 # define R300_PFS_NODE_ALU_END_SHIFT 6
656 # define R300_PFS_NODE_ALU_END_MASK (63 << 6)
657 # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12
658 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)
659 # define R300_PFS_NODE_TEX_END_SHIFT 17
660 # define R300_PFS_NODE_TEX_END_MASK (31 << 17)
661 # define R300_PFS_NODE_LAST_NODE (1 << 22)
664 // As far as I can tell, texture instructions cannot write into output
665 // registers directly. A subsequent ALU instruction is always necessary,
666 // even if it's just MAD o0, r0, 1, 0 */
667 #define R300_PFS_TEXI_0 0x4620
668 # define R300_FPITX_SRC_SHIFT 0
669 # define R300_FPITX_SRC_MASK (31 << 0)
670 # define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */
671 # define R300_FPITX_DST_SHIFT 6
672 # define R300_FPITX_DST_MASK (31 << 6)
673 # define R300_FPITX_IMAGE_SHIFT 11
674 # define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */
677 // The ALU instructions register blocks are enumerated according to the order
678 // in which fglrx. I assume there is space for 64 instructions, since
679 // each block has space for a maximum of 64 DWORDs, and this matches reported
682 // The basic functional block seems to be one MAD for each color and alpha,
683 // and an adder that adds all components after the MUL.
684 // - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
685 // - DP4: Use OUTC_DP4, OUTA_DP4
686 // - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
687 // - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
688 // - CMP: If ARG2 < 0, return ARG1, else return ARG0
689 // - FLR: use FRC+MAD
690 // - XPD: use MAD+MAD
691 // - SGE, SLT: use MAD+CMP
692 // - RSQ: use ABS modifier for argument
693 // - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP)
694 // into color register
695 // - apparently, there's no quick DST operation
696 // - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
697 // - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
698 // - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
701 // First stage selects three sources from the available registers and
702 // constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
703 // fglrx sorts the three source fields: Registers before constants,
704 // lower indices before higher indices; I do not know whether this is necessary.
705 // fglrx fills unused sources with "read constant 0"
706 // According to specs, you cannot select more than two different constants.
708 // Second stage selects the operands from the sources. This is defined in
709 // INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
711 // Swizzling and negation happens in this stage, as well.
713 // Important: Color and alpha seem to be mostly separate, i.e. their sources
714 // selection appears to be fully independent (the register storage is probably
715 // physically split into a color and an alpha section).
716 // However (because of the apparent physical split), there is some interaction
717 // WRT swizzling. If, for example, you want to load an R component into an
718 // Alpha operand, this R component is taken from a *color* source, not from
719 // an alpha source. The corresponding register doesn't even have to appear in
720 // the alpha sources list. (I hope this alll makes sense to you)
722 // Destination selection
723 // The destination register index is in FPI1 (color) and FPI3 (alpha) together
725 // There are separate enable bits for writing into temporary registers
726 // (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* /DSTA_OUTPUT).
727 // You can write to both at once, or not write at all (the same index
728 // must be used for both).
730 // Note: There is a special form for LRP
731 // - Argument order is the same as in ARB_fragment_program.
732 // - Operation is MAD
733 // - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
734 // - Set FPI0/FPI2_SPECIAL_LRP
735 // Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */
736 #define R300_PFS_INSTR1_0 0x46C0
737 # define R300_FPI1_SRC0C_SHIFT 0
738 # define R300_FPI1_SRC0C_MASK (31 << 0)
739 # define R300_FPI1_SRC0C_CONST (1 << 5)
740 # define R300_FPI1_SRC1C_SHIFT 6
741 # define R300_FPI1_SRC1C_MASK (31 << 6)
742 # define R300_FPI1_SRC1C_CONST (1 << 11)
743 # define R300_FPI1_SRC2C_SHIFT 12
744 # define R300_FPI1_SRC2C_MASK (31 << 12)
745 # define R300_FPI1_SRC2C_CONST (1 << 17)
746 # define R300_FPI1_DSTC_SHIFT 18
747 # define R300_FPI1_DSTC_MASK (31 << 18)
748 # define R300_FPI1_DSTC_REG_X (1 << 23)
749 # define R300_FPI1_DSTC_REG_Y (1 << 24)
750 # define R300_FPI1_DSTC_REG_Z (1 << 25)
751 # define R300_FPI1_DSTC_OUTPUT_X (1 << 26)
752 # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27)
753 # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28)
755 #define R300_PFS_INSTR3_0 0x47C0
756 # define R300_FPI3_SRC0A_SHIFT 0
757 # define R300_FPI3_SRC0A_MASK (31 << 0)
758 # define R300_FPI3_SRC0A_CONST (1 << 5)
759 # define R300_FPI3_SRC1A_SHIFT 6
760 # define R300_FPI3_SRC1A_MASK (31 << 6)
761 # define R300_FPI3_SRC1A_CONST (1 << 11)
762 # define R300_FPI3_SRC2A_SHIFT 12
763 # define R300_FPI3_SRC2A_MASK (31 << 12)
764 # define R300_FPI3_SRC2A_CONST (1 << 17)
765 # define R300_FPI3_DSTA_SHIFT 18
766 # define R300_FPI3_DSTA_MASK (31 << 18)
767 # define R300_FPI3_DSTA_REG (1 << 23)
768 # define R300_FPI3_DSTA_OUTPUT (1 << 24)
770 #define R300_PFS_INSTR0_0 0x48C0
771 # define R300_FPI0_ARGC_SRC0C_XYZ 0
772 # define R300_FPI0_ARGC_SRC0C_XXX 1
773 # define R300_FPI0_ARGC_SRC0C_YYY 2
774 # define R300_FPI0_ARGC_SRC0C_ZZZ 3
775 # define R300_FPI0_ARGC_SRC1C_XYZ 4
776 # define R300_FPI0_ARGC_SRC1C_XXX 5
777 # define R300_FPI0_ARGC_SRC1C_YYY 6
778 # define R300_FPI0_ARGC_SRC1C_ZZZ 7
779 # define R300_FPI0_ARGC_SRC2C_XYZ 8
780 # define R300_FPI0_ARGC_SRC2C_XXX 9
781 # define R300_FPI0_ARGC_SRC2C_YYY 10
782 # define R300_FPI0_ARGC_SRC2C_ZZZ 11
783 # define R300_FPI0_ARGC_SRC0A 12
784 # define R300_FPI0_ARGC_SRC1A 13
785 # define R300_FPI0_ARGC_SRC2A 14
786 # define R300_FPI0_ARGC_SRC1C_LRP 15
787 # define R300_FPI0_ARGC_ZERO 20
788 # define R300_FPI0_ARGC_ONE 21
789 # define R300_FPI0_ARGC_HALF 22 /* GUESS */
790 # define R300_FPI0_ARGC_SRC0C_YZX 23
791 # define R300_FPI0_ARGC_SRC1C_YZX 24
792 # define R300_FPI0_ARGC_SRC2C_YZX 25
793 # define R300_FPI0_ARGC_SRC0C_ZXY 26
794 # define R300_FPI0_ARGC_SRC1C_ZXY 27
795 # define R300_FPI0_ARGC_SRC2C_ZXY 28
796 # define R300_FPI0_ARGC_SRC0CA_WZY 29
797 # define R300_FPI0_ARGC_SRC1CA_WZY 30
798 # define R300_FPI0_ARGC_SRC2CA_WZY 31
800 # define R300_FPI0_ARG0C_SHIFT 0
801 # define R300_FPI0_ARG0C_MASK (31 << 0)
802 # define R300_FPI0_ARG0C_NEG (1 << 5)
803 # define R300_FPI0_ARG0C_ABS (1 << 6)
804 # define R300_FPI0_ARG1C_SHIFT 7
805 # define R300_FPI0_ARG1C_MASK (31 << 7)
806 # define R300_FPI0_ARG1C_NEG (1 << 12)
807 # define R300_FPI0_ARG1C_ABS (1 << 13)
808 # define R300_FPI0_ARG2C_SHIFT 14
809 # define R300_FPI0_ARG2C_MASK (31 << 14)
810 # define R300_FPI0_ARG2C_NEG (1 << 19)
811 # define R300_FPI0_ARG2C_ABS (1 << 20)
812 # define R300_FPI0_SPECIAL_LRP (1 << 21)
813 # define R300_FPI0_OUTC_MAD (0 << 23)
814 # define R300_FPI0_OUTC_DP3 (1 << 23)
815 # define R300_FPI0_OUTC_DP4 (2 << 23)
816 # define R300_FPI0_OUTC_MIN (4 << 23)
817 # define R300_FPI0_OUTC_MAX (5 << 23)
818 # define R300_FPI0_OUTC_CMP (8 << 23)
819 # define R300_FPI0_OUTC_FRC (9 << 23)
820 # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)
821 # define R300_FPI0_OUTC_SAT (1 << 30)
822 # define R300_FPI0_UNKNOWN_31 (1 << 31)
824 #define R300_PFS_INSTR2_0 0x49C0
825 # define R300_FPI2_ARGA_SRC0C_X 0
826 # define R300_FPI2_ARGA_SRC0C_Y 1
827 # define R300_FPI2_ARGA_SRC0C_Z 2
828 # define R300_FPI2_ARGA_SRC1C_X 3
829 # define R300_FPI2_ARGA_SRC1C_Y 4
830 # define R300_FPI2_ARGA_SRC1C_Z 5
831 # define R300_FPI2_ARGA_SRC2C_X 6
832 # define R300_FPI2_ARGA_SRC2C_Y 7
833 # define R300_FPI2_ARGA_SRC2C_Z 8
834 # define R300_FPI2_ARGA_SRC0A 9
835 # define R300_FPI2_ARGA_SRC1A 10
836 # define R300_FPI2_ARGA_SRC2A 11
837 # define R300_FPI2_ARGA_SRC1A_LRP 15
838 # define R300_FPI2_ARGA_ZERO 16
839 # define R300_FPI2_ARGA_ONE 17
840 # define R300_FPI2_ARGA_HALF 18 /* GUESS */
842 # define R300_FPI2_ARG0A_SHIFT 0
843 # define R300_FPI2_ARG0A_MASK (31 << 0)
844 # define R300_FPI2_ARG0A_NEG (1 << 5)
845 # define R300_FPI2_ARG1A_SHIFT 7
846 # define R300_FPI2_ARG1A_MASK (31 << 7)
847 # define R300_FPI2_ARG1A_NEG (1 << 12)
848 # define R300_FPI2_ARG2A_SHIFT 14
849 # define R300_FPI2_AEG2A_MASK (31 << 14)
850 # define R300_FPI2_ARG2A_NEG (1 << 19)
851 # define R300_FPI2_SPECIAL_LRP (1 << 21)
852 # define R300_FPI2_OUTA_MAD (0 << 23)
853 # define R300_FPI2_OUTA_DP4 (1 << 23)
854 # define R300_RPI2_OUTA_MIN (2 << 23)
855 # define R300_RPI2_OUTA_MAX (3 << 23)
856 # define R300_FPI2_OUTA_CMP (6 << 23)
857 # define R300_FPI2_OUTA_FRC (7 << 23)
858 # define R300_FPI2_OUTA_EX2 (8 << 23)
859 # define R300_FPI2_OUTA_LG2 (9 << 23)
860 # define R300_FPI2_OUTA_RCP (10 << 23)
861 # define R300_FPI2_OUTA_RSQ (11 << 23)
862 # define R300_FPI2_OUTA_SAT (1 << 30)
863 # define R300_FPI2_UNKNOWN_31 (1 << 31)
867 #define R300_PP_ALPHA_TEST 0x4BD4
868 # define R300_REF_ALPHA_MASK 0x000000ff
869 # define R300_ALPHA_TEST_FAIL (0 << 8)
870 # define R300_ALPHA_TEST_LESS (1 << 8)
871 # define R300_ALPHA_TEST_LEQUAL (2 << 8)
872 # define R300_ALPHA_TEST_EQUAL (3 << 8)
873 # define R300_ALPHA_TEST_GEQUAL (4 << 8)
874 # define R300_ALPHA_TEST_GREATER (5 << 8)
875 # define R300_ALPHA_TEST_NEQUAL (6 << 8)
876 # define R300_ALPHA_TEST_PASS (7 << 8)
877 # define R300_ALPHA_TEST_OP_MASK (7 << 8)
878 # define R300_ALPHA_TEST_ENABLE (1 << 11)
881 /* Fragment program parameters in 7.16 floating point */
882 #define R300_PFS_PARAM_0_X 0x4C00
883 #define R300_PFS_PARAM_0_Y 0x4C04
884 #define R300_PFS_PARAM_0_Z 0x4C08
885 #define R300_PFS_PARAM_0_W 0x4C0C
886 /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */
887 #define R300_PFS_PARAM_31_X 0x4DF0
888 #define R300_PFS_PARAM_31_Y 0x4DF4
889 #define R300_PFS_PARAM_31_Z 0x4DF8
890 #define R300_PFS_PARAM_31_W 0x4DFC
893 // - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application
894 // - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same
895 // function (both registers are always set up completely in any case)
896 // - Most blend flags are simply copied from R200 and not tested yet */
897 #define R300_RB3D_CBLEND 0x4E04
898 #define R300_RB3D_ABLEND 0x4E08
899 /* the following only appear in CBLEND */
900 # define R300_BLEND_ENABLE (1 << 0)
901 # define R300_BLEND_UNKNOWN (3 << 1)
902 # define R300_BLEND_NO_SEPARATE (1 << 3)
903 /* the following are shared between CBLEND and ABLEND */
904 # define R300_FCN_MASK (3 << 12)
905 # define R300_COMB_FCN_ADD_CLAMP (0 << 12)
906 # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)
907 # define R300_COMB_FCN_SUB_CLAMP (2 << 12)
908 # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)
909 # define R300_SRC_BLEND_GL_ZERO (32 << 16)
910 # define R300_SRC_BLEND_GL_ONE (33 << 16)
911 # define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16)
912 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
913 # define R300_SRC_BLEND_GL_DST_COLOR (36 << 16)
914 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
915 # define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
916 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
917 # define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16)
918 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
919 # define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
920 # define R300_SRC_BLEND_MASK (63 << 16)
921 # define R300_DST_BLEND_GL_ZERO (32 << 24)
922 # define R300_DST_BLEND_GL_ONE (33 << 24)
923 # define R300_DST_BLEND_GL_SRC_COLOR (34 << 24)
924 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
925 # define R300_DST_BLEND_GL_DST_COLOR (36 << 24)
926 # define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
927 # define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24)
928 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
929 # define R300_DST_BLEND_GL_DST_ALPHA (40 << 24)
930 # define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
931 # define R300_DST_BLEND_MASK (63 << 24)
932 #define R300_RB3D_COLORMASK 0x4E0C
933 # define R300_COLORMASK0_B (1<<0)
934 # define R300_COLORMASK0_G (1<<1)
935 # define R300_COLORMASK0_R (1<<2)
936 # define R300_COLORMASK0_A (1<<3)
939 #define R300_RB3D_COLOROFFSET0 0x4E28
940 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */
941 #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */
942 #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */
943 #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */
945 /* Bit 16: Larger tiles
947 // Bit 18: Extremely weird tile like, but some pixels duplicated? */
948 #define R300_RB3D_COLORPITCH0 0x4E38
949 # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
950 # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
951 # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
952 # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
953 # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
954 # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
955 # define R300_COLOR_UNKNOWN_22_23 (3 << 22) /* GUESS: Format? */
956 #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */
957 #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
958 #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
961 /* Guess by Vladimir.
962 // Set to 0A before 3D operations, set to 02 afterwards. */
963 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C
964 # define R300_RB3D_DSTCACHE_02 0x00000002
965 # define R300_RB3D_DSTCACHE_0A 0x0000000A
968 /* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */
969 /* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */
970 #define R300_RB3D_ZCNTL_0 0x4F00
971 # define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */
972 # define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */
973 # define R300_RB3D_Z_TEST 0x00000012
974 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
975 # define R300_RB3D_Z_WRITE_ONLY 0x00000006
976 #define R300_RB3D_ZCNTL_1 0x4F04
977 # define R300_Z_TEST_NEVER (0 << 0) /* GUESS (based on R200) */
978 # define R300_Z_TEST_LESS (1 << 0)
979 # define R300_Z_TEST_LEQUAL (2 << 0)
980 # define R300_Z_TEST_EQUAL (3 << 0) /* GUESS */
981 # define R300_Z_TEST_GEQUAL (4 << 0) /* GUESS */
982 # define R300_Z_TEST_GREATER (5 << 0) /* GUESS */
983 # define R300_Z_TEST_NEQUAL (6 << 0)
984 # define R300_Z_TEST_ALWAYS (7 << 0)
985 # define R300_Z_TEST_MASK (7 << 0)
987 #define R300_RB3D_DEPTHOFFSET 0x4F20
988 #define R300_RB3D_DEPTHPITCH 0x4F24
989 # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
990 # define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */
991 # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */
992 # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */
993 # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */
994 # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */
996 /* BEGIN: Vertex program instruction set
997 // Every instruction is four dwords long:
998 // DWORD 0: output and opcode
999 // DWORD 1: first argument
1000 // DWORD 2: second argument
1001 // DWORD 3: third argument
1004 // - ABS r, a is implemented as MAX r, a, -a
1005 // - MOV is implemented as ADD to zero
1006 // - XPD is implemented as MUL + MAD
1007 // - FLR is implemented as FRC + ADD
1008 // - apparently, fglrx tries to schedule instructions so that there is at least
1009 // one instruction between the write to a temporary and the first read
1010 // from said temporary; however, violations of this scheduling are allowed
1011 // - register indices seem to be unrelated with OpenGL aliasing to conventional state
1012 // - only one attribute and one parameter can be loaded at a time; however, the
1013 // same attribute/parameter can be used for more than one argument
1014 // - the second software argument for POW is the third hardware argument (no idea why)
1015 // - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
1017 // There is some magic surrounding LIT:
1018 // The single argument is replicated across all three inputs, but swizzled:
1019 // First argument: xyzy
1020 // Second argument: xyzx
1021 // Third argument: xyzw
1022 // Whenever the result is used later in the fragment program, fglrx forces x and w
1023 // to be 1.0 in the input selection; I don't know whether this is strictly necessary */
1024 #define R300_VPI_OUT_OP_DOT (1 << 0)
1025 #define R300_VPI_OUT_OP_MUL (2 << 0)
1026 #define R300_VPI_OUT_OP_ADD (3 << 0)
1027 #define R300_VPI_OUT_OP_MAD (4 << 0)
1028 #define R300_VPI_OUT_OP_FRC (6 << 0)
1029 #define R300_VPI_OUT_OP_MAX (7 << 0)
1030 #define R300_VPI_OUT_OP_MIN (8 << 0)
1031 #define R300_VPI_OUT_OP_SGE (9 << 0)
1032 #define R300_VPI_OUT_OP_SLT (10 << 0)
1033 #define R300_VPI_OUT_OP_EXP (65 << 0)
1034 #define R300_VPI_OUT_OP_LOG (66 << 0)
1035 #define R300_VPI_OUT_OP_LIT (68 << 0)
1036 #define R300_VPI_OUT_OP_POW (69 << 0)
1037 #define R300_VPI_OUT_OP_RCP (70 << 0)
1038 #define R300_VPI_OUT_OP_RSQ (72 << 0)
1039 #define R300_VPI_OUT_OP_EX2 (75 << 0)
1040 #define R300_VPI_OUT_OP_LG2 (76 << 0)
1041 #define R300_VPI_OUT_OP_MAD_2 (128 << 0)
1043 #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)
1044 #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)
1045 #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)
1047 #define R300_VPI_OUT_REG_INDEX_SHIFT 13
1048 #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */
1050 #define R300_VPI_OUT_WRITE_X (1 << 20)
1051 #define R300_VPI_OUT_WRITE_Y (1 << 21)
1052 #define R300_VPI_OUT_WRITE_Z (1 << 22)
1053 #define R300_VPI_OUT_WRITE_W (1 << 23)
1055 #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0)
1056 #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)
1057 #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)
1058 #define R300_VPI_IN_REG_CLASS_NONE (9 << 0)
1059 #define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */
1061 #define R300_VPI_IN_REG_INDEX_SHIFT 5
1062 #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */
1064 /* The R300 can select components from the input register arbitrarily.
1065 // Use the following constants, shifted by the component shift you
1066 // want to select */
1067 #define R300_VPI_IN_SELECT_X 0
1068 #define R300_VPI_IN_SELECT_Y 1
1069 #define R300_VPI_IN_SELECT_Z 2
1070 #define R300_VPI_IN_SELECT_W 3
1071 #define R300_VPI_IN_SELECT_ZERO 4
1072 #define R300_VPI_IN_SELECT_ONE 5
1073 #define R300_VPI_IN_SELECT_MASK 7
1075 #define R300_VPI_IN_X_SHIFT 13
1076 #define R300_VPI_IN_Y_SHIFT 16
1077 #define R300_VPI_IN_Z_SHIFT 19
1078 #define R300_VPI_IN_W_SHIFT 22
1080 #define R300_VPI_IN_NEG_X (1 << 25)
1081 #define R300_VPI_IN_NEG_Y (1 << 26)
1082 #define R300_VPI_IN_NEG_Z (1 << 27)
1083 #define R300_VPI_IN_NEG_W (1 << 28)
1086 #endif /* _R300_REG_H */
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