2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
33 * Nicolai Haehnle <prefect_@gmx.net>
36 #ifndef __R300_CONTEXT_H__
37 #define __R300_CONTEXT_H__
39 #include "tnl/t_vertex.h"
41 #include "radeon_drm.h"
48 #include "radeon_context.h"
51 typedef struct r300_context r300ContextRec;
52 typedef struct r300_context *r300ContextPtr;
54 #include "radeon_lock.h"
57 /* Checkpoint.. for convenience */
58 #define CPT { fprintf(stderr, "%s:%s line %d\n", __FILE__, __FUNCTION__, __LINE__); }
59 #define WARN_ONCE(a) { \
60 static int warn##__LINE__=1; \
62 fprintf(stderr, "%s:%s line %d ***WARN_ONCE*** " a, \
63 __FILE__, __FUNCTION__, __LINE__); \
68 typedef GLuint uint32_t;
69 typedef GLubyte uint8_t;
71 /* We should probably change types within vertex_shader
72 and pixel_shader structure later on */
74 #include "vertex_shader.h"
75 #include "pixel_shader.h"
78 static __inline__ uint32_t r300PackFloat32(float fl)
80 union { float fl; uint32_t u; } u;
87 /************ DMA BUFFERS **************/
89 /* Need refcounting on dma buffers:
91 struct r300_dma_buffer {
92 int refcount; /* the number of retained regions in buf */
96 #define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \
97 (rvb)->address - rmesa->dma.buf0_address + \
100 /* A retained region, eg vertices for indexed vertices.
102 struct r300_dma_region {
103 struct r300_dma_buffer *buf;
104 char *address; /* == buf->address */
105 int start, end, ptr; /* offsets from start of buf */
112 /* Active dma region. Allocations for vertices and retained
113 * regions come from here. Also used for emitting random vertices,
114 * these may be flushed by calling flush_current();
116 struct r300_dma_region current;
118 void (*flush) (r300ContextPtr);
120 char *buf0_address; /* start of buf[0], for index calcs */
121 GLuint nr_released_bufs; /* flush after so many buffers released */
124 /* Texture related */
126 typedef struct r300_tex_obj r300TexObj, *r300TexObjPtr;
128 /* Texture object in locally shared texture space.
130 struct r300_tex_obj {
131 driTextureObject base;
133 GLuint bufAddr; /* Offset to start of locally
134 shared texture block */
136 GLuint dirty_state; /* Flags (1 per texunit) for
137 whether or not this texobj
138 has dirty hardware state
139 (pp_*) that needs to be
143 drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
144 /* Six, for the cube faces */
147 /* hardware register values */
148 /* Note that R200 has 8 registers per texture and R300 only 7 */
150 GLuint pitch; /* one of the unknown registers.. unknown 1 ?*/
151 GLuint size; /* npot only */
153 GLuint offset; /* Image location in texmem.
154 All cube faces follow. */
157 /* end hardware registers */
159 /* registers computed by r200 code - keep them here to
160 compare against what is actually written.
162 to be removed later.. */
163 GLuint pp_border_color;
164 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */
168 GLboolean border_fallback;
171 struct r300_texture_env_state {
172 r300TexObjPtr texobj;
177 #define R300_MAX_TEXTURE_UNITS 8
179 struct r300_texture_state {
180 struct r300_texture_env_state unit[R300_MAX_TEXTURE_UNITS];
181 int tc_count; /* number of incoming texture coordinates from VAP */
185 * A block of hardware state.
187 * When check returns non-zero, the returned number of dwords must be
188 * copied verbatim into the command buffer in order to update a state atom
191 struct r300_state_atom {
192 struct r300_state_atom *next, *prev;
193 const char* name; /* for debug */
194 int cmd_size; /* maximum size in dwords */
195 GLuint idx; /* index in an array (e.g. textures) */
199 int (*check)(r300ContextPtr, struct r300_state_atom* atom);
203 #define R300_VPT_CMD_0 0
204 #define R300_VPT_XSCALE 1
205 #define R300_VPT_XOFFSET 2
206 #define R300_VPT_YSCALE 3
207 #define R300_VPT_YOFFSET 4
208 #define R300_VPT_ZSCALE 5
209 #define R300_VPT_ZOFFSET 6
210 #define R300_VPT_CMDSIZE 7
212 #define R300_ZBS_CMD_0 0
213 #define R300_ZBS_FACTOR 1
214 #define R300_ZBS_CONSTANT 2
215 #define R300_ZBS_CMDSIZE 3
217 #define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
218 #define R300_VIR_CNTL_0 1
219 #define R300_VIR_CNTL_1 2
220 #define R300_VIR_CNTL_2 3
221 #define R300_VIR_CNTL_3 4
222 #define R300_VIR_CNTL_4 5
223 #define R300_VIR_CNTL_5 6
224 #define R300_VIR_CNTL_6 7
225 #define R300_VIR_CNTL_7 8
226 #define R300_VIR_CMDSIZE 9
228 #define R300_VIC_CMD_0 0
229 #define R300_VIC_CNTL_0 1
230 #define R300_VIC_CNTL_1 2
231 #define R300_VIC_CMDSIZE 3
233 #define R300_VOF_CMD_0 0
234 #define R300_VOF_CNTL_0 1
235 #define R300_VOF_CNTL_1 2
236 #define R300_VOF_CMDSIZE 3
239 #define R300_PVS_CMD_0 0
240 #define R300_PVS_CNTL_1 1
241 #define R300_PVS_CNTL_2 2
242 #define R300_PVS_CNTL_3 3
243 #define R300_PVS_CMDSIZE 4
245 #define R300_GB_MISC_CMD_0 0
246 #define R300_GB_MISC_MSPOS_0 1
247 #define R300_GB_MISC_MSPOS_1 2
248 #define R300_GB_MISC_TILE_CONFIG 3
249 #define R300_GB_MISC_SELECT 4
250 #define R300_GB_MISC_AA_CONFIG 5
251 #define R300_GB_MISC_CMDSIZE 6
253 #define R300_TXE_CMD_0 0
254 #define R300_TXE_ENABLE 1
255 #define R300_TXE_CMDSIZE 2
257 #define R300_PS_CMD_0 0
258 #define R300_PS_POINTSIZE 1
259 #define R300_PS_CMDSIZE 2
261 #define R300_CUL_CMD_0 0
262 #define R300_CUL_CULL 1
263 #define R300_CUL_CMDSIZE 2
265 #define R300_RC_CMD_0 0
266 #define R300_RC_CNTL_0 1
267 #define R300_RC_CNTL_1 2
268 #define R300_RC_CMDSIZE 3
270 #define R300_RI_CMD_0 0
271 #define R300_RI_INTERP_0 1
272 #define R300_RI_INTERP_1 2
273 #define R300_RI_INTERP_2 3
274 #define R300_RI_INTERP_3 4
275 #define R300_RI_INTERP_4 5
276 #define R300_RI_INTERP_5 6
277 #define R300_RI_INTERP_6 7
278 #define R300_RI_INTERP_7 8
279 #define R300_RI_CMDSIZE 9
281 #define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
282 #define R300_RR_ROUTE_0 1
283 #define R300_RR_ROUTE_1 2
284 #define R300_RR_ROUTE_2 3
285 #define R300_RR_ROUTE_3 4
286 #define R300_RR_ROUTE_4 5
287 #define R300_RR_ROUTE_5 6
288 #define R300_RR_ROUTE_6 7
289 #define R300_RR_ROUTE_7 8
290 #define R300_RR_CMDSIZE 9
292 #define R300_FP_CMD_0 0
293 #define R300_FP_CNTL0 1
294 #define R300_FP_CNTL1 2
295 #define R300_FP_CNTL2 3
296 #define R300_FP_CMD_1 4
297 #define R300_FP_NODE0 5
298 #define R300_FP_NODE1 6
299 #define R300_FP_NODE2 7
300 #define R300_FP_NODE3 8
301 #define R300_FP_CMDSIZE 9
303 #define R300_FPT_CMD_0 0
304 #define R300_FPT_INSTR_0 1
305 #define R300_FPT_CMDSIZE 65
307 #define R300_FPI_CMD_0 0
308 #define R300_FPI_INSTR_0 1
309 #define R300_FPI_CMDSIZE 65
311 #define R300_FPP_CMD_0 0
312 #define R300_FPP_PARAM_0 1
313 #define R300_FPP_CMDSIZE (32*4+1)
315 #define R300_AT_CMD_0 0
316 #define R300_AT_ALPHA_TEST 1
317 #define R300_AT_UNKNOWN 2
318 #define R300_AT_CMDSIZE 3
320 #define R300_BLD_CMD_0 0
321 #define R300_BLD_CBLEND 1
322 #define R300_BLD_ABLEND 2
323 #define R300_BLD_CMDSIZE 3
325 #define R300_CMK_CMD_0 0
326 #define R300_CMK_COLORMASK 1
327 #define R300_CMK_CMDSIZE 2
329 #define R300_CB_CMD_0 0
330 #define R300_CB_OFFSET 1
331 #define R300_CB_CMD_1 2
332 #define R300_CB_PITCH 3
333 #define R300_CB_CMDSIZE 4
335 #define R300_ZS_CMD_0 0
336 #define R300_ZS_CNTL_0 1
337 #define R300_ZS_CNTL_1 2
338 #define R300_ZS_CNTL_2 3
339 #define R300_ZS_CMDSIZE 4
341 #define R300_ZB_CMD_0 0
342 #define R300_ZB_OFFSET 1
343 #define R300_ZB_PITCH 2
344 #define R300_ZB_CMDSIZE 3
346 #define R300_VPI_CMD_0 0
347 #define R300_VPI_INSTR_0 1
348 #define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
350 #define R300_VPP_CMD_0 0
351 #define R300_VPP_PARAM_0 1
352 #define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
354 #define R300_VPS_CMD_0 0
355 #define R300_VPS_ZERO_0 1
356 #define R300_VPS_ZERO_1 2
357 #define R300_VPS_POINTSIZE 3
358 #define R300_VPS_ZERO_3 4
359 #define R300_VPS_CMDSIZE 5
361 /* the layout is common for all fields inside tex */
362 #define R300_TEX_CMD_0 0
363 #define R300_TEX_VALUE_0 1
364 /* We don't really use this, instead specify mtu+1 dynamically
365 #define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
369 * Cache for hardware register state.
371 struct r300_hw_state {
372 struct r300_state_atom atomlist;
376 int max_state_size; /* in dwords */
378 struct r300_state_atom vpt; /* viewport (1D98) */
379 struct r300_state_atom zbs; /* zbias (1DB0) */
380 struct r300_state_atom unk2080; /* (2080) */
381 struct r300_state_atom vof; /* VAP output format register 0x2090 */
382 struct r300_state_atom vte; /* (20B0) */
383 struct r300_state_atom unk2134; /* (2134) */
384 struct r300_state_atom unk2140; /* (2140) */
385 struct r300_state_atom vir[2]; /* vap input route (2150/21E0) */
386 struct r300_state_atom vic; /* vap input control (2180) */
387 struct r300_state_atom unk21DC; /* (21DC) */
388 struct r300_state_atom unk221C; /* (221C) */
389 struct r300_state_atom unk2220; /* (2220) */
390 struct r300_state_atom unk2288; /* (2288) */
391 struct r300_state_atom pvs; /* pvs_cntl (22D0) */
392 struct r300_state_atom gb_enable; /* (4008) */
393 struct r300_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
394 struct r300_state_atom unk4200; /* (4200) */
395 struct r300_state_atom unk4214; /* (4214) */
396 struct r300_state_atom ps; /* pointsize (421C) */
397 struct r300_state_atom unk4230; /* (4230) */
398 struct r300_state_atom unk4260; /* (4260) */
399 struct r300_state_atom unk4274; /* (4274) */
400 struct r300_state_atom unk4288; /* (4288) */
401 struct r300_state_atom unk42A0; /* (42A0) */
402 struct r300_state_atom unk42B4; /* (42B4) */
403 struct r300_state_atom cul; /* cull cntl (42B8) */
404 struct r300_state_atom unk42C0; /* (42C0) */
405 struct r300_state_atom rc; /* rs control (4300) */
406 struct r300_state_atom ri; /* rs interpolators (4310) */
407 struct r300_state_atom rr; /* rs route (4330) */
408 struct r300_state_atom unk43A4; /* (43A4) */
409 struct r300_state_atom unk43E8; /* (43E8) */
410 struct r300_state_atom fp; /* fragment program cntl + nodes (4600) */
411 struct r300_state_atom fpt; /* texi - (4620) */
412 struct r300_state_atom unk46A4; /* (46A4) */
413 struct r300_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
414 struct r300_state_atom unk4BC0; /* (4BC0) */
415 struct r300_state_atom unk4BC8; /* (4BC8) */
416 struct r300_state_atom at; /* alpha test (4BD4) */
417 struct r300_state_atom unk4BD8; /* (4BD8) */
418 struct r300_state_atom fpp; /* 0x4C00 and following */
419 struct r300_state_atom unk4E00; /* (4E00) */
420 struct r300_state_atom bld; /* blending (4E04) */
421 struct r300_state_atom cmk; /* colormask (4E0C) */
422 struct r300_state_atom unk4E10; /* (4E10) */
423 struct r300_state_atom cb; /* colorbuffer (4E28) */
424 struct r300_state_atom unk4E50; /* (4E50) */
425 struct r300_state_atom unk4E88; /* (4E88) */
426 struct r300_state_atom unk4EA0; /* (4E88) I saw it only written on RV350 hardware.. */
427 struct r300_state_atom zs; /* zstencil control (4F00) */
428 struct r300_state_atom unk4F10; /* (4F10) */
429 struct r300_state_atom zb; /* z buffer (4F20) */
430 struct r300_state_atom unk4F28; /* (4F28) */
431 struct r300_state_atom unk4F30; /* (4F30) */
432 struct r300_state_atom unk4F44; /* (4F44) */
433 struct r300_state_atom unk4F54; /* (4F54) */
435 struct r300_state_atom vpi; /* vp instructions */
436 struct r300_state_atom vpp; /* vp parameters */
437 struct r300_state_atom vps; /* vertex point size (?) */
439 /* 8 texture units */
440 /* the state is grouped by function and not by
441 texture unit. This makes single unit updates
442 really awkward - we are much better off
443 updating the whole thing at once */
445 struct r300_state_atom filter;
446 struct r300_state_atom unknown1;
447 struct r300_state_atom size;
448 struct r300_state_atom format;
449 struct r300_state_atom offset;
450 struct r300_state_atom unknown4;
451 struct r300_state_atom unknown5;
452 //struct r300_state_atom border_color;
454 struct r300_state_atom txe; /* tex enable (4104) */
459 * This structure holds the command buffer while it is being constructed.
461 * The first batch of commands in the buffer is always the state that needs
462 * to be re-emitted when the context is lost. This batch can be skipped
466 int size; /* DWORDs allocated for buffer */
468 int count_used; /* DWORDs filled so far */
469 int count_reemit; /* size of re-emission batch */
477 struct r300_depthbuffer_state {
481 struct r300_vap_reg_state {
482 /* input register assigments */
487 int i_tex[R300_MAX_TEXTURE_UNITS];
492 /* Vertex shader state */
494 /* 64 appears to be the maximum */
495 #define VSF_MAX_FRAGMENT_LENGTH 64
498 struct r300_vertex_shader_fragment {
501 GLuint d[VSF_MAX_FRAGMENT_LENGTH];
502 float f[VSF_MAX_FRAGMENT_LENGTH];
503 VERTEX_SHADER_INSTRUCTION i[VSF_MAX_FRAGMENT_LENGTH/4];
507 #define VSF_DEST_PROGRAM 0x0
508 #define VSF_DEST_MATRIX0 0x200
509 #define VSF_DEST_MATRIX1 0x204
510 #define VSF_DEST_MATRIX2 0x208
511 #define VSF_DEST_VECTOR0 0x20c
512 #define VSF_DEST_VECTOR1 0x20d
513 #define VSF_DEST_UNKNOWN1 0x400
514 #define VSF_DEST_UNKNOWN2 0x406
516 struct r300_vertex_shader_state {
517 struct r300_vertex_shader_fragment program;
519 /* a bit of a waste - each uses only a subset of allocated space..
520 but easier to program */
521 struct r300_vertex_shader_fragment matrix[3];
522 struct r300_vertex_shader_fragment vector[2];
524 struct r300_vertex_shader_fragment unknown1;
525 struct r300_vertex_shader_fragment unknown2;
528 int unknown_ptr1; /* pointer within program space */
534 int unknown_ptr2; /* pointer within program space */
535 int unknown_ptr3; /* pointer within program space */
538 /* r300_vertex_shader_state and r300_vertex_program should probably be merged together someday.
539 * Keeping them them seperate for now should ensure fixed pipeline keeps functioning properly.
541 struct r300_vertex_program {
542 struct vertex_program mesa_program; /* Must be first */
545 struct r300_vertex_shader_fragment program;
546 struct r300_vertex_shader_fragment params;
549 unsigned long num_temporaries; /* Number of temp vars used by program */
550 int inputs[VERT_ATTRIB_MAX];
553 /* 64 appears to be the maximum */
554 #define PSF_MAX_PROGRAM_LENGTH 64
556 struct r300_pixel_shader_program {
559 GLuint inst[PSF_MAX_PROGRAM_LENGTH];
562 /* ALU intructions (logic and integer) */
570 } inst[PSF_MAX_PROGRAM_LENGTH];
573 /* node information */
574 /* nodes are used to synchronize ALU and TEX streams */
575 /* There could be up to 4 nodes each consisting of
576 a number of TEX instructions followed by some ALU
578 /* the last node of a program should always be node3 */
586 int active_nodes; /* must be between 1 and 4, inclusive */
587 int first_node_has_tex; /* other nodes always have it */
589 int temp_register_count; /* magic value goes into PFS_CNTL_1 */
599 #define MAX_PIXEL_SHADER_PARAMS 32
600 struct r300_pixel_shader_state {
601 struct r300_pixel_shader_program program;
604 int param_length; /* to limit the number of unnecessary writes */
610 } param[MAX_PIXEL_SHADER_PARAMS];
613 /* 8 is somewhat bogus... it is probably something like 24 */
614 #define R300_MAX_AOS_ARRAYS 8
616 #define AOS_FORMAT_FLOAT 1
617 #define AOS_FORMAT_UBYTE 2
618 #define AOS_FORMAT_FLOAT_COLOR 3
624 struct r300_aos_rec {
626 int element_size; /* in dwords */
627 int stride; /* distance between elements, in dwords */
631 int ncomponents; /* number of components - between 1 and 4, inclusive */
633 int reg; /* which register they are assigned to. */
638 struct r300_depthbuffer_state depth;
639 struct r300_texture_state texture;
640 struct r300_vap_reg_state vap_reg;
641 struct r300_vertex_shader_state vertex_shader;
642 struct r300_pixel_shader_state pixel_shader;
643 struct r300_aos_rec aos[R300_MAX_AOS_ARRAYS];
651 * R300 context structure.
653 struct r300_context {
654 struct radeon_context radeon; /* parent class, must be first */
656 struct r300_hw_state hw;
657 struct r300_cmdbuf cmdbuf;
658 struct r300_state state;
663 GLboolean save_on_next_unlock;
665 /* Texture object bookkeeping
668 driTexHeap *texture_heaps[R200_NR_TEX_HEAPS];
669 driTextureObject swapped;
671 float initialMaxAnisotropy;
673 /* Clientdata textures;
675 GLuint prefer_gart_client_texturing;
679 GLmatrix TexGenMatrix[R300_MAX_TEXTURE_UNITS];
680 GLboolean recheck_texgen[R300_MAX_TEXTURE_UNITS];
681 GLboolean TexGenNeedNormals[R300_MAX_TEXTURE_UNITS];
682 GLuint TexMatEnabled;
683 GLuint TexMatCompSel;
684 GLuint TexGenEnabled;
686 GLuint TexGenCompSel;
689 struct r300_vertex_program *current_vp;
692 #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
694 extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv);
695 extern GLboolean r300CreateContext(const __GLcontextModes * glVisual,
696 __DRIcontextPrivate * driContextPriv,
697 void *sharedContextPrivate);
699 extern void r300InitVertexProgFuncs(struct dd_function_table *functions);
700 extern void r300VertexProgUpdateParams(GLcontext *ctx, struct r300_vertex_program *vp);
702 #endif /* __R300_CONTEXT_H__ */