src/mesa/drivers/dri/r300/r300_context.c

   1 /*
   2 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3
   4 The Weather Channel (TM) funded Tungsten Graphics to develop the
   5 initial release of the Radeon 8500 driver under the XFree86 license.
   6 This notice must be preserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /**
  31  * \file
  32  *
  33  * \author Keith Whitwell <keith@tungstengraphics.com>
  34  *
  35  * \author Nicolai Haehnle <prefect_@gmx.net>
  36  */
  37
  38 #include <stdbool.h>
  39 #include "main/glheader.h"
  40 #include "main/api_arrayelt.h"
  41 #include "main/context.h"
  42 #include "main/simple_list.h"
  43 #include "main/imports.h"
  44 #include "main/extensions.h"
  45 #include "main/bufferobj.h"
  46 #include "main/texobj.h"
  47 #include "main/mfeatures.h"
  48
  49 #include "swrast/swrast.h"
  50 #include "swrast_setup/swrast_setup.h"
  51 #include "vbo/vbo.h"
  52
  53 #include "tnl/tnl.h"
  54 #include "tnl/t_pipeline.h"
  55
  56 #include "drivers/common/driverfuncs.h"
  57 #include "drivers/common/meta.h"
  58
  59 #include "r300_context.h"
  60 #include "radeon_span.h"
  61 #include "r300_blit.h"
  62 #include "r300_cmdbuf.h"
  63 #include "r300_state.h"
  64 #include "r300_tex.h"
  65 #include "r300_emit.h"
  66 #include "r300_render.h"
  67 #include "r300_swtcl.h"
  68 #include "radeon_bocs_wrapper.h"
  69 #include "radeon_buffer_objects.h"
  70 #include "radeon_queryobj.h"
  71
  72 #include "utils.h"
  73 #include "xmlpool.h"            /* for symbolic values of enum-type options */
  74
  75
  76 static const struct tnl_pipeline_stage *r300_pipeline[] = {
  77         /* Catch any t&l fallbacks
  78          */
  79         &_tnl_vertex_transform_stage,
  80         &_tnl_normal_transform_stage,
  81         &_tnl_lighting_stage,
  82         &_tnl_fog_coordinate_stage,
  83         &_tnl_texgen_stage,
  84         &_tnl_texture_transform_stage,
  85         &_tnl_point_attenuation_stage,
  86         &_tnl_vertex_program_stage,
  87         &_tnl_render_stage,
  88         0,
  89 };
  90
  91 static void r300_get_lock(radeonContextPtr rmesa)
  92 {
  93         drm_radeon_sarea_t *sarea = rmesa->sarea;
  94
  95         if (sarea->ctx_owner != rmesa->dri.hwContext) {
  96                 sarea->ctx_owner = rmesa->dri.hwContext;
  97                 if (!rmesa->radeonScreen->kernel_mm)
  98                         radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
  99         }
 100 }
 101
 102 static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
 103 {
 104     /* please flush pipe do all pending work */
 105     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 106                                   R300_SC_SCREENDOOR, 1));
 107     radeon_cs_write_dword(cs, 0x0);
 108     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 109                                   R300_SC_SCREENDOOR, 1));
 110     radeon_cs_write_dword(cs, 0x00FFFFFF);
 111     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 112                                   R300_SC_HYPERZ, 1));
 113     radeon_cs_write_dword(cs, 0x0);
 114     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 115                                   R300_US_CONFIG, 1));
 116     radeon_cs_write_dword(cs, 0x0);
 117     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 118                                   R300_ZB_CNTL, 1));
 119     radeon_cs_write_dword(cs, 0x0);
 120     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
 121     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 122                                   R300_RB3D_DSTCACHE_CTLSTAT, 1));
 123     radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
 124     radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
 125                                   R300_ZB_ZCACHE_CTLSTAT, 1));
 126     radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
 127     radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
 128                                R300_WAIT_3D | R300_WAIT_3D_CLEAN));
 129 }
 130
 131 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 132 {
 133         BATCH_LOCALS(radeon);
 134
 135         cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
 136         BEGIN_BATCH_NO_AUTOSTATE(2);
 137         OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
 138         END_BATCH();
 139         end_3d(radeon);
 140 }
 141
 142 static void r300_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode)
 143 {
 144         r300ContextPtr r300 = R300_CONTEXT(ctx);
 145         if (mode)
 146                 r300->radeon.Fallback |= bit;
 147         else
 148                 r300->radeon.Fallback &= ~bit;
 149
 150         r300SwitchFallback(ctx, R300_FALLBACK_RADEON_COMMON, mode);
 151 }
 152
 153 static void r300_emit_query_finish(radeonContextPtr radeon)
 154 {
 155         r300ContextPtr r300 = (r300ContextPtr)radeon;
 156         struct radeon_query_object *query = radeon->query.current;
 157         BATCH_LOCALS(radeon);
 158
 159         BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
 160         switch (r300->radeon.radeonScreen->num_gb_pipes) {
 161         case 4:
 162                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 163                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 164                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 165         case 3:
 166                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
 167                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 168                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 169         case 2:
 170                 if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
 171                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
 172                 } else {
 173                         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
 174                 }
 175                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 176                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 177         case 1:
 178         default:
 179                 OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
 180                 OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 181                 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 182                 break;
 183         }
 184         OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
 185         END_BATCH();
 186         query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
 187         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 188         query->emitted_begin = GL_FALSE;
 189 }
 190
 191 static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
 192 {
 193         BATCH_LOCALS(radeon);
 194         struct radeon_query_object *query = radeon->query.current;
 195
 196         BEGIN_BATCH_NO_AUTOSTATE(8);
 197         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 198         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 199         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 200         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 201         END_BATCH();
 202
 203         query->curr_offset += sizeof(uint32_t);
 204         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 205         query->emitted_begin = GL_FALSE;
 206 }
 207
 208 static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
 209 {
 210         BATCH_LOCALS(radeon);
 211         struct radeon_query_object *query = radeon->query.current;
 212
 213         BEGIN_BATCH_NO_AUTOSTATE(14);
 214         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
 215         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 216         OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
 217         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
 218         OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
 219         OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
 220         OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
 221         END_BATCH();
 222
 223         query->curr_offset += 2 * sizeof(uint32_t);
 224         assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
 225         query->emitted_begin = GL_FALSE;
 226 }
 227
 228 static void r300_init_vtbl(radeonContextPtr radeon)
 229 {
 230         radeon->vtbl.get_lock = r300_get_lock;
 231         radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
 232         radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
 233         radeon->vtbl.swtcl_flush = r300_swtcl_flush;
 234         radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
 235         radeon->vtbl.fallback = r300_fallback;
 236         if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
 237                 if (radeon->radeonScreen->num_z_pipes == 2)
 238                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
 239                 else
 240                         radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
 241         } else
 242                 radeon->vtbl.emit_query_finish = r300_emit_query_finish;
 243
 244         radeon->vtbl.check_blit = r300_check_blit;
 245         radeon->vtbl.blit = r300_blit;
 246
 247         if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
 248                 radeon->vtbl.is_format_renderable = r500IsFormatRenderable;
 249         } else {
 250                 radeon->vtbl.is_format_renderable = r300IsFormatRenderable;
 251         }
 252 }
 253
 254 static void r300InitConstValues(struct gl_context *ctx, radeonScreenPtr screen)
 255 {
 256         r300ContextPtr r300 = R300_CONTEXT(ctx);
 257
 258         ctx->Const.MaxTextureImageUnits =
 259             driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
 260         ctx->Const.MaxTextureCoordUnits =
 261             driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
 262         ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
 263                  ctx->Const.MaxTextureCoordUnits);
 264         ctx->Const.MaxCombinedTextureImageUnits =
 265                 ctx->Const.MaxVertexTextureImageUnits +
 266                 ctx->Const.MaxTextureImageUnits;
 267
 268
 269         ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 270         ctx->Const.MaxTextureLodBias = 16.0;
 271
 272         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 273                 ctx->Const.MaxTextureLevels = 13;
 274                 ctx->Const.MaxCubeTextureLevels = 13;
 275                 ctx->Const.MaxTextureRectSize = 4096;
 276                 ctx->Const.MaxRenderbufferSize = 4096;
 277         }
 278         else {
 279                 ctx->Const.MaxTextureLevels = 12;
 280                 ctx->Const.MaxCubeTextureLevels = 12;
 281                 ctx->Const.MaxTextureRectSize = 2048;
 282                 ctx->Const.MaxRenderbufferSize = 2048;
 283         }
 284
 285         ctx->Const.MinPointSize = 1.0;
 286         ctx->Const.MinPointSizeAA = 1.0;
 287         ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
 288         ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
 289
 290         ctx->Const.MinLineWidth = 1.0;
 291         ctx->Const.MinLineWidthAA = 1.0;
 292         ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
 293         ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
 294
 295         ctx->Const.MaxDrawBuffers = 1;
 296         ctx->Const.MaxColorAttachments = 1;
 297
 298         if (r300->options.hw_tcl_enabled) {
 299                 ctx->Const.VertexProgram.MaxNativeInstructions = 255;
 300                 ctx->Const.VertexProgram.MaxNativeAluInstructions = 255;
 301                 ctx->Const.VertexProgram.MaxNativeAttribs = 16;
 302                 ctx->Const.VertexProgram.MaxNativeTemps = 32;
 303                 ctx->Const.VertexProgram.MaxNativeParameters = 256;
 304                 ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
 305         }
 306
 307         if (screen->chip_family >= CHIP_FAMILY_RV515) {
 308                 ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
 309                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 310
 311                 /* The hardware limits are higher than this,
 312                  * but the non-KMS DRM interface artificially limits us
 313                  * to this many instructions.
 314                  *
 315                  * We could of course work around it in the KMS path,
 316                  * but it would be a mess, so it seems wiser
 317                  * to leave it as is. Going forward, the Gallium driver
 318                  * will not be subject to these limitations.
 319                  */
 320                 ctx->Const.FragmentProgram.MaxNativeParameters = 255;
 321                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
 322                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
 323                 ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
 324                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
 325                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 326         } else {
 327                 ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
 328                 ctx->Const.FragmentProgram.MaxNativeAttribs = 11;       /* copy i915... */
 329                 ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
 330                 ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
 331                 ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
 332                 ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
 333                 ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
 334                 ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
 335         }
 336
 337 }
 338
 339 static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
 340 {
 341         struct r300_options options = { 0 };
 342
 343         driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
 344                             screen->driScreen->myNum, "r300");
 345
 346         r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
 347
 348         options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
 349         options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
 350         options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
 351
 352         if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
 353                 options.hw_tcl_enabled = 0;
 354         else
 355                 options.hw_tcl_enabled = 1;
 356
 357         options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
 358
 359         r300->options = options;
 360 }
 361
 362 static void r300InitGLExtensions(struct gl_context *ctx)
 363 {
 364         r300ContextPtr r300 = R300_CONTEXT(ctx);
 365
 366         ctx->Extensions.ARB_depth_texture = true;
 367         ctx->Extensions.ARB_fragment_program = true;
 368         ctx->Extensions.ARB_shadow = true;
 369         ctx->Extensions.ARB_shadow_ambient = true;
 370         ctx->Extensions.ARB_texture_border_clamp = true;
 371         ctx->Extensions.ARB_texture_cube_map = true;
 372         ctx->Extensions.ARB_texture_env_combine = true;
 373         ctx->Extensions.ARB_texture_env_crossbar = true;
 374         ctx->Extensions.ARB_texture_env_dot3 = true;
 375         ctx->Extensions.ARB_vertex_program = true;
 376         ctx->Extensions.EXT_blend_color = true;
 377         ctx->Extensions.EXT_blend_equation_separate = true;
 378         ctx->Extensions.EXT_blend_func_separate = true;
 379         ctx->Extensions.EXT_blend_minmax = true;
 380         ctx->Extensions.EXT_fog_coord = true;
 381         ctx->Extensions.EXT_gpu_program_parameters = true;
 382         ctx->Extensions.EXT_point_parameters = true;
 383         ctx->Extensions.EXT_provoking_vertex = true;
 384         ctx->Extensions.EXT_secondary_color = true;
 385         ctx->Extensions.EXT_shadow_funcs = true;
 386         ctx->Extensions.EXT_texture_env_dot3 = true;
 387         ctx->Extensions.EXT_texture_filter_anisotropic = true;
 388         ctx->Extensions.EXT_texture_mirror_clamp = true;
 389         ctx->Extensions.EXT_texture_sRGB = true;
 390         ctx->Extensions.EXT_vertex_array_bgra = true;
 391         ctx->Extensions.ATI_separate_stencil = true;
 392         ctx->Extensions.ATI_texture_env_combine3 = true;
 393         ctx->Extensions.ATI_texture_mirror_once = true;
 394         ctx->Extensions.MESA_pack_invert = true;
 395         ctx->Extensions.MESA_ycbcr_texture = true;
 396         ctx->Extensions.NV_blend_square = true;
 397         ctx->Extensions.NV_texture_rectangle = true;
 398         ctx->Extensions.NV_vertex_program = true;
 399 #if FEATURE_OES_EGL_image
 400         ctx->Extensions.OES_EGL_image = true;
 401 #endif
 402
 403         if (r300->radeon.radeonScreen->kernel_mm) {
 404                 ctx->Extensions.EXT_framebuffer_blit = true;
 405                 ctx->Extensions.EXT_framebuffer_object = true;
 406         }
 407
 408         ctx->Extensions.EXT_stencil_two_side =
 409            !r300->options.stencil_two_side_disabled;
 410
 411         if (r300->options.s3tc_force_disabled) {
 412                 ctx->Extensions.EXT_texture_compression_s3tc = false;
 413         } else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
 414                 ctx->Extensions.EXT_texture_compression_s3tc = true;
 415                 ctx->Extensions.S3_s3tc = true;
 416         }
 417
 418         ctx->Extensions.ARB_occlusion_query =
 419                 r300->radeon.radeonScreen->drmSupportsOcclusionQueries;
 420
 421         ctx->Extensions.ARB_half_float_vertex =
 422                 (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_R420);
 423
 424         ctx->Extensions.EXT_packed_depth_stencil =
 425                 (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
 426 }
 427
 428 static void r300InitIoctlFuncs(struct dd_function_table *functions)
 429 {
 430         functions->Clear = _mesa_meta_Clear;
 431         functions->Finish = radeonFinish;
 432         functions->Flush = radeonFlush;
 433 }
 434
 435 /* Create the device specific rendering context.
 436  */
 437 GLboolean r300CreateContext(gl_api api,
 438                             const struct gl_config * glVisual,
 439                             __DRIcontext * driContextPriv,
 440                             void *sharedContextPrivate)
 441 {
 442         __DRIscreen *sPriv = driContextPriv->driScreenPriv;
 443         radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
 444         struct dd_function_table functions;
 445         r300ContextPtr r300;
 446         struct gl_context *ctx;
 447
 448         assert(glVisual);
 449         assert(driContextPriv);
 450         assert(screen);
 451
 452         r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
 453         if (!r300)
 454                 return GL_FALSE;
 455
 456         r300ParseOptions(r300, screen);
 457
 458         r300->radeon.radeonScreen = screen;
 459         r300_init_vtbl(&r300->radeon);
 460
 461         _mesa_init_driver_functions(&functions);
 462         r300InitIoctlFuncs(&functions);
 463         r300InitStateFuncs(&r300->radeon, &functions);
 464         r300InitTextureFuncs(&r300->radeon, &functions);
 465         r300InitShaderFuncs(&functions);
 466         radeonInitQueryObjFunctions(&functions);
 467         radeonInitBufferObjectFuncs(&functions);
 468
 469         if (!radeonInitContext(&r300->radeon, &functions,
 470                                glVisual, driContextPriv,
 471                                sharedContextPrivate)) {
 472                 FREE(r300);
 473                 return GL_FALSE;
 474         }
 475
 476         ctx = r300->radeon.glCtx;
 477
 478         r300->fallback = 0;
 479         if (r300->options.hw_tcl_enabled)
 480                 ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
 481
 482         ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
 483
 484         r300InitConstValues(ctx, screen);
 485
 486         _mesa_set_mvp_with_dp4( ctx, GL_TRUE );
 487
 488         /* Initialize the software rasterizer and helper modules.
 489          */
 490         _swrast_CreateContext(ctx);
 491         _vbo_CreateContext(ctx);
 492         _tnl_CreateContext(ctx);
 493         _swsetup_CreateContext(ctx);
 494         _swsetup_Wakeup(ctx);
 495
 496         /* Install the customized pipeline:
 497          */
 498         _tnl_destroy_pipeline(ctx);
 499         _tnl_install_pipeline(ctx, r300_pipeline);
 500         TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
 501
 502         /* Configure swrast and TNL to match hardware characteristics:
 503          */
 504         _swrast_allow_pixel_fog(ctx, GL_FALSE);
 505         _swrast_allow_vertex_fog(ctx, GL_TRUE);
 506         _tnl_allow_pixel_fog(ctx, GL_FALSE);
 507         _tnl_allow_vertex_fog(ctx, GL_TRUE);
 508
 509         if (r300->options.hw_tcl_enabled) {
 510                 r300InitDraw(ctx);
 511         } else {
 512                 r300InitSwtcl(ctx);
 513         }
 514
 515         r300_blit_init(r300);
 516         radeon_fbo_init(&r300->radeon);
 517         radeonInitSpanFuncs( ctx );
 518         r300InitCmdBuf(r300);
 519         r300InitState(r300);
 520         r300InitShaderFunctions(r300);
 521
 522         r300InitGLExtensions(ctx);
 523
 524         return GL_TRUE;
 525 }
 526