src/mesa/drivers/dri/r200/r200_state_init.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */
   2 /*
   3 Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4
   5 The Weather Channel (TM) funded Tungsten Graphics to develop the
   6 initial release of the Radeon 8500 driver under the XFree86 license.
   7 This notice must be preserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28 */
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "glheader.h"
  36 #include "imports.h"
  37 #include "enums.h"
  38 #include "colormac.h"
  39 #include "api_arrayelt.h"
  40
  41 #include "swrast/swrast.h"
  42 #include "array_cache/acache.h"
  43 #include "tnl/tnl.h"
  44 #include "tnl/t_pipeline.h"
  45 #include "swrast_setup/swrast_setup.h"
  46
  47 #include "r200_context.h"
  48 #include "r200_ioctl.h"
  49 #include "r200_state.h"
  50 #include "r200_tcl.h"
  51 #include "r200_tex.h"
  52 #include "r200_swtcl.h"
  53 #include "r200_vtxfmt.h"
  54
  55 #include "xmlpool.h"
  56
  57 /* =============================================================
  58  * State initialization
  59  */
  60
  61 void r200PrintDirty( r200ContextPtr rmesa, const char *msg )
  62 {
  63    struct r200_state_atom *l;
  64
  65    fprintf(stderr, msg);
  66    fprintf(stderr, ": ");
  67
  68    foreach(l, &rmesa->hw.atomlist) {
  69       if (l->dirty || rmesa->hw.all_dirty)
  70          fprintf(stderr, "%s, ", l->name);
  71    }
  72
  73    fprintf(stderr, "\n");
  74 }
  75
  76 static int cmdpkt( int id )
  77 {
  78    drm_radeon_cmd_header_t h;
  79    h.i = 0;
  80    h.packet.cmd_type = RADEON_CMD_PACKET;
  81    h.packet.packet_id = id;
  82    return h.i;
  83 }
  84
  85 static int cmdvec( int offset, int stride, int count )
  86 {
  87    drm_radeon_cmd_header_t h;
  88    h.i = 0;
  89    h.vectors.cmd_type = RADEON_CMD_VECTORS;
  90    h.vectors.offset = offset;
  91    h.vectors.stride = stride;
  92    h.vectors.count = count;
  93    return h.i;
  94 }
  95
  96 static int cmdscl( int offset, int stride, int count )
  97 {
  98    drm_radeon_cmd_header_t h;
  99    h.i = 0;
 100    h.scalars.cmd_type = RADEON_CMD_SCALARS;
 101    h.scalars.offset = offset;
 102    h.scalars.stride = stride;
 103    h.scalars.count = count;
 104    return h.i;
 105 }
 106
 107 static int cmdscl2( int offset, int stride, int count )
 108 {
 109    drm_radeon_cmd_header_t h;
 110    h.i = 0;
 111    h.scalars.cmd_type = RADEON_CMD_SCALARS2;
 112    h.scalars.offset = offset - 0x100;
 113    h.scalars.stride = stride;
 114    h.scalars.count = count;
 115    return h.i;
 116 }
 117
 118 #define CHECK( NM, FLAG )                               \
 119 static GLboolean check_##NM( GLcontext *ctx, int idx )  \
 120 {                                                       \
 121    (void) idx;                                          \
 122    return FLAG;                                         \
 123 }
 124
 125 #define TCL_CHECK( NM, FLAG )                           \
 126 static GLboolean check_##NM( GLcontext *ctx, int idx )  \
 127 {                                                       \
 128    r200ContextPtr rmesa = R200_CONTEXT(ctx);            \
 129    (void) idx;                                          \
 130    return !rmesa->TclFallback && (FLAG);                \
 131 }
 132
 133
 134
 135 CHECK( always, GL_TRUE )
 136 CHECK( never, GL_FALSE )
 137 CHECK( tex_any, ctx->Texture._EnabledUnits )
 138 CHECK( tex_pair, (ctx->Texture.Unit[idx]._ReallyEnabled | ctx->Texture.Unit[idx & ~1]._ReallyEnabled))
 139 CHECK( tex, ctx->Texture.Unit[idx]._ReallyEnabled )
 140 CHECK( tex_cube, ctx->Texture.Unit[idx]._ReallyEnabled & TEXTURE_CUBE_BIT)
 141 CHECK( fog, ctx->Fog.Enabled )
 142 TCL_CHECK( tcl, GL_TRUE )
 143 TCL_CHECK( tcl_tex, ctx->Texture.Unit[idx]._ReallyEnabled )
 144 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
 145 TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[idx].Enabled )
 146 TCL_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << idx)) )
 147
 148
 149 /* Initialize the context's hardware state.
 150  */
 151 void r200InitState( r200ContextPtr rmesa )
 152 {
 153    GLcontext *ctx = rmesa->glCtx;
 154    GLuint color_fmt, depth_fmt, i;
 155
 156    switch ( rmesa->r200Screen->cpp ) {
 157    case 2:
 158       color_fmt = R200_COLOR_FORMAT_RGB565;
 159       break;
 160    case 4:
 161       color_fmt = R200_COLOR_FORMAT_ARGB8888;
 162       break;
 163    default:
 164       fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
 165       exit( -1 );
 166    }
 167
 168    rmesa->state.color.clear = 0x00000000;
 169
 170    switch ( ctx->Visual.depthBits ) {
 171    case 16:
 172       rmesa->state.depth.clear = 0x0000ffff;
 173       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
 174       depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z;
 175       rmesa->state.stencil.clear = 0x00000000;
 176       break;
 177    case 24:
 178       rmesa->state.depth.clear = 0x00ffffff;
 179       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
 180       depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z;
 181       rmesa->state.stencil.clear = 0xffff0000;
 182       break;
 183    default:
 184       fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
 185                ctx->Visual.depthBits );
 186       exit( -1 );
 187    }
 188
 189    /* Only have hw stencil when depth buffer is 24 bits deep */
 190    rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
 191                                      ctx->Visual.depthBits == 24 );
 192
 193    rmesa->Fallback = 0;
 194
 195    if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
 196       rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset;
 197       rmesa->state.color.drawPitch  = rmesa->r200Screen->backPitch;
 198    } else {
 199       rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset;
 200       rmesa->state.color.drawPitch  = rmesa->r200Screen->frontPitch;
 201    }
 202
 203    rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
 204    rmesa->state.pixel.readPitch  = rmesa->state.color.drawPitch;
 205
 206    rmesa->hw.max_state_size = 0;
 207
 208 #define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX )                           \
 209    do {                                                         \
 210       rmesa->hw.ATOM.cmd_size = SZ;                             \
 211       rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int));     \
 212       rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
 213       rmesa->hw.ATOM.name = NM;                                 \
 214       rmesa->hw.ATOM.idx = IDX;                                 \
 215       rmesa->hw.ATOM.check = check_##CHK;                       \
 216       rmesa->hw.ATOM.dirty = GL_FALSE;                          \
 217       rmesa->hw.max_state_size += SZ * sizeof(int);             \
 218    } while (0)
 219
 220
 221    /* Allocate state buffers:
 222     */
 223    if (rmesa->r200Screen->drmSupportsBlendColor)
 224       ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 );
 225    else
 226       ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 );
 227    ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
 228    ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
 229    ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
 230    ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
 231    ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 );
 232    ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 );
 233    ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 );
 234    ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
 235    ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 );
 236    ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
 237    ALLOC_STATE( tf, tex_any, TF_STATE_SIZE, "TF/tfactor", 0 );
 238    if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) {
 239    /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */
 240       ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE, "TEX/tex-0", 0 );
 241       ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE, "TEX/tex-1", 1 );
 242       ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 );
 243    }
 244    else {
 245       ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE, "TEX/tex-0", 0 );
 246       ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE, "TEX/tex-1", 1 );
 247       ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 );
 248    }
 249    ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE, "TEX/tex-2", 2 );
 250    ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE, "TEX/tex-3", 3 );
 251    ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE, "TEX/tex-4", 4 );
 252    ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE, "TEX/tex-5", 5 );
 253    if (rmesa->r200Screen->drmSupportsCubeMaps) {
 254       ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
 255       ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
 256       ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
 257       ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
 258       ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
 259       ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
 260    }
 261    else {
 262       ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 );
 263       ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 );
 264       ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 );
 265       ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 );
 266       ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 );
 267       ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 );
 268    }
 269
 270    ALLOC_STATE( tcl, tcl, TCL_STATE_SIZE, "TCL/tcl", 0 );
 271    ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 );
 272    ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 );
 273    ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 );
 274    ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 );
 275    ALLOC_STATE( grd, tcl, GRD_STATE_SIZE, "GRD/guard-band", 0 );
 276    ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 0 );
 277    ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 );
 278    ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 );
 279    ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 );
 280    ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 );
 281    ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 );
 282    ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 );
 283    ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 );
 284    ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 );
 285    ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 );
 286    ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 );
 287    ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 );
 288    ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 );
 289    ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
 290    ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 );
 291    ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 );
 292    ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 );
 293    ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 );
 294    ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 );
 295    ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 );
 296    ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 );
 297    ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 );
 298    ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 );
 299    ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 );
 300    ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 );
 301    ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 );
 302    ALLOC_STATE( pix[0], always, PIX_STATE_SIZE, "PIX/pixstage-0", 0 );
 303    ALLOC_STATE( pix[1], tex, PIX_STATE_SIZE, "PIX/pixstage-1", 1 );
 304    ALLOC_STATE( pix[2], tex, PIX_STATE_SIZE, "PIX/pixstage-2", 2 );
 305    ALLOC_STATE( pix[3], tex, PIX_STATE_SIZE, "PIX/pixstage-3", 3 );
 306    ALLOC_STATE( pix[4], tex, PIX_STATE_SIZE, "PIX/pixstage-4", 4 );
 307    ALLOC_STATE( pix[5], tex, PIX_STATE_SIZE, "PIX/pixstage-5", 5 );
 308
 309    r200SetUpAtomList( rmesa );
 310
 311    /* Fill in the packet headers:
 312     */
 313    rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
 314    rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
 315    rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
 316    if (rmesa->r200Screen->drmSupportsBlendColor)
 317       rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR);
 318    rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
 319    rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
 320    rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
 321    rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
 322    rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
 323    rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
 324    rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(R200_EMIT_PP_CNTL_X);
 325    rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET);
 326    rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL);
 327    rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0);
 328    rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS);
 329    rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(R200_EMIT_RE_POINTSIZE);
 330    rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0);
 331    rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3);
 332    rmesa->hw.tf.cmd[TF_CMD_0]   = cmdpkt(R200_EMIT_TFACTOR_0);
 333    rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_0);
 334    rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_0);
 335    rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_1);
 336    rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_1);
 337    rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_2);
 338    rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_2);
 339    rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_3);
 340    rmesa->hw.tex[3].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_3);
 341    rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_4);
 342    rmesa->hw.tex[4].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_4);
 343    rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_5);
 344    rmesa->hw.tex[5].cmd[TEX_CMD_1] = cmdpkt(R200_EMIT_PP_TXOFFSET_5);
 345    rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0);
 346    rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0);
 347    rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1);
 348    rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1);
 349    rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2);
 350    rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2);
 351    rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3);
 352    rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3);
 353    rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4);
 354    rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4);
 355    rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5);
 356    rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5);
 357    rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_0);
 358    rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_1);
 359    rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_2);
 360    rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_3);
 361    rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_4);
 362    rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_5);
 363    rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
 364    rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0);
 365    rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL);
 366    rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2);
 367    rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(R200_EMIT_MATRIX_SELECT_0);
 368    rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(R200_EMIT_VAP_CTL);
 369    rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(R200_EMIT_VTX_FMT_0);
 370    rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL);
 371    rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL);
 372    rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(R200_EMIT_VTE_CNTL);
 373    rmesa->hw.mtl[0].cmd[MTL_CMD_0] =
 374       cmdvec( R200_VS_MAT_0_EMISS, 1, 16 );
 375    rmesa->hw.mtl[0].cmd[MTL_CMD_1] =
 376       cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 );
 377    rmesa->hw.mtl[1].cmd[MTL_CMD_0] =
 378       cmdvec( R200_VS_MAT_1_EMISS, 1, 16 );
 379    rmesa->hw.mtl[1].cmd[MTL_CMD_1] =
 380       cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 );
 381
 382    rmesa->hw.grd.cmd[GRD_CMD_0] =
 383       cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
 384    rmesa->hw.fog.cmd[FOG_CMD_0] =
 385       cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 );
 386    rmesa->hw.glt.cmd[GLT_CMD_0] =
 387       cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
 388    rmesa->hw.eye.cmd[EYE_CMD_0] =
 389       cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 );
 390
 391    rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] =
 392       cmdvec( R200_VS_MATRIX_0_MV, 1, 16);
 393    rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] =
 394       cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16);
 395    rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] =
 396       cmdvec( R200_VS_MATRIX_2_MVP, 1, 16);
 397    rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] =
 398       cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16);
 399    rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] =
 400       cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16);
 401    rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] =
 402       cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16);
 403    rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] =
 404       cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16);
 405    rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] =
 406       cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16);
 407    rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] =
 408       cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16);
 409
 410    for (i = 0 ; i < 8; i++) {
 411       rmesa->hw.lit[i].cmd[LIT_CMD_0] =
 412          cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
 413       rmesa->hw.lit[i].cmd[LIT_CMD_1] =
 414          cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 );
 415    }
 416
 417    for (i = 0 ; i < 6; i++) {
 418       rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
 419          cmdvec( R200_VS_UCP_ADDR + i, 1, 4 );
 420    }
 421
 422    /* Initial Harware state:
 423     */
 424    rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS
 425                                      /* | R200_RIGHT_HAND_CUBE_OGL*/);
 426
 427    rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX |
 428                                           R200_FOG_USE_SPEC_ALPHA);
 429
 430    rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
 431
 432    rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
 433                                 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
 434                                 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
 435
 436    if (rmesa->r200Screen->drmSupportsBlendColor) {
 437       rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000;
 438       rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
 439                                 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
 440                                 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
 441       rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP |
 442                                 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) |
 443                                 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT));
 444    }
 445
 446    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
 447       rmesa->r200Screen->depthOffset + rmesa->r200Screen->fbLocation;
 448
 449    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
 450       ((rmesa->r200Screen->depthPitch &
 451         R200_DEPTHPITCH_MASK) |
 452        R200_DEPTH_ENDIAN_NO_SWAP);
 453
 454    if (rmesa->using_hyperz)
 455       rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ;
 456
 457    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
 458                                                R200_Z_TEST_LESS |
 459                                                R200_STENCIL_TEST_ALWAYS |
 460                                                R200_STENCIL_FAIL_KEEP |
 461                                                R200_STENCIL_ZPASS_KEEP |
 462                                                R200_STENCIL_ZFAIL_KEEP |
 463                                                R200_Z_WRITE_ENABLE);
 464
 465    if (rmesa->using_hyperz) {
 466       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE |
 467                                                   R200_Z_DECOMPRESSION_ENABLE;
 468 /*      if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200)
 469          rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
 470    }
 471
 472    rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
 473                                      | R200_TEX_BLEND_0_ENABLE);
 474
 475    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt;
 476    switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
 477    case DRI_CONF_DITHER_XERRORDIFFRESET:
 478       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT;
 479       break;
 480    case DRI_CONF_DITHER_ORDERED:
 481       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE;
 482       break;
 483    }
 484    if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
 485         DRI_CONF_ROUND_ROUND )
 486       rmesa->state.color.roundEnable = R200_ROUND_ENABLE;
 487    else
 488       rmesa->state.color.roundEnable = 0;
 489    if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
 490         DRI_CONF_COLOR_REDUCTION_DITHER )
 491       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE;
 492    else
 493       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
 494
 495    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
 496                                                rmesa->r200Screen->fbLocation)
 497                                               & R200_COLOROFFSET_MASK);
 498
 499    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
 500                                               R200_COLORPITCH_MASK) |
 501                                              R200_COLOR_ENDIAN_NO_SWAP);
 502
 503    rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW |
 504                                      R200_BFACE_SOLID |
 505                                      R200_FFACE_SOLID |
 506                                      R200_FLAT_SHADE_VTX_LAST |
 507                                      R200_DIFFUSE_SHADE_GOURAUD |
 508                                      R200_ALPHA_SHADE_GOURAUD |
 509                                      R200_SPECULAR_SHADE_GOURAUD |
 510                                      R200_FOG_SHADE_GOURAUD |
 511                                      R200_VTX_PIX_CENTER_OGL |
 512                                      R200_ROUND_MODE_TRUNC |
 513                                      R200_ROUND_PREC_8TH_PIX);
 514
 515    rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE |
 516                                      R200_SCISSOR_ENABLE);
 517
 518    rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
 519
 520    rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
 521       ((0 << R200_LINE_CURRENT_PTR_SHIFT) |
 522        (1 << R200_LINE_CURRENT_COUNT_SHIFT));
 523
 524    rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
 525
 526    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
 527       ((0x00 << R200_STENCIL_REF_SHIFT) |
 528        (0xff << R200_STENCIL_MASK_SHIFT) |
 529        (0xff << R200_STENCIL_WRITEMASK_SHIFT));
 530
 531    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY;
 532    rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
 533
 534    rmesa->hw.tam.cmd[TAM_DEBUG3] = 0;
 535
 536    rmesa->hw.msc.cmd[MSC_RE_MISC] =
 537       ((0 << R200_STIPPLE_X_OFFSET_SHIFT) |
 538        (0 << R200_STIPPLE_Y_OFFSET_SHIFT) |
 539        R200_STIPPLE_BIG_BIT_ORDER);
 540
 541
 542    rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
 543    rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0;
 544    rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0;
 545    rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0;
 546    rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0;
 547    rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] =
 548 #ifdef MESA_BIG_ENDIAN
 549                                                 R200_VC_32BIT_SWAP;
 550 #else
 551                                                 R200_VC_NO_SWAP;
 552 #endif
 553
 554    if (!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) {
 555       /* Bypass TCL */
 556       rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
 557    }
 558
 559    rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = 0x100010;
 560    rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
 561       (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
 562    rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] =
 563       (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) |
 564       (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT);
 565    rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] =
 566       (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) |
 567       (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) |
 568       (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) |
 569       (0x09 << R200_VTX_TEX_3_ADDR__SHIFT);
 570    rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] =
 571       (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) |
 572       (0x0B << R200_VTX_TEX_5_ADDR__SHIFT);
 573
 574
 575    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE]  = 0x00000000;
 576    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
 577    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE]  = 0x00000000;
 578    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
 579    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE]  = 0x00000000;
 580    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
 581
 582    for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
 583       rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL;
 584       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
 585          ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) |  /* <-- note i */
 586           (2 << R200_TXFORMAT_WIDTH_SHIFT) |
 587           (2 << R200_TXFORMAT_HEIGHT_SHIFT));
 588       rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
 589           rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
 590       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
 591       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] =
 592          (/* R200_TEXCOORD_PROJ | */
 593           0x100000);    /* Small default bias */
 594
 595       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
 596       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] =
 597          rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
 598       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] =
 599          rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
 600       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] =
 601          rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
 602       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] =
 603          rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
 604       rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] =
 605          rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP];
 606
 607       rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] =
 608          (R200_TXC_ARG_A_ZERO |
 609           R200_TXC_ARG_B_ZERO |
 610           R200_TXC_ARG_C_DIFFUSE_COLOR |
 611           R200_TXC_OP_MADD);
 612
 613       rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] =
 614          ((i << R200_TXC_TFACTOR_SEL_SHIFT) |
 615           R200_TXC_SCALE_1X |
 616           R200_TXC_CLAMP_0_1 |
 617           R200_TXC_OUTPUT_REG_R0);
 618
 619       rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] =
 620          (R200_TXA_ARG_A_ZERO |
 621           R200_TXA_ARG_B_ZERO |
 622           R200_TXA_ARG_C_DIFFUSE_ALPHA |
 623           R200_TXA_OP_MADD);
 624
 625       rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] =
 626          ((i << R200_TXA_TFACTOR_SEL_SHIFT) |
 627           R200_TXA_SCALE_1X |
 628           R200_TXA_CLAMP_0_1 |
 629           R200_TXA_OUTPUT_REG_R0);
 630    }
 631
 632    rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0;
 633    rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0;
 634    rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0;
 635    rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0;
 636    rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0;
 637    rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0;
 638
 639    rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] =
 640       (R200_VAP_TCL_ENABLE |
 641        (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT));
 642
 643    rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] =
 644       (R200_VPORT_X_SCALE_ENA |
 645        R200_VPORT_Y_SCALE_ENA |
 646        R200_VPORT_Z_SCALE_ENA |
 647        R200_VPORT_X_OFFSET_ENA |
 648        R200_VPORT_Y_OFFSET_ENA |
 649        R200_VPORT_Z_OFFSET_ENA |
 650 /* FIXME: Turn on for tex rect only */
 651        R200_VTX_ST_DENORMALIZED |
 652        R200_VTX_W0_FMT);
 653
 654
 655    rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0;
 656    rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0;
 657    rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] =
 658       ((R200_VTX_Z0 | R200_VTX_W0 |
 659        (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)));
 660    rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0;
 661    rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW);
 662    rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE;
 663
 664
 665    /* Matrix selection */
 666    rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] =
 667       (R200_MTX_MV << R200_MODELVIEW_0_SHIFT);
 668
 669    rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] =
 670        (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT);
 671
 672    rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] =
 673       (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT);
 674
 675    rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] =
 676       ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) |
 677        (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) |
 678        (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) |
 679        (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT));
 680
 681    rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] =
 682       ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) |
 683        (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT));
 684
 685
 686    /* General TCL state */
 687    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] =
 688       (R200_SPECULAR_LIGHTS |
 689        R200_DIFFUSE_SPECULAR_COMBINE |
 690        R200_LOCAL_LIGHT_VEC_GL |
 691        R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT |
 692        R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT);
 693
 694    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] =
 695       ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) |
 696        (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) |
 697        (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) |
 698        (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) |
 699        (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) |
 700        (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) |
 701        (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) |
 702        (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT));
 703
 704    rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */
 705    rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0;
 706    rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0;
 707    rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0;
 708
 709    rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
 710       (R200_UCP_IN_CLIP_SPACE |
 711        R200_CULL_FRONT_IS_CCW);
 712
 713    /* Texgen/Texmat state */
 714    rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff;
 715    rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] =
 716       ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) |
 717        (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) |
 718        (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) |
 719        (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) |
 720        (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) |
 721        (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT));
 722    rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0;
 723    rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] =
 724       ((0 << R200_TEXGEN_0_INPUT_SHIFT) |
 725        (1 << R200_TEXGEN_1_INPUT_SHIFT) |
 726        (2 << R200_TEXGEN_2_INPUT_SHIFT) |
 727        (3 << R200_TEXGEN_3_INPUT_SHIFT) |
 728        (4 << R200_TEXGEN_4_INPUT_SHIFT) |
 729        (5 << R200_TEXGEN_5_INPUT_SHIFT));
 730    rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0;
 731
 732
 733    for (i = 0 ; i < 8; i++) {
 734       struct gl_light *l = &ctx->Light.Light[i];
 735       GLenum p = GL_LIGHT0 + i;
 736       *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
 737
 738       ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
 739       ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
 740       ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
 741       ctx->Driver.Lightfv( ctx, p, GL_POSITION, 0 );
 742       ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, 0 );
 743       ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
 744       ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
 745       ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
 746                            &l->ConstantAttenuation );
 747       ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
 748                            &l->LinearAttenuation );
 749       ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
 750                            &l->QuadraticAttenuation );
 751       *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
 752    }
 753
 754    ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
 755                              ctx->Light.Model.Ambient );
 756
 757    TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
 758
 759    for (i = 0 ; i < 6; i++) {
 760       ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
 761    }
 762
 763    ctx->Driver.Fogfv( ctx, GL_FOG_MODE, 0 );
 764    ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
 765    ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
 766    ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
 767    ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
 768    ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, 0 );
 769
 770    rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
 771    rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
 772    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
 773    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
 774
 775    rmesa->hw.eye.cmd[EYE_X] = 0;
 776    rmesa->hw.eye.cmd[EYE_Y] = 0;
 777    rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
 778    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
 779
 780    r200LightingSpaceChange( ctx );
 781
 782    rmesa->hw.all_dirty = GL_TRUE;
 783 }