1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_context.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_regions.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_mipmap_tree.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLIT
45 static GLuint translate_raster_op(GLenum logicop)
48 case GL_CLEAR: return 0x00;
49 case GL_AND: return 0x88;
50 case GL_AND_REVERSE: return 0x44;
51 case GL_COPY: return 0xCC;
52 case GL_AND_INVERTED: return 0x22;
53 case GL_NOOP: return 0xAA;
54 case GL_XOR: return 0x66;
55 case GL_OR: return 0xEE;
56 case GL_NOR: return 0x11;
57 case GL_EQUIV: return 0x99;
58 case GL_INVERT: return 0x55;
59 case GL_OR_REVERSE: return 0xDD;
60 case GL_COPY_INVERTED: return 0x33;
61 case GL_OR_INVERTED: return 0xBB;
62 case GL_NAND: return 0x77;
63 case GL_SET: return 0xFF;
90 intelEmitCopyBlit(struct intel_context *intel,
93 drm_intel_bo *src_buffer,
97 drm_intel_bo *dst_buffer,
100 GLshort src_x, GLshort src_y,
101 GLshort dst_x, GLshort dst_y,
102 GLshort w, GLshort h,
105 GLuint CMD, BR13, pass = 0;
106 int dst_y2 = dst_y + h;
107 int dst_x2 = dst_x + w;
108 drm_intel_bo *aper_array[3];
111 if (dst_tiling != I915_TILING_NONE) {
112 if (dst_offset & 4095)
114 if (dst_tiling == I915_TILING_Y)
117 if (src_tiling != I915_TILING_NONE) {
118 if (src_offset & 4095)
120 if (src_tiling == I915_TILING_Y)
124 /* do space check before going any further */
126 aper_array[0] = intel->batch.bo;
127 aper_array[1] = dst_buffer;
128 aper_array[2] = src_buffer;
130 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
131 intel_batchbuffer_flush(intel);
140 intel_batchbuffer_require_space(intel, 8 * 4, true);
141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
143 src_buffer, src_pitch, src_offset, src_x, src_y,
144 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
149 /* For big formats (such as floating point), do the copy using 32bpp and
150 * multiply the coordinates.
153 assert(cpp % 4 == 0);
160 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
165 CMD = XY_SRC_COPY_BLT_CMD;
168 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
175 if (dst_tiling != I915_TILING_NONE) {
179 if (src_tiling != I915_TILING_NONE) {
185 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
189 assert(dst_x < dst_x2);
190 assert(dst_y < dst_y2);
194 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
195 OUT_BATCH((dst_y << 16) | dst_x);
196 OUT_BATCH((dst_y2 << 16) | dst_x2);
197 OUT_RELOC_FENCED(dst_buffer,
198 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
200 OUT_BATCH((src_y << 16) | src_x);
201 OUT_BATCH((uint16_t)src_pitch);
202 OUT_RELOC_FENCED(src_buffer,
203 I915_GEM_DOMAIN_RENDER, 0,
207 intel_batchbuffer_emit_mi_flush(intel);
214 * Use blitting to clear the renderbuffers named by 'flags'.
215 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
216 * since that might include software renderbuffers or renderbuffers
217 * which we're clearing with triangles.
218 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
221 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
223 struct intel_context *intel = intel_context(ctx);
224 struct gl_framebuffer *fb = ctx->DrawBuffer;
225 GLuint clear_depth_value, clear_depth_mask;
227 GLint cx, cy, cw, ch;
228 GLbitfield fail_mask = 0;
232 * Compute values for clearing the buffers.
234 clear_depth_value = 0;
235 clear_depth_mask = 0;
236 if (mask & BUFFER_BIT_DEPTH) {
237 clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
238 clear_depth_mask = XY_BLT_WRITE_RGB;
240 if (mask & BUFFER_BIT_STENCIL) {
241 clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24;
242 clear_depth_mask |= XY_BLT_WRITE_ALPHA;
247 cy = ctx->DrawBuffer->Height - fb->_Ymax;
250 cw = fb->_Xmax - fb->_Xmin;
251 ch = fb->_Ymax - fb->_Ymin;
253 if (cw == 0 || ch == 0)
256 all = (cw == fb->Width && ch == fb->Height);
258 /* Loop over all renderbuffers */
259 mask &= (1 << BUFFER_COUNT) - 1;
261 GLuint buf = _mesa_ffs(mask) - 1;
262 GLboolean is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL;
263 struct intel_renderbuffer *irb;
264 drm_intel_bo *write_buffer;
269 drm_intel_bo *aper_array[2];
273 irb = intel_get_renderbuffer(fb, buf);
274 if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) {
275 fail_mask |= 1 << buf;
279 /* OK, clear this renderbuffer */
280 write_buffer = intel_region_buffer(intel, irb->region,
281 all ? INTEL_WRITE_FULL :
283 x1 = cx + irb->draw_x;
284 y1 = cy + irb->draw_y;
285 x2 = cx + cw + irb->draw_x;
286 y2 = cy + ch + irb->draw_y;
288 pitch = irb->region->pitch;
289 cpp = irb->region->cpp;
291 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
293 irb->region->buffer, (pitch * cpp),
294 x1, y1, x2 - x1, y2 - y1);
297 CMD = XY_COLOR_BLT_CMD;
299 /* Setup the blit command */
301 if (is_depth_stencil) {
302 CMD |= clear_depth_mask;
305 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
309 assert(irb->region->tiling != I915_TILING_Y);
312 if (irb->region->tiling != I915_TILING_NONE) {
317 BR13 |= (pitch * cpp);
319 if (is_depth_stencil) {
320 clear_val = clear_depth_value;
323 GLclampf *color = ctx->Color.ClearColor;
325 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
326 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
327 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
328 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
330 switch (irb->Base.Format) {
331 case MESA_FORMAT_ARGB8888:
332 case MESA_FORMAT_XRGB8888:
333 clear_val = PACK_COLOR_8888(clear[3], clear[0],
336 case MESA_FORMAT_RGB565:
337 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
339 case MESA_FORMAT_ARGB4444:
340 clear_val = PACK_COLOR_4444(clear[3], clear[0],
343 case MESA_FORMAT_ARGB1555:
344 clear_val = PACK_COLOR_1555(clear[3], clear[0],
348 clear_val = PACK_COLOR_8888(clear[3], clear[3],
352 fail_mask |= 1 << buf;
357 BR13 |= br13_for_cpp(cpp);
362 /* do space check before going any further */
363 aper_array[0] = intel->batch.bo;
364 aper_array[1] = write_buffer;
366 if (drm_intel_bufmgr_check_aperture_space(aper_array,
367 ARRAY_SIZE(aper_array)) != 0) {
368 intel_batchbuffer_flush(intel);
374 OUT_BATCH((y1 << 16) | x1);
375 OUT_BATCH((y2 << 16) | x2);
376 OUT_RELOC_FENCED(write_buffer,
377 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
379 OUT_BATCH(clear_val);
382 if (intel->always_flush_cache)
383 intel_batchbuffer_emit_mi_flush(intel);
385 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
386 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
393 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
395 GLubyte *src_bits, GLuint src_size,
398 drm_intel_bo *dst_buffer,
401 GLshort x, GLshort y,
402 GLshort w, GLshort h,
405 int dwords = ALIGN(src_size, 8) / 4;
406 uint32_t opcode, br13, blit_cmd;
408 if (dst_tiling != I915_TILING_NONE) {
409 if (dst_offset & 4095)
411 if (dst_tiling == I915_TILING_Y)
415 assert( logic_op - GL_CLEAR >= 0 );
416 assert( logic_op - GL_CLEAR < 0x10 );
417 assert(dst_pitch > 0);
424 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
426 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
428 intel_batchbuffer_require_space(intel,
433 opcode = XY_SETUP_BLT_CMD;
435 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
437 if (dst_tiling != I915_TILING_NONE) {
438 opcode |= XY_DST_TILED;
443 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
444 br13 |= br13_for_cpp(cpp);
446 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
447 if (dst_tiling != I915_TILING_NONE)
448 blit_cmd |= XY_DST_TILED;
450 BEGIN_BATCH_BLT(8 + 3);
453 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
454 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
455 OUT_RELOC_FENCED(dst_buffer,
456 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
458 OUT_BATCH(0); /* bg */
459 OUT_BATCH(fg_color); /* fg */
460 OUT_BATCH(0); /* pattern base addr */
462 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
463 OUT_BATCH((y << 16) | x);
464 OUT_BATCH(((y + h) << 16) | (x + w));
467 intel_batchbuffer_data(intel, src_bits, dwords * 4, true);
469 intel_batchbuffer_emit_mi_flush(intel);
474 /* We don't have a memmove-type blit like some other hardware, so we'll do a
475 * rectangular blit covering a large space, then emit 1-scanline blit at the
476 * end to cover the last if we need.
479 intel_emit_linear_blit(struct intel_context *intel,
480 drm_intel_bo *dst_bo,
481 unsigned int dst_offset,
482 drm_intel_bo *src_bo,
483 unsigned int src_offset,
486 GLuint pitch, height;
489 /* The pitch given to the GPU must be DWORD aligned, and
490 * we want width to match pitch. Max width is (1 << 15 - 1),
491 * rounding that down to the nearest DWORD is 1 << 15 - 4
493 pitch = MIN2(size, (1 << 15) - 4);
494 height = size / pitch;
495 ok = intelEmitCopyBlit(intel, 1,
496 pitch, src_bo, src_offset, I915_TILING_NONE,
497 pitch, dst_bo, dst_offset, I915_TILING_NONE,
500 pitch, height, /* w, h */
504 src_offset += pitch * height;
505 dst_offset += pitch * height;
506 size -= pitch * height;
507 assert (size < (1 << 15));
508 assert ((size & 3) == 0); /* Pitch must be DWORD aligned */
510 ok = intelEmitCopyBlit(intel, 1,
511 size, src_bo, src_offset, I915_TILING_NONE,
512 size, dst_bo, dst_offset, I915_TILING_NONE,
522 * Used to initialize the alpha value of an ARGB8888 teximage after
523 * loading it from an XRGB8888 source.
525 * This is very common with glCopyTexImage2D().
528 intel_set_teximage_alpha_to_one(struct gl_context *ctx,
529 struct intel_texture_image *intel_image)
531 struct intel_context *intel = intel_context(ctx);
532 unsigned int image_x, image_y;
533 uint32_t x1, y1, x2, y2;
536 drm_intel_bo *aper_array[2];
537 struct intel_region *region = intel_image->mt->region;
540 assert(intel_image->base.TexFormat == MESA_FORMAT_ARGB8888);
542 /* get dest x/y in destination texture */
543 intel_miptree_get_image_offset(intel_image->mt,
551 x2 = image_x + intel_image->base.Width;
552 y2 = image_y + intel_image->base.Height;
554 pitch = region->pitch;
557 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
559 intel_image->mt->region->buffer, (pitch * cpp),
560 x1, y1, x2 - x1, y2 - y1);
562 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
563 CMD = XY_COLOR_BLT_CMD;
564 CMD |= XY_BLT_WRITE_ALPHA;
566 assert(region->tiling != I915_TILING_Y);
569 if (region->tiling != I915_TILING_NONE) {
574 BR13 |= (pitch * cpp);
576 /* do space check before going any further */
577 aper_array[0] = intel->batch.bo;
578 aper_array[1] = region->buffer;
580 if (drm_intel_bufmgr_check_aperture_space(aper_array,
581 ARRAY_SIZE(aper_array)) != 0) {
582 intel_batchbuffer_flush(intel);
588 OUT_BATCH((y1 << 16) | x1);
589 OUT_BATCH((y2 << 16) | x2);
590 OUT_RELOC_FENCED(region->buffer,
591 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
593 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
596 intel_batchbuffer_emit_mi_flush(intel);