2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_context.h"
26 #include "brw_state.h"
27 #include "brw_defines.h"
30 #include "program/prog_parameter.h"
31 #include "program/prog_statevars.h"
32 #include "intel_batchbuffer.h"
35 upload_wm_state(struct brw_context *brw)
37 struct intel_context *intel = &brw->intel;
38 struct gl_context *ctx = &intel->ctx;
39 const struct brw_fragment_program *fp =
40 brw_fragment_program_const(brw->fragment_program);
41 bool writes_depth = false;
42 bool multisampled = false;
46 if (ctx->DrawBuffer->_ColorDrawBuffers[0])
47 multisampled = ctx->DrawBuffer->_ColorDrawBuffers[0]->NumSamples > 0;
50 dw1 |= GEN7_WM_STATISTICS_ENABLE;
51 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
52 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
55 if (ctx->Line.StippleFlag)
56 dw1 |= GEN7_WM_LINE_STIPPLE_ENABLE;
59 if (ctx->Polygon.StippleFlag)
60 dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE;
62 /* BRW_NEW_FRAGMENT_PROGRAM */
63 if (fp->program.Base.InputsRead & FRAG_BIT_WPOS)
64 dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W;
65 if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
67 dw1 |= GEN7_WM_PSCDEPTH_ON;
69 /* CACHE_NEW_WM_PROG */
70 dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
71 GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
74 if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
75 dw1 |= GEN7_WM_KILL_ENABLE;
78 if (brw_color_buffer_write_enabled(brw) || writes_depth ||
79 dw1 & GEN7_WM_KILL_ENABLE) {
80 dw1 |= GEN7_WM_DISPATCH_ENABLE;
83 dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
84 dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
86 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
87 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
91 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
97 const struct brw_tracked_state gen7_wm_state = {
99 .mesa = (_NEW_LINE | _NEW_POLYGON |
100 _NEW_COLOR | _NEW_BUFFERS),
101 .brw = (BRW_NEW_FRAGMENT_PROGRAM |
103 .cache = CACHE_NEW_WM_PROG,
105 .emit = upload_wm_state,
109 upload_ps_state(struct brw_context *brw)
111 struct intel_context *intel = &brw->intel;
112 struct gl_context *ctx = &intel->ctx;
113 uint32_t dw2, dw4, dw5;
114 const int max_threads_shift = brw->intel.is_haswell ?
115 HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
117 /* BRW_NEW_PS_BINDING_TABLE */
119 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
120 OUT_BATCH(brw->wm.bind_bo_offset);
123 /* CACHE_NEW_SAMPLER */
125 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
126 OUT_BATCH(brw->sampler.offset);
129 /* CACHE_NEW_WM_PROG */
130 if (brw->wm.prog_data->nr_params == 0) {
131 /* Disable the push constant buffers. */
133 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
143 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
145 OUT_BATCH(ALIGN(brw->wm.prog_data->nr_params,
146 brw->wm.prog_data->dispatch_width) / 8);
148 /* Pointer to the WM constant buffer. Covered by the set of
149 * state flags from gen6_upload_wm_push_constants.
151 OUT_BATCH(brw->wm.push_const_offset);
160 /* CACHE_NEW_SAMPLER */
161 dw2 |= (ALIGN(brw->sampler.count, 4) / 4) << GEN7_PS_SAMPLER_COUNT_SHIFT;
163 /* Use ALT floating point mode for ARB fragment programs, because they
164 * require 0^0 == 1. Even though _CurrentFragmentProgram is used for
165 * rendering, CurrentFragmentProgram is used for this check to
166 * differentiate between the GLSL and non-GLSL cases.
168 if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
169 dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
171 if (intel->is_haswell)
172 dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
174 dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
176 /* CACHE_NEW_WM_PROG */
177 if (brw->wm.prog_data->nr_params > 0)
178 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
180 /* CACHE_NEW_WM_PROG | _NEW_COLOR
182 * The hardware wedges if you have this bit set but don't turn on any dual
183 * source blend factors.
185 if (brw->wm.prog_data->dual_src_blend &&
186 (ctx->Color.BlendEnabled & 1) &&
187 ctx->Color.Blend[0]._UsesDualSrc) {
188 dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
191 /* BRW_NEW_FRAGMENT_PROGRAM */
192 if (brw->fragment_program->Base.InputsRead != 0)
193 dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
195 if (brw->wm.prog_data->dispatch_width == 8) {
196 dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
197 if (brw->wm.prog_data->prog_offset_16)
198 dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
200 dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
203 dw5 |= (brw->wm.prog_data->first_curbe_grf <<
204 GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
205 dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
206 GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
209 OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
210 OUT_BATCH(brw->wm.prog_offset);
212 if (brw->wm.prog_data->total_scratch) {
213 OUT_RELOC(brw->wm.scratch_bo,
214 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
215 ffs(brw->wm.prog_data->total_scratch) - 11);
221 OUT_BATCH(0); /* kernel 1 pointer */
222 OUT_BATCH(brw->wm.prog_offset + brw->wm.prog_data->prog_offset_16);
226 const struct brw_tracked_state gen7_ps_state = {
228 .mesa = (_NEW_PROGRAM_CONSTANTS |
230 .brw = (BRW_NEW_FRAGMENT_PROGRAM |
231 BRW_NEW_PS_BINDING_TABLE |
233 .cache = (CACHE_NEW_SAMPLER |
236 .emit = upload_ps_state,