2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "intel_batchbuffer.h"
27 #include "intel_fbo.h"
28 #include "intel_mipmap_tree.h"
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_state.h"
34 #include "brw_blorp.h"
35 #include "gen7_blorp.h"
43 * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
44 * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
45 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
46 * programmed in order for the programming of this state to be
50 gen7_blorp_emit_urb_config(struct brw_context *brw,
51 const brw_blorp_params *params)
53 /* The minimum valid value is 32. See 3DSTATE_URB_VS,
54 * Dword 1.15:0 "VS Number of URB Entries".
56 int num_vs_entries = 32;
58 int vs_start = 2; /* skip over push constants */
60 gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
64 /* 3DSTATE_BLEND_STATE_POINTERS */
66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
67 const brw_blorp_params *params,
68 uint32_t cc_blend_state_offset)
70 struct intel_context *intel = &brw->intel;
73 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
74 OUT_BATCH(cc_blend_state_offset | 1);
79 /* 3DSTATE_CC_STATE_POINTERS */
81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
82 const brw_blorp_params *params,
83 uint32_t cc_state_offset)
85 struct intel_context *intel = &brw->intel;
88 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
89 OUT_BATCH(cc_state_offset | 1);
94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
95 const brw_blorp_params *params)
97 struct intel_context *intel = &brw->intel;
98 struct brw_cc_viewport *ccv;
99 uint32_t cc_vp_offset;
101 ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
104 ccv->min_depth = 0.0;
105 ccv->max_depth = 1.0;
108 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
109 OUT_BATCH(cc_vp_offset);
114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
116 * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
120 const brw_blorp_params *params,
121 uint32_t depthstencil_offset)
123 struct intel_context *intel = &brw->intel;
126 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
127 OUT_BATCH(depthstencil_offset | 1);
132 /* SURFACE_STATE for renderbuffer or texture surface (see
133 * brw_update_renderbuffer_surface and brw_update_texture_surface)
136 gen7_blorp_emit_surface_state(struct brw_context *brw,
137 const brw_blorp_params *params,
138 const brw_blorp_surface_info *surface,
139 uint32_t read_domains, uint32_t write_domain,
140 bool is_render_target)
142 struct intel_context *intel = &brw->intel;
144 uint32_t wm_surf_offset;
145 uint32_t width, height;
146 surface->get_miplevel_dims(&width, &height);
147 if (surface->map_stencil_as_y_tiled) {
151 struct intel_region *region = surface->mt->region;
153 struct gen7_surface_state *surf = (struct gen7_surface_state *)
154 brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
156 memset(surf, 0, sizeof(*surf));
158 if (surface->mt->align_h == 4)
159 surf->ss0.vertical_alignment = 1;
160 if (surface->mt->align_w == 8)
161 surf->ss0.horizontal_alignment = 1;
163 surf->ss0.surface_format = surface->brw_surfaceformat;
164 surf->ss0.surface_type = BRW_SURFACE_2D;
165 surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ?
166 GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
169 surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */
171 surf->ss2.width = width - 1;
172 surf->ss2.height = height - 1;
174 uint32_t tiling = surface->map_stencil_as_y_tiled
175 ? I915_TILING_Y : region->tiling;
176 gen7_set_surface_tiling(surf, tiling);
178 uint32_t pitch_bytes = region->pitch * region->cpp;
179 if (surface->map_stencil_as_y_tiled)
181 surf->ss3.pitch = pitch_bytes - 1;
183 gen7_set_surface_num_multisamples(surf, surface->num_samples);
184 if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
185 gen7_set_surface_mcs_info(brw, surf, wm_surf_offset,
186 surface->mt->mcs_mt, is_render_target);
189 if (intel->is_haswell) {
190 surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
191 surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
192 surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
193 surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
196 /* Emit relocation to surface contents */
197 drm_intel_bo_emit_reloc(brw->intel.batch.bo,
199 offsetof(struct gen7_surface_state, ss1),
201 surf->ss1.base_addr - region->bo->offset,
202 read_domains, write_domain);
204 gen7_check_surface_setup(surf, is_render_target);
206 return wm_surf_offset;
211 * SAMPLER_STATE. See gen7_update_sampler_state().
214 gen7_blorp_emit_sampler_state(struct brw_context *brw,
215 const brw_blorp_params *params)
217 uint32_t sampler_offset;
219 struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
220 brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
221 sizeof(struct gen7_sampler_state),
222 32, &sampler_offset);
223 memset(sampler, 0, sizeof(*sampler));
225 sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
226 sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
227 sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
229 sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
230 sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
231 sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
233 // sampler->ss0.min_mag_neq = 1;
237 sampler->ss0.lod_bias = 0;
239 sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
240 sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
242 /* Set BaseMipLevel, MaxLOD, MinLOD:
244 * XXX: I don't think that using firstLevel, lastLevel works,
245 * because we always setup the surface state as if firstLevel ==
246 * level zero. Probably have to subtract firstLevel from each of
249 sampler->ss0.base_level = U_FIXED(0, 1);
251 sampler->ss1.max_lod = U_FIXED(0, 8);
252 sampler->ss1.min_lod = U_FIXED(0, 8);
254 sampler->ss3.non_normalized_coord = 1;
256 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
257 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
258 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
259 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
260 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
261 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
263 return sampler_offset;
269 * Disable the hull shader.
272 gen7_blorp_emit_hs_disable(struct brw_context *brw,
273 const brw_blorp_params *params)
275 struct intel_context *intel = &brw->intel;
278 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
291 * Disable the tesselation engine.
294 gen7_blorp_emit_te_disable(struct brw_context *brw,
295 const brw_blorp_params *params)
297 struct intel_context *intel = &brw->intel;
300 OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
310 * Disable the domain shader.
313 gen7_blorp_emit_ds_disable(struct brw_context *brw,
314 const brw_blorp_params *params)
316 struct intel_context *intel = &brw->intel;
319 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
334 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
335 const brw_blorp_params *params)
337 struct intel_context *intel = &brw->intel;
340 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
348 gen7_blorp_emit_sf_config(struct brw_context *brw,
349 const brw_blorp_params *params)
351 struct intel_context *intel = &brw->intel;
355 * Disable ViewportTransformEnable (dw1.1)
357 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
358 * Primitives Overview":
359 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
360 * use of screen- space coordinates).
362 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
363 * and BackFaceFillMode (dw1.4:3) to SOLID(0).
365 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
366 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
367 * SOLID: Any triangle or rectangle object found to be front-facing
368 * is rendered as a solid object. This setting is required when
369 * (rendering rectangle (RECTLIST) objects.
373 OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
374 OUT_BATCH(params->depth_format <<
375 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
376 OUT_BATCH(params->num_samples > 0 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
387 OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
388 OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
389 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
390 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
391 for (int i = 0; i < 12; ++i)
399 * Disable thread dispatch (dw5.19) and enable the HiZ op.
402 gen7_blorp_emit_wm_config(struct brw_context *brw,
403 const brw_blorp_params *params,
404 brw_blorp_prog_data *prog_data)
406 struct intel_context *intel = &brw->intel;
408 uint32_t dw1 = 0, dw2 = 0;
410 switch (params->hiz_op) {
411 case GEN6_HIZ_OP_DEPTH_CLEAR:
412 dw1 |= GEN7_WM_DEPTH_CLEAR;
414 case GEN6_HIZ_OP_DEPTH_RESOLVE:
415 dw1 |= GEN7_WM_DEPTH_RESOLVE;
417 case GEN6_HIZ_OP_HIZ_RESOLVE:
418 dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
420 case GEN6_HIZ_OP_NONE:
426 dw1 |= GEN7_WM_STATISTICS_ENABLE;
427 dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
428 dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
429 dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
430 if (params->use_wm_prog) {
431 dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
432 dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
435 if (params->num_samples > 0) {
436 dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
437 if (prog_data && prog_data->persample_msaa_dispatch)
438 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
440 dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
442 dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
443 dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
447 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
457 * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
458 * that, thread dispatch info must still be specified.
459 * - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
460 * states that the valid range for this field is [0x3, 0x2f].
461 * - A dispatch mode must be given; that is, at least one of the
462 * "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
463 * discovered through simulator error messages.
466 gen7_blorp_emit_ps_config(struct brw_context *brw,
467 const brw_blorp_params *params,
468 uint32_t prog_offset,
469 brw_blorp_prog_data *prog_data)
471 struct intel_context *intel = &brw->intel;
472 uint32_t dw2, dw4, dw5;
473 const int max_threads_shift = brw->intel.is_haswell ?
474 HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
477 dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
479 /* If there's a WM program, we need to do 16-pixel dispatch since that's
480 * what the program is compiled for. If there isn't, then it shouldn't
481 * matter because no program is actually being run. However, the hardware
482 * gets angry if we don't enable at least one dispatch mode, so just enable
483 * 16-pixel dispatch unconditionally.
485 dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
487 if (intel->is_haswell)
488 dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
489 if (params->use_wm_prog) {
490 dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
491 dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
492 dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
496 OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
497 OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
509 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
510 const brw_blorp_params *params,
511 uint32_t wm_bind_bo_offset)
513 struct intel_context *intel = &brw->intel;
516 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
517 OUT_BATCH(wm_bind_bo_offset);
523 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
524 const brw_blorp_params *params,
525 uint32_t sampler_offset)
527 struct intel_context *intel = &brw->intel;
530 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
531 OUT_BATCH(sampler_offset);
537 gen7_blorp_emit_constant_ps(struct brw_context *brw,
538 const brw_blorp_params *params,
539 uint32_t wm_push_const_offset)
541 struct intel_context *intel = &brw->intel;
543 /* Make sure the push constants fill an exact integer number of
546 assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
548 /* There must be at least one register worth of push constant data. */
549 assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
551 /* Enable push constant buffer 0. */
553 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
555 OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
557 OUT_BATCH(wm_push_const_offset);
566 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
567 const brw_blorp_params *params)
569 struct intel_context *intel = &brw->intel;
570 uint32_t draw_x, draw_y;
571 uint32_t tile_mask_x, tile_mask_y;
573 if (params->depth.mt) {
574 params->depth.get_draw_offsets(&draw_x, &draw_y);
575 gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
578 /* 3DSTATE_DEPTH_BUFFER */
580 uint32_t width, height;
581 params->depth.get_miplevel_dims(&width, &height);
583 uint32_t tile_x = draw_x & tile_mask_x;
584 uint32_t tile_y = draw_y & tile_mask_y;
586 intel_region_get_aligned_offset(params->depth.mt->region,
587 draw_x & ~tile_mask_x,
588 draw_y & ~tile_mask_y);
590 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
591 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
592 * Coordinate Offset X/Y":
594 * "The 3 LSBs of both offsets must be zero to ensure correct
597 * We have no guarantee that tile_x and tile_y are correctly aligned,
598 * since they are determined by the mipmap layout, which is only aligned
601 * So, to avoid hanging the GPU, just smash the low order 3 bits of
602 * tile_x and tile_y to 0. This is a temporary workaround until we come
603 * up with a better solution.
608 intel_emit_depth_stall_flushes(intel);
611 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
612 uint32_t pitch_bytes =
613 params->depth.mt->region->pitch * params->depth.mt->region->cpp;
614 OUT_BATCH((pitch_bytes - 1) |
615 params->depth_format << 18 |
616 1 << 22 | /* hiz enable */
617 1 << 28 | /* depth write */
618 BRW_SURFACE_2D << 29);
619 OUT_RELOC(params->depth.mt->region->bo,
620 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
622 OUT_BATCH((width + tile_x - 1) << 4 |
623 (height + tile_y - 1) << 18);
631 /* 3DSTATE_HIER_DEPTH_BUFFER */
633 struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
634 uint32_t hiz_offset =
635 intel_region_get_aligned_offset(hiz_region,
636 draw_x & ~tile_mask_x,
637 (draw_y & ~tile_mask_y) / 2);
640 OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
641 OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
642 OUT_RELOC(hiz_region->bo,
643 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
648 /* 3DSTATE_STENCIL_BUFFER */
651 OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
660 gen7_blorp_emit_depth_disable(struct brw_context *brw,
661 const brw_blorp_params *params)
663 struct intel_context *intel = &brw->intel;
666 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
667 OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
677 /* 3DSTATE_CLEAR_PARAMS
679 * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
680 * 3DSTATE_CLEAR_PARAMS:
681 * [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
682 * with the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
683 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
686 gen7_blorp_emit_clear_params(struct brw_context *brw,
687 const brw_blorp_params *params)
689 struct intel_context *intel = &brw->intel;
692 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
693 OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
694 OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
701 gen7_blorp_emit_primitive(struct brw_context *brw,
702 const brw_blorp_params *params)
704 struct intel_context *intel = &brw->intel;
707 OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
708 OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
710 OUT_BATCH(3); /* vertex count per instance */
712 OUT_BATCH(1); /* instance count */
720 * \copydoc gen6_blorp_exec()
723 gen7_blorp_exec(struct intel_context *intel,
724 const brw_blorp_params *params)
726 struct gl_context *ctx = &intel->ctx;
727 struct brw_context *brw = brw_context(ctx);
728 brw_blorp_prog_data *prog_data = NULL;
729 uint32_t cc_blend_state_offset = 0;
730 uint32_t cc_state_offset = 0;
731 uint32_t depthstencil_offset;
732 uint32_t wm_push_const_offset = 0;
733 uint32_t wm_bind_bo_offset = 0;
734 uint32_t sampler_offset = 0;
736 uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
737 gen6_blorp_emit_batch_head(brw, params);
738 gen7_allocate_push_constants(brw);
739 gen6_emit_3dstate_multisample(brw, params->num_samples);
740 gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false);
741 gen6_blorp_emit_state_base_address(brw, params);
742 gen6_blorp_emit_vertices(brw, params);
743 gen7_blorp_emit_urb_config(brw, params);
744 if (params->use_wm_prog) {
745 cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
746 cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
747 gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
748 gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
750 depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
751 gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
752 depthstencil_offset);
753 if (params->use_wm_prog) {
754 uint32_t wm_surf_offset_renderbuffer;
755 uint32_t wm_surf_offset_texture;
756 wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
757 wm_surf_offset_renderbuffer =
758 gen7_blorp_emit_surface_state(brw, params, ¶ms->dst,
759 I915_GEM_DOMAIN_RENDER,
760 I915_GEM_DOMAIN_RENDER,
761 true /* is_render_target */);
762 wm_surf_offset_texture =
763 gen7_blorp_emit_surface_state(brw, params, ¶ms->src,
764 I915_GEM_DOMAIN_SAMPLER, 0,
765 false /* is_render_target */);
767 gen6_blorp_emit_binding_table(brw, params,
768 wm_surf_offset_renderbuffer,
769 wm_surf_offset_texture);
770 sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
772 gen6_blorp_emit_vs_disable(brw, params);
773 gen7_blorp_emit_hs_disable(brw, params);
774 gen7_blorp_emit_te_disable(brw, params);
775 gen7_blorp_emit_ds_disable(brw, params);
776 gen6_blorp_emit_gs_disable(brw, params);
777 gen7_blorp_emit_streamout_disable(brw, params);
778 gen6_blorp_emit_clip_disable(brw, params);
779 gen7_blorp_emit_sf_config(brw, params);
780 gen7_blorp_emit_wm_config(brw, params, prog_data);
781 if (params->use_wm_prog) {
782 gen7_blorp_emit_binding_table_pointers_ps(brw, params,
784 gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
785 gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
787 gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
788 gen7_blorp_emit_cc_viewport(brw, params);
790 if (params->depth.mt)
791 gen7_blorp_emit_depth_stencil_config(brw, params);
793 gen7_blorp_emit_depth_disable(brw, params);
794 gen7_blorp_emit_clear_params(brw, params);
795 gen6_blorp_emit_drawing_rectangle(brw, params);
796 gen7_blorp_emit_primitive(brw, params);
798 /* See comments above at first invocation of intel_flush() in
799 * gen6_blorp_emit_batch_head().
804 brw->state.dirty.brw = ~0;
805 brw->state.dirty.cache = ~0;