2 * Copyright © 2009 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
32 #include "main/macros.h"
33 #include "intel_batchbuffer.h"
36 get_attr_override(struct brw_context *brw, int fs_attr, int two_side_color)
38 int attr_index = 0, i, vs_attr;
41 if (fs_attr <= FRAG_ATTRIB_TEX7)
43 else if (fs_attr == FRAG_ATTRIB_FACE)
44 vs_attr = 0; /* XXX */
45 else if (fs_attr == FRAG_ATTRIB_PNTC)
46 vs_attr = 0; /* XXX */
48 assert(fs_attr >= FRAG_ATTRIB_VAR0);
49 vs_attr = fs_attr - FRAG_ATTRIB_VAR0 + VERT_RESULT_VAR0;
52 /* Find the source index (0 = first attribute after the 4D position)
53 * for this output attribute. attr is currently a VERT_RESULT_* but should
56 for (i = 1; i < vs_attr; i++) {
57 if (i == VERT_RESULT_PSIZ)
59 if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(i))
63 assert(attr_index < 32);
66 if ((brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1)) &&
67 (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1))) {
68 assert(brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0));
69 assert(brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0));
71 } else if ((brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0)) &&
72 (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0)))
76 if (bfc && (fs_attr <= FRAG_ATTRIB_TEX7 && fs_attr > FRAG_ATTRIB_WPOS)) {
77 if (fs_attr == FRAG_ATTRIB_COL0)
78 attr_index |= (ATTRIBUTE_SWIZZLE_INPUTATTR_FACING << ATTRIBUTE_SWIZZLE_SHIFT);
79 else if (fs_attr == FRAG_ATTRIB_COL1 && bfc == 2) {
81 attr_index |= (ATTRIBUTE_SWIZZLE_INPUTATTR_FACING << ATTRIBUTE_SWIZZLE_SHIFT);
91 upload_sf_state(struct brw_context *brw)
93 struct intel_context *intel = &brw->intel;
94 struct gl_context *ctx = &intel->ctx;
95 /* CACHE_NEW_VS_PROG */
96 uint32_t num_inputs = brw_count_bits(brw->vs.prog_data->outputs_written);
97 /* BRW_NEW_FRAGMENT_PROGRAM */
98 uint32_t num_outputs = brw_count_bits(brw->fragment_program->Base.InputsRead);
99 uint32_t dw1, dw2, dw3, dw4, dw16, dw17;
102 GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
103 int attr = 0, input_index = 0;
105 int two_side_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
107 uint16_t attr_overrides[FRAG_ATTRIB_MAX];
110 if (ctx->Transform.ClipPlanesEnabled)
116 GEN6_SF_SWIZZLE_ENABLE |
117 num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
118 (num_inputs + 1) / 2 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
119 urb_start << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
120 dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
121 GEN6_SF_STATISTICS_ENABLE;
128 if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
129 dw2 |= GEN6_SF_WINDING_CCW;
131 if (ctx->Polygon.OffsetFill)
132 dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
134 if (ctx->Polygon.OffsetLine)
135 dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
137 if (ctx->Polygon.OffsetPoint)
138 dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
140 switch (ctx->Polygon.FrontMode) {
142 dw2 |= GEN6_SF_FRONT_SOLID;
146 dw2 |= GEN6_SF_FRONT_WIREFRAME;
150 dw2 |= GEN6_SF_FRONT_POINT;
158 switch (ctx->Polygon.BackMode) {
160 dw2 |= GEN6_SF_BACK_SOLID;
164 dw2 |= GEN6_SF_BACK_WIREFRAME;
168 dw2 |= GEN6_SF_BACK_POINT;
177 if (ctx->Scissor.Enabled)
178 dw3 |= GEN6_SF_SCISSOR_ENABLE;
181 if (ctx->Polygon.CullFlag) {
182 switch (ctx->Polygon.CullFaceMode) {
184 dw3 |= GEN6_SF_CULL_FRONT;
187 dw3 |= GEN6_SF_CULL_BACK;
189 case GL_FRONT_AND_BACK:
190 dw3 |= GEN6_SF_CULL_BOTH;
197 dw3 |= GEN6_SF_CULL_NONE;
201 dw3 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
202 GEN6_SF_LINE_WIDTH_SHIFT;
203 if (ctx->Line.SmoothFlag) {
204 dw3 |= GEN6_SF_LINE_AA_ENABLE;
205 dw3 |= GEN6_SF_LINE_AA_MODE_TRUE;
206 dw3 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
210 if (!(ctx->VertexProgram.PointSizeEnabled ||
211 ctx->Point._Attenuated))
212 dw4 |= GEN6_SF_USE_STATE_POINT_WIDTH;
214 /* Clamp to ARB_point_parameters user limits */
215 point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
217 /* Clamp to the hardware limits and convert to fixed point */
218 dw4 |= U_FIXED(CLAMP(point_size, 0.125, 255.875), 3);
220 if (ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
221 dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
224 if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
226 (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
227 (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
228 (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
231 (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
234 /* Create the mapping from the FS inputs we produce to the VS outputs
237 for (; attr < FRAG_ATTRIB_MAX; attr++) {
238 if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
242 if (ctx->Point.PointSprite &&
243 (attr >= FRAG_ATTRIB_TEX0 && attr <= FRAG_ATTRIB_TEX7) &&
244 ctx->Point.CoordReplace[attr - FRAG_ATTRIB_TEX0]) {
245 dw16 |= (1 << input_index);
248 if (attr == FRAG_ATTRIB_PNTC)
249 dw16 |= (1 << input_index);
252 if (ctx->Light.ShadeModel == GL_FLAT) {
254 * Setup the Constant Interpolation Enable bit mask for each
255 * corresponding attribute(currently, we only care two attrs:
256 * FRAG_BIT_COL0 and FRAG_BIT_COL1).
258 * FIXME: should we care other attributes?
260 if (attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1)
261 dw17 |= (1 << input_index);
264 /* The hardware can only do the overrides on 16 overrides at a
265 * time, and the other up to 16 have to be lined up so that the
266 * input index = the output index. We'll need to do some
267 * tweaking to make sure that's the case.
269 assert(input_index < 16 || attr == input_index);
271 attr_overrides[input_index++] = get_attr_override(brw, attr,
275 for (; input_index < FRAG_ATTRIB_MAX; input_index++)
276 attr_overrides[input_index] = 0;
279 OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
284 OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant. copied from gen4 */
285 OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
286 OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
287 for (i = 0; i < 8; i++) {
288 OUT_BATCH(attr_overrides[i * 2] | attr_overrides[i * 2 + 1] << 16);
290 OUT_BATCH(dw16); /* point sprite texcoord bitmask */
291 OUT_BATCH(dw17); /* constant interp bitmask */
292 OUT_BATCH(0); /* wrapshortest enables 0-7 */
293 OUT_BATCH(0); /* wrapshortest enables 8-15 */
297 const struct brw_tracked_state gen6_sf_state = {
299 .mesa = (_NEW_LIGHT |
306 .brw = (BRW_NEW_CONTEXT |
307 BRW_NEW_FRAGMENT_PROGRAM),
308 .cache = CACHE_NEW_VS_PROG
310 .emit = upload_sf_state,