src/mesa/drivers/dri/i965/gen6_depthstencil.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30
  31 static void
  32 gen6_prepare_depth_stencil_state(struct brw_context *brw)
  33 {
  34    struct gl_context *ctx = &brw->intel.ctx;
  35    struct gen6_depth_stencil_state *ds;
  36
  37    ds = brw_state_batch(brw, sizeof(*ds), 64,
  38                         &brw->cc.depth_stencil_state_offset);
  39    memset(ds, 0, sizeof(*ds));
  40
  41    /* _NEW_STENCIL */
  42    if (ctx->Stencil._Enabled) {
  43       int back = ctx->Stencil._BackFace;
  44
  45       ds->ds0.stencil_enable = 1;
  46       ds->ds0.stencil_func =
  47          intel_translate_compare_func(ctx->Stencil.Function[0]);
  48       ds->ds0.stencil_fail_op =
  49          intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
  50       ds->ds0.stencil_pass_depth_fail_op =
  51          intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
  52       ds->ds0.stencil_pass_depth_pass_op =
  53          intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
  54       ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
  55       ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0];
  56
  57       if (ctx->Stencil._TestTwoSide) {
  58          ds->ds0.bf_stencil_enable = 1;
  59          ds->ds0.bf_stencil_func =
  60             intel_translate_compare_func(ctx->Stencil.Function[back]);
  61          ds->ds0.bf_stencil_fail_op =
  62             intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
  63          ds->ds0.bf_stencil_pass_depth_fail_op =
  64             intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
  65          ds->ds0.bf_stencil_pass_depth_pass_op =
  66             intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
  67          ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
  68          ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
  69       }
  70
  71       /* Not really sure about this:
  72        */
  73       if (ctx->Stencil.WriteMask[0] ||
  74           (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
  75          ds->ds0.stencil_write_enable = 1;
  76    }
  77
  78    /* _NEW_DEPTH */
  79    if (ctx->Depth.Test) {
  80       ds->ds2.depth_test_enable = 1;
  81       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
  82       ds->ds2.depth_write_enable = ctx->Depth.Mask;
  83    }
  84
  85    brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE;
  86 }
  87
  88 const struct brw_tracked_state gen6_depth_stencil_state = {
  89    .dirty = {
  90       .mesa = _NEW_DEPTH | _NEW_STENCIL,
  91       .brw = BRW_NEW_BATCH,
  92       .cache = 0,
  93    },
  94    .prepare = gen6_prepare_depth_stencil_state,
  95 };