2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
37 /* Use these to force spilling so that that functionality can be
38 * tested with known-good examples rather than having to construct new
41 #define TEST_PAYLOAD_SPILLS 0
42 #define TEST_DST_SPILLS 0
44 static void spill_value(struct brw_wm_compile *c,
45 struct brw_wm_value *value);
47 static void prealloc_reg(struct brw_wm_compile *c,
48 struct brw_wm_value *value,
52 /* Set nextuse to zero, it will be corrected by
53 * update_register_usage().
55 c->pass2_grf[reg].value = value;
56 c->pass2_grf[reg].nextuse = 0;
58 value->resident = &c->pass2_grf[reg];
59 value->hw_reg = brw_vec8_grf(reg*2, 0);
61 if (TEST_PAYLOAD_SPILLS)
62 spill_value(c, value);
67 /* Initialize all the register values. Do the initial setup
68 * calculations for interpolants.
70 static void init_registers( struct brw_wm_compile *c )
72 struct brw_context *brw = c->func.brw;
73 struct intel_context *intel = &brw->intel;
74 GLuint nr_interp_regs = 0;
78 for (j = 0; j < c->grf_limit; j++)
79 c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
81 for (j = 0; j < (c->nr_payload_regs + 1) / 2; j++)
82 prealloc_reg(c, &c->payload.depth[j], i++);
84 for (j = 0; j < c->nr_creg; j++)
85 prealloc_reg(c, &c->creg[j], i++);
87 if (intel->gen >= 6) {
88 for (unsigned int j = 0; j < FRAG_ATTRIB_MAX; j++) {
89 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(j)) {
91 prealloc_reg(c, &c->payload.input_interp[j], i++);
95 for (j = 0; j < VERT_RESULT_MAX; j++) {
96 if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
99 if (j >= VERT_RESULT_VAR0)
100 fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
101 else if (j <= VERT_RESULT_TEX7)
108 prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
111 assert(nr_interp_regs >= 1);
115 c->prog_data.first_curbe_grf = ALIGN(c->nr_payload_regs, 2);
116 c->prog_data.urb_read_length = nr_interp_regs * 2;
117 c->prog_data.curb_read_length = c->nr_creg * 2;
119 c->max_wm_grf = i * 2;
123 /* Update the nextuse value for each register in our file.
125 static void update_register_usage(struct brw_wm_compile *c,
130 for (i = 1; i < c->grf_limit; i++) {
131 struct brw_wm_grf *grf = &c->pass2_grf[i];
133 /* Only search those which can change:
135 if (grf->nextuse < thisinsn) {
136 const struct brw_wm_ref *ref = grf->value->lastuse;
138 /* Has last use of value been passed?
140 if (ref->insn < thisinsn) {
141 grf->value->resident = 0;
143 grf->nextuse = BRW_WM_MAX_INSN;
146 /* Else loop through chain to update:
148 while (ref->prevuse && ref->prevuse->insn >= thisinsn)
151 grf->nextuse = ref->insn;
158 static void spill_value(struct brw_wm_compile *c,
159 struct brw_wm_value *value)
161 /* Allocate a spill slot. Note that allocations start from 0x40 -
162 * the first slot is reserved to mean "undef" in brw_wm_emit.c
164 if (!value->spill_slot) {
165 c->last_scratch += 0x40;
166 value->spill_slot = c->last_scratch;
169 /* The spill will be done in brw_wm_emit.c immediately after the
170 * value is calculated, so we can just take this reg without any
173 value->resident->value = NULL;
174 value->resident->nextuse = BRW_WM_MAX_INSN;
175 value->resident = NULL;
180 /* Search for contiguous region with the most distant nearest
181 * member. Free regs count as very distant.
183 * TODO: implement spill-to-reg so that we can rearrange discontigous
184 * free regs and then spill the oldest non-free regs in sequence.
185 * This would mean inserting instructions in this pass.
187 static GLuint search_contiguous_regs(struct brw_wm_compile *c,
191 struct brw_wm_grf *grf = c->pass2_grf;
196 /* Start search at 1: r0 is special and can't be used or spilled.
198 for (i = 1; i < c->grf_limit && furthest < BRW_WM_MAX_INSN; i++) {
199 GLuint group_nextuse = BRW_WM_MAX_INSN;
201 for (j = 0; j < nr; j++) {
202 if (grf[i+j].nextuse < group_nextuse)
203 group_nextuse = grf[i+j].nextuse;
206 if (group_nextuse > furthest) {
207 furthest = group_nextuse;
212 assert(furthest != thisinsn);
214 /* Any non-empty regs will need to be spilled:
216 for (j = 0; j < nr; j++)
217 if (grf[reg+j].value)
218 spill_value(c, grf[reg+j].value);
224 static void alloc_contiguous_dest(struct brw_wm_compile *c,
225 struct brw_wm_value *dst[],
229 GLuint reg = search_contiguous_regs(c, nr, thisinsn);
232 for (i = 0; i < nr; i++) {
234 /* Need to grab a dummy value in TEX case. Don't introduce
235 * it into the tracking scheme.
237 dst[i] = &c->vreg[c->nr_vreg++];
240 assert(!dst[i]->resident);
241 assert(c->pass2_grf[reg+i].nextuse != thisinsn);
243 c->pass2_grf[reg+i].value = dst[i];
244 c->pass2_grf[reg+i].nextuse = thisinsn;
246 dst[i]->resident = &c->pass2_grf[reg+i];
249 dst[i]->hw_reg = brw_vec8_grf((reg+i)*2, 0);
252 if ((reg+nr)*2 > c->max_wm_grf)
253 c->max_wm_grf = (reg+nr) * 2;
257 static void load_args(struct brw_wm_compile *c,
258 struct brw_wm_instruction *inst)
260 GLuint thisinsn = inst - c->instruction;
263 for (i = 0; i < 3; i++) {
264 for (j = 0; j < 4; j++) {
265 struct brw_wm_ref *ref = inst->src[i][j];
268 if (!ref->value->resident) {
269 /* Need to bring the value in from scratch space. The code for
270 * this will be done in brw_wm_emit.c, here we just do the
271 * register allocation and mark the ref as requiring a fill.
273 GLuint reg = search_contiguous_regs(c, 1, thisinsn);
275 c->pass2_grf[reg].value = ref->value;
276 c->pass2_grf[reg].nextuse = thisinsn;
278 ref->value->resident = &c->pass2_grf[reg];
280 /* Note that a fill is required:
282 ref->unspill_reg = reg*2;
285 /* Adjust the hw_reg to point at the value's current location:
287 assert(ref->value == ref->value->resident->value);
288 ref->hw_reg.nr += (ref->value->resident - c->pass2_grf) * 2;
296 /* Step 3: Work forwards once again. Perform register allocations,
297 * taking into account instructions like TEX which require contiguous
298 * result registers. Where necessary spill registers to scratch space
301 void brw_wm_pass2( struct brw_wm_compile *c )
308 for (insn = 0; insn < c->nr_insns; insn++) {
309 struct brw_wm_instruction *inst = &c->instruction[insn];
311 /* Update registers' nextuse values:
313 update_register_usage(c, insn);
315 /* May need to unspill some args.
319 /* Allocate registers to hold results:
321 switch (inst->opcode) {
325 alloc_contiguous_dest(c, inst->dst, 4, insn);
329 for (i = 0; i < 4; i++) {
330 if (inst->writemask & (1<<i)) {
331 assert(inst->dst[i]);
332 alloc_contiguous_dest(c, &inst->dst[i], 1, insn);
338 if (TEST_DST_SPILLS && inst->opcode != WM_PIXELXY) {
339 for (i = 0; i < 4; i++)
341 spill_value(c, inst->dst[i]);
345 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
346 brw_wm_print_program(c, "pass2");
349 c->state = PASS2_DONE;
351 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
352 brw_wm_print_program(c, "pass2/done");