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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "../glsl/glsl_types.h"
50 #include "../glsl/ir_optimization.h"
51 #include "../glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable *ir)
58 if (variable_storage(ir))
61 if (strcmp(ir->name, "gl_FragColor") == 0) {
62 this->frag_color = ir;
63 } else if (strcmp(ir->name, "gl_FragData") == 0) {
65 } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
66 this->frag_depth = ir;
69 if (ir->mode == ir_var_in) {
70 if (!strcmp(ir->name, "gl_FragCoord")) {
71 reg = emit_fragcoord_interpolation(ir);
72 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
73 reg = emit_frontfacing_interpolation(ir);
75 reg = emit_general_interpolation(ir);
78 hash_table_insert(this->variable_ht, reg, ir);
82 if (ir->mode == ir_var_uniform) {
83 int param_index = c->prog_data.nr_params;
85 if (c->dispatch_width == 16) {
86 if (!variable_storage(ir)) {
87 fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
92 if (!strncmp(ir->name, "gl_", 3)) {
93 setup_builtin_uniform_values(ir);
95 setup_uniform_values(ir->location, ir->type);
98 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
99 reg->type = brw_type_for_base_type(ir->type);
103 reg = new(this->mem_ctx) fs_reg(this, ir->type);
105 hash_table_insert(this->variable_ht, reg, ir);
109 fs_visitor::visit(ir_dereference_variable *ir)
111 fs_reg *reg = variable_storage(ir->var);
116 fs_visitor::visit(ir_dereference_record *ir)
118 const glsl_type *struct_type = ir->record->type;
120 ir->record->accept(this);
122 unsigned int offset = 0;
123 for (unsigned int i = 0; i < struct_type->length; i++) {
124 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
126 offset += type_size(struct_type->fields.structure[i].type);
128 this->result.reg_offset += offset;
129 this->result.type = brw_type_for_base_type(ir->type);
133 fs_visitor::visit(ir_dereference_array *ir)
138 ir->array->accept(this);
139 index = ir->array_index->as_constant();
141 element_size = type_size(ir->type);
142 this->result.type = brw_type_for_base_type(ir->type);
145 assert(this->result.file == UNIFORM ||
146 (this->result.file == GRF &&
147 this->result.reg != 0));
148 this->result.reg_offset += index->value.i[0] * element_size;
150 assert(!"FINISHME: non-constant array element");
154 /* Instruction selection: Produce a MOV.sat instead of
155 * MIN(MAX(val, 0), 1) when possible.
158 fs_visitor::try_emit_saturate(ir_expression *ir)
160 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
165 this->result = reg_undef;
166 sat_val->accept(this);
167 fs_reg src = this->result;
169 this->result = fs_reg(this, ir->type);
170 fs_inst *inst = emit(BRW_OPCODE_MOV, this->result, src);
171 inst->saturate = true;
177 fs_visitor::visit(ir_expression *ir)
179 unsigned int operand;
183 assert(ir->get_num_operands() <= 2);
185 if (try_emit_saturate(ir))
188 /* This is where our caller would like us to put the result, if possible. */
189 fs_reg saved_result_storage = this->result;
191 for (operand = 0; operand < ir->get_num_operands(); operand++) {
192 this->result = reg_undef;
193 ir->operands[operand]->accept(this);
194 if (this->result.file == BAD_FILE) {
196 fail("Failed to get tree for expression operand:\n");
197 ir->operands[operand]->accept(&v);
199 op[operand] = this->result;
201 /* Matrix expression operands should have been broken down to vector
202 * operations already.
204 assert(!ir->operands[operand]->type->is_matrix());
205 /* And then those vector operands should have been broken down to scalar.
207 assert(!ir->operands[operand]->type->is_vector());
210 /* Inherit storage from our parent if possible, and otherwise we
213 if (saved_result_storage.file == BAD_FILE) {
214 this->result = fs_reg(this, ir->type);
216 this->result = saved_result_storage;
219 switch (ir->operation) {
220 case ir_unop_logic_not:
221 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
222 * ones complement of the whole register, not just bit 0.
224 emit(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1));
227 op[0].negate = !op[0].negate;
228 this->result = op[0];
232 op[0].negate = false;
233 this->result = op[0];
236 temp = fs_reg(this, ir->type);
238 /* Unalias the destination. (imagine a = sign(a)) */
239 this->result = fs_reg(this, ir->type);
241 emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f));
243 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
244 inst->conditional_mod = BRW_CONDITIONAL_G;
245 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(1.0f));
246 inst->predicated = true;
248 inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
249 inst->conditional_mod = BRW_CONDITIONAL_L;
250 inst = emit(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f));
251 inst->predicated = true;
255 emit_math(FS_OPCODE_RCP, this->result, op[0]);
259 emit_math(FS_OPCODE_EXP2, this->result, op[0]);
262 emit_math(FS_OPCODE_LOG2, this->result, op[0]);
266 assert(!"not reached: should be handled by ir_explog_to_explog2");
269 case ir_unop_sin_reduced:
270 emit_math(FS_OPCODE_SIN, this->result, op[0]);
273 case ir_unop_cos_reduced:
274 emit_math(FS_OPCODE_COS, this->result, op[0]);
278 emit(FS_OPCODE_DDX, this->result, op[0]);
281 emit(FS_OPCODE_DDY, this->result, op[0]);
285 emit(BRW_OPCODE_ADD, this->result, op[0], op[1]);
288 assert(!"not reached: should be handled by ir_sub_to_add_neg");
292 emit(BRW_OPCODE_MUL, this->result, op[0], op[1]);
295 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
298 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
302 case ir_binop_greater:
303 case ir_binop_lequal:
304 case ir_binop_gequal:
306 case ir_binop_all_equal:
307 case ir_binop_nequal:
308 case ir_binop_any_nequal:
310 /* original gen4 does implicit conversion before comparison. */
312 temp.type = op[0].type;
314 inst = emit(BRW_OPCODE_CMP, temp, op[0], op[1]);
315 inst->conditional_mod = brw_conditional_for_comparison(ir->operation);
316 emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1));
319 case ir_binop_logic_xor:
320 emit(BRW_OPCODE_XOR, this->result, op[0], op[1]);
323 case ir_binop_logic_or:
324 emit(BRW_OPCODE_OR, this->result, op[0], op[1]);
327 case ir_binop_logic_and:
328 emit(BRW_OPCODE_AND, this->result, op[0], op[1]);
333 assert(!"not reached: should be handled by brw_fs_channel_expressions");
337 assert(!"not reached: should be handled by lower_noise");
340 case ir_quadop_vector:
341 assert(!"not reached: should be handled by lower_quadop_vector");
345 emit_math(FS_OPCODE_SQRT, this->result, op[0]);
349 emit_math(FS_OPCODE_RSQ, this->result, op[0]);
356 emit(BRW_OPCODE_MOV, this->result, op[0]);
361 /* original gen4 does implicit conversion before comparison. */
363 temp.type = op[0].type;
365 inst = emit(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f));
366 inst->conditional_mod = BRW_CONDITIONAL_NZ;
367 inst = emit(BRW_OPCODE_AND, this->result, this->result, fs_reg(1));
371 emit(BRW_OPCODE_RNDZ, this->result, op[0]);
374 op[0].negate = !op[0].negate;
375 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]);
376 this->result.negate = true;
379 inst = emit(BRW_OPCODE_RNDD, this->result, op[0]);
382 inst = emit(BRW_OPCODE_FRC, this->result, op[0]);
384 case ir_unop_round_even:
385 emit(BRW_OPCODE_RNDE, this->result, op[0]);
389 if (intel->gen >= 6) {
390 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]);
391 inst->conditional_mod = BRW_CONDITIONAL_L;
393 /* Unalias the destination */
394 this->result = fs_reg(this, ir->type);
396 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]);
397 inst->conditional_mod = BRW_CONDITIONAL_L;
399 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]);
400 inst->predicated = true;
404 if (intel->gen >= 6) {
405 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]);
406 inst->conditional_mod = BRW_CONDITIONAL_GE;
408 /* Unalias the destination */
409 this->result = fs_reg(this, ir->type);
411 inst = emit(BRW_OPCODE_CMP, this->result, op[0], op[1]);
412 inst->conditional_mod = BRW_CONDITIONAL_G;
414 inst = emit(BRW_OPCODE_SEL, this->result, op[0], op[1]);
415 inst->predicated = true;
420 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]);
423 case ir_unop_bit_not:
424 inst = emit(BRW_OPCODE_NOT, this->result, op[0]);
426 case ir_binop_bit_and:
427 inst = emit(BRW_OPCODE_AND, this->result, op[0], op[1]);
429 case ir_binop_bit_xor:
430 inst = emit(BRW_OPCODE_XOR, this->result, op[0], op[1]);
432 case ir_binop_bit_or:
433 inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]);
437 case ir_binop_lshift:
438 case ir_binop_rshift:
439 assert(!"GLSL 1.30 features unsupported");
445 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
446 const glsl_type *type, bool predicated)
448 switch (type->base_type) {
449 case GLSL_TYPE_FLOAT:
453 for (unsigned int i = 0; i < type->components(); i++) {
454 l.type = brw_type_for_base_type(type);
455 r.type = brw_type_for_base_type(type);
457 if (predicated || !l.equals(&r)) {
458 fs_inst *inst = emit(BRW_OPCODE_MOV, l, r);
459 inst->predicated = predicated;
466 case GLSL_TYPE_ARRAY:
467 for (unsigned int i = 0; i < type->length; i++) {
468 emit_assignment_writes(l, r, type->fields.array, predicated);
472 case GLSL_TYPE_STRUCT:
473 for (unsigned int i = 0; i < type->length; i++) {
474 emit_assignment_writes(l, r, type->fields.structure[i].type,
479 case GLSL_TYPE_SAMPLER:
483 assert(!"not reached");
489 fs_visitor::visit(ir_assignment *ir)
494 /* FINISHME: arrays on the lhs */
495 this->result = reg_undef;
496 ir->lhs->accept(this);
499 /* If we're doing a direct assignment, an RHS expression could
500 * drop its result right into our destination. Otherwise, tell it
504 !(ir->lhs->type->is_scalar() ||
505 (ir->lhs->type->is_vector() &&
506 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) {
507 this->result = reg_undef;
510 ir->rhs->accept(this);
513 assert(l.file != BAD_FILE);
514 assert(r.file != BAD_FILE);
517 emit_bool_to_cond_code(ir->condition);
520 if (ir->lhs->type->is_scalar() ||
521 ir->lhs->type->is_vector()) {
522 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
523 if (ir->write_mask & (1 << i)) {
525 inst = emit(BRW_OPCODE_MOV, l, r);
526 inst->predicated = true;
527 } else if (!l.equals(&r)) {
528 inst = emit(BRW_OPCODE_MOV, l, r);
536 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
541 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
552 if (ir->shadow_comparitor && ir->op != ir_txd) {
553 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
554 fs_inst *inst = emit(BRW_OPCODE_MOV,
555 fs_reg(MRF, base_mrf + mlen + i), coordinate);
556 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler))
557 inst->saturate = true;
559 coordinate.reg_offset++;
561 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
564 if (ir->op == ir_tex) {
565 /* There's no plain shadow compare message, so we use shadow
566 * compare with a bias of 0.0.
568 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f));
570 } else if (ir->op == ir_txb) {
571 this->result = reg_undef;
572 ir->lod_info.bias->accept(this);
573 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
576 assert(ir->op == ir_txl);
577 this->result = reg_undef;
578 ir->lod_info.lod->accept(this);
579 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
583 this->result = reg_undef;
584 ir->shadow_comparitor->accept(this);
585 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
587 } else if (ir->op == ir_tex) {
588 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
589 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
591 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler))
592 inst->saturate = true;
593 coordinate.reg_offset++;
595 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
597 } else if (ir->op == ir_txd) {
598 this->result = reg_undef;
599 ir->lod_info.grad.dPdx->accept(this);
600 fs_reg dPdx = this->result;
602 this->result = reg_undef;
603 ir->lod_info.grad.dPdy->accept(this);
604 fs_reg dPdy = this->result;
606 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
607 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i), coordinate);
608 coordinate.reg_offset++;
610 /* the slots for u and v are always present, but r is optional */
611 mlen += MAX2(ir->coordinate->type->vector_elements, 2);
614 * dPdx = dudx, dvdx, drdx
615 * dPdy = dudy, dvdy, drdy
617 * 1-arg: Does not exist.
619 * 2-arg: dudx dvdx dudy dvdy
620 * dPdx.x dPdx.y dPdy.x dPdy.y
623 * 3-arg: dudx dvdx drdx dudy dvdy drdy
624 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
627 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
628 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx);
631 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
633 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
634 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy);
637 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
639 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
640 * instructions. We'll need to do SIMD16 here.
642 assert(ir->op == ir_txb || ir->op == ir_txl);
644 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
645 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF,
646 base_mrf + mlen + i * 2),
648 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler))
649 inst->saturate = true;
650 coordinate.reg_offset++;
653 /* lod/bias appears after u/v/r. */
656 if (ir->op == ir_txb) {
657 this->result = reg_undef;
658 ir->lod_info.bias->accept(this);
659 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
662 this->result = reg_undef;
663 ir->lod_info.lod->accept(this);
664 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
668 /* The unused upper half. */
671 /* Now, since we're doing simd16, the return is 2 interleaved
672 * vec4s where the odd-indexed ones are junk. We'll need to move
673 * this weirdness around to the expected layout.
677 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type,
679 dst.type = BRW_REGISTER_TYPE_F;
682 fs_inst *inst = NULL;
685 inst = emit(FS_OPCODE_TEX, dst);
688 inst = emit(FS_OPCODE_TXB, dst);
691 inst = emit(FS_OPCODE_TXL, dst);
694 inst = emit(FS_OPCODE_TXD, dst);
697 assert(!"GLSL 1.30 features unsupported");
700 inst->base_mrf = base_mrf;
702 inst->header_present = true;
705 for (int i = 0; i < 4; i++) {
706 emit(BRW_OPCODE_MOV, orig_dst, dst);
707 orig_dst.reg_offset++;
715 /* gen5's sampler has slots for u, v, r, array index, then optional
716 * parameters like shadow comparitor or LOD bias. If optional
717 * parameters aren't present, those base slots are optional and don't
718 * need to be included in the message.
720 * We don't fill in the unnecessary slots regardless, which may look
721 * surprising in the disassembly.
724 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
729 int reg_width = c->dispatch_width / 8;
730 bool header_present = false;
733 /* The offsets set up by the ir_texture visitor are in the
734 * m1 header, so we can't go headerless.
736 header_present = true;
741 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
742 fs_inst *inst = emit(BRW_OPCODE_MOV,
743 fs_reg(MRF, base_mrf + mlen + i * reg_width),
745 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler))
746 inst->saturate = true;
747 coordinate.reg_offset++;
749 mlen += ir->coordinate->type->vector_elements * reg_width;
751 if (ir->shadow_comparitor && ir->op != ir_txd) {
752 mlen = MAX2(mlen, header_present + 4 * reg_width);
754 this->result = reg_undef;
755 ir->shadow_comparitor->accept(this);
756 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
760 fs_inst *inst = NULL;
763 inst = emit(FS_OPCODE_TEX, dst);
766 this->result = reg_undef;
767 ir->lod_info.bias->accept(this);
768 mlen = MAX2(mlen, header_present + 4 * reg_width);
769 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
772 inst = emit(FS_OPCODE_TXB, dst);
776 this->result = reg_undef;
777 ir->lod_info.lod->accept(this);
778 mlen = MAX2(mlen, header_present + 4 * reg_width);
779 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
782 inst = emit(FS_OPCODE_TXL, dst);
785 this->result = reg_undef;
786 ir->lod_info.grad.dPdx->accept(this);
787 fs_reg dPdx = this->result;
789 this->result = reg_undef;
790 ir->lod_info.grad.dPdy->accept(this);
791 fs_reg dPdy = this->result;
793 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
797 * dPdx = dudx, dvdx, drdx
798 * dPdy = dudy, dvdy, drdy
800 * Load up these values:
801 * - dudx dudy dvdx dvdy drdx drdy
802 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
804 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
805 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx);
809 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy);
814 inst = emit(FS_OPCODE_TXD, dst);
818 assert(!"GLSL 1.30 features unsupported");
821 inst->base_mrf = base_mrf;
823 inst->header_present = header_present;
826 fail("Message length >11 disallowed by hardware\n");
833 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
838 int reg_width = c->dispatch_width / 8;
839 bool header_present = false;
842 /* The offsets set up by the ir_texture visitor are in the
843 * m1 header, so we can't go headerless.
845 header_present = true;
850 if (ir->shadow_comparitor && ir->op != ir_txd) {
851 this->result = reg_undef;
852 ir->shadow_comparitor->accept(this);
853 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
857 /* Set up the LOD info */
862 this->result = reg_undef;
863 ir->lod_info.bias->accept(this);
864 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
868 this->result = reg_undef;
869 ir->lod_info.lod->accept(this);
870 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
874 if (c->dispatch_width == 16)
875 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
877 this->result = reg_undef;
878 ir->lod_info.grad.dPdx->accept(this);
879 fs_reg dPdx = this->result;
881 this->result = reg_undef;
882 ir->lod_info.grad.dPdy->accept(this);
883 fs_reg dPdy = this->result;
885 /* Load dPdx and the coordinate together:
886 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
888 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
889 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
891 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler))
892 inst->saturate = true;
893 coordinate.reg_offset++;
896 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdx);
900 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), dPdy);
907 assert(!"GLSL 1.30 features unsupported");
911 /* Set up the coordinate (except for TXD where it was done earlier) */
912 if (ir->op != ir_txd) {
913 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
914 fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
916 if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler))
917 inst->saturate = true;
918 coordinate.reg_offset++;
923 /* Generate the SEND */
924 fs_inst *inst = NULL;
926 case ir_tex: inst = emit(FS_OPCODE_TEX, dst); break;
927 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
928 case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break;
929 case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break;
930 case ir_txf: assert(!"TXF unsupported.");
932 inst->base_mrf = base_mrf;
934 inst->header_present = header_present;
937 fail("Message length >11 disallowed by hardware\n");
944 fs_visitor::visit(ir_texture *ir)
946 fs_inst *inst = NULL;
948 int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base);
949 sampler = fp->Base.SamplerUnits[sampler];
951 /* Our hardware doesn't have a sample_d_c message, so shadow compares
952 * for textureGrad/TXD need to be emulated with instructions.
954 bool hw_compare_supported = ir->op != ir_txd;
955 if (ir->shadow_comparitor && !hw_compare_supported) {
956 assert(c->key.compare_funcs[sampler] != GL_NONE);
957 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */
958 if (c->key.compare_funcs[sampler] == GL_ALWAYS)
959 return swizzle_result(ir, fs_reg(1.0f), sampler);
960 else if (c->key.compare_funcs[sampler] == GL_NEVER)
961 return swizzle_result(ir, fs_reg(0.0f), sampler);
964 this->result = reg_undef;
965 ir->coordinate->accept(this);
966 fs_reg coordinate = this->result;
968 if (ir->offset != NULL) {
969 ir_constant *offset = ir->offset->as_constant();
970 assert(offset != NULL);
972 signed char offsets[3];
973 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++)
974 offsets[i] = (signed char) offset->value.i[i];
976 /* Combine all three offsets into a single unsigned dword:
978 * bits 11:8 - U Offset (X component)
979 * bits 7:4 - V Offset (Y component)
980 * bits 3:0 - R Offset (Z component)
982 unsigned offset_bits = 0;
983 for (unsigned i = 0; i < ir->offset->type->vector_elements; i++) {
984 const unsigned shift = 4 * (2 - i);
985 offset_bits |= (offsets[i] << shift) & (0xF << shift);
988 /* Explicitly set up the message header by copying g0 to msg reg m1. */
989 emit(BRW_OPCODE_MOV, fs_reg(MRF, 1, BRW_REGISTER_TYPE_UD),
990 fs_reg(GRF, 0, BRW_REGISTER_TYPE_UD));
992 /* Then set the offset bits in DWord 2 of the message header. */
994 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, 1, 2),
995 BRW_REGISTER_TYPE_UD)),
996 fs_reg(brw_imm_uw(offset_bits)));
999 /* Should be lowered by do_lower_texture_projection */
1000 assert(!ir->projector);
1002 /* The 965 requires the EU to do the normalization of GL rectangle
1003 * texture coordinates. We use the program parameter state
1004 * tracking to get the scaling factor.
1006 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) {
1007 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters;
1008 int tokens[STATE_LENGTH] = {
1010 STATE_TEXRECT_SCALE,
1016 if (c->dispatch_width == 16) {
1017 fail("rectangle scale uniform setup not supported on 16-wide\n");
1018 this->result = fs_reg(this, ir->type);
1022 c->prog_data.param_convert[c->prog_data.nr_params] =
1024 c->prog_data.param_convert[c->prog_data.nr_params + 1] =
1027 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1028 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1029 GLuint index = _mesa_add_state_reference(params,
1030 (gl_state_index *)tokens);
1032 this->param_index[c->prog_data.nr_params] = index;
1033 this->param_offset[c->prog_data.nr_params] = 0;
1034 c->prog_data.nr_params++;
1035 this->param_index[c->prog_data.nr_params] = index;
1036 this->param_offset[c->prog_data.nr_params] = 1;
1037 c->prog_data.nr_params++;
1039 fs_reg dst = fs_reg(this, ir->coordinate->type);
1040 fs_reg src = coordinate;
1043 emit(BRW_OPCODE_MUL, dst, src, scale_x);
1046 emit(BRW_OPCODE_MUL, dst, src, scale_y);
1049 /* Writemasking doesn't eliminate channels on SIMD8 texture
1050 * samples, so don't worry about them.
1052 fs_reg dst = fs_reg(this, glsl_type::vec4_type);
1054 if (intel->gen >= 7) {
1055 inst = emit_texture_gen7(ir, dst, coordinate, sampler);
1056 } else if (intel->gen >= 5) {
1057 inst = emit_texture_gen5(ir, dst, coordinate, sampler);
1059 inst = emit_texture_gen4(ir, dst, coordinate, sampler);
1062 /* If there's an offset, we already set up m1. To avoid the implied move,
1063 * use the null register. Otherwise, we want an implied move from g0.
1065 if (ir->offset != NULL || !inst->header_present)
1066 inst->src[0] = reg_undef;
1068 inst->src[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW));
1070 inst->sampler = sampler;
1072 if (ir->shadow_comparitor) {
1073 if (hw_compare_supported) {
1074 inst->shadow_compare = true;
1076 this->result = reg_undef;
1077 ir->shadow_comparitor->accept(this);
1078 fs_reg ref = this->result;
1081 dst = fs_reg(this, glsl_type::vec4_type);
1083 /* FINISHME: This needs to be done pre-filtering. */
1085 uint32_t conditional = 0;
1086 switch (c->key.compare_funcs[sampler]) {
1087 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */
1088 case GL_LESS: conditional = BRW_CONDITIONAL_L; break;
1089 case GL_GREATER: conditional = BRW_CONDITIONAL_G; break;
1090 case GL_LEQUAL: conditional = BRW_CONDITIONAL_LE; break;
1091 case GL_GEQUAL: conditional = BRW_CONDITIONAL_GE; break;
1092 case GL_EQUAL: conditional = BRW_CONDITIONAL_EQ; break;
1093 case GL_NOTEQUAL: conditional = BRW_CONDITIONAL_NEQ; break;
1094 default: assert(!"Should not get here: bad shadow compare function");
1097 /* Use conditional moves to load 0 or 1 as the result */
1098 this->current_annotation = "manual shadow comparison";
1099 for (int i = 0; i < 4; i++) {
1100 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(0.0f));
1102 inst = emit(BRW_OPCODE_CMP, reg_null_f, ref, value);
1103 inst->conditional_mod = conditional;
1105 inst = emit(BRW_OPCODE_MOV, dst, fs_reg(1.0f));
1106 inst->predicated = true;
1115 swizzle_result(ir, dst, sampler);
1119 * Swizzle the result of a texture result. This is necessary for
1120 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1123 fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
1125 this->result = orig_val;
1127 if (ir->type == glsl_type::float_type) {
1128 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1129 assert(ir->sampler->type->sampler_shadow);
1130 } else if (c->key.tex_swizzles[sampler] != SWIZZLE_NOOP) {
1131 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
1133 for (int i = 0; i < 4; i++) {
1134 int swiz = GET_SWZ(c->key.tex_swizzles[sampler], i);
1135 fs_reg l = swizzled_result;
1138 if (swiz == SWIZZLE_ZERO) {
1139 emit(BRW_OPCODE_MOV, l, fs_reg(0.0f));
1140 } else if (swiz == SWIZZLE_ONE) {
1141 emit(BRW_OPCODE_MOV, l, fs_reg(1.0f));
1143 fs_reg r = orig_val;
1144 r.reg_offset += GET_SWZ(c->key.tex_swizzles[sampler], i);
1145 emit(BRW_OPCODE_MOV, l, r);
1148 this->result = swizzled_result;
1153 fs_visitor::visit(ir_swizzle *ir)
1155 this->result = reg_undef;
1156 ir->val->accept(this);
1157 fs_reg val = this->result;
1159 if (ir->type->vector_elements == 1) {
1160 this->result.reg_offset += ir->mask.x;
1164 fs_reg result = fs_reg(this, ir->type);
1165 this->result = result;
1167 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1168 fs_reg channel = val;
1186 channel.reg_offset += swiz;
1187 emit(BRW_OPCODE_MOV, result, channel);
1188 result.reg_offset++;
1193 fs_visitor::visit(ir_discard *ir)
1195 assert(ir->condition == NULL); /* FINISHME */
1197 emit(FS_OPCODE_DISCARD);
1198 kill_emitted = true;
1202 fs_visitor::visit(ir_constant *ir)
1204 /* Set this->result to reg at the bottom of the function because some code
1205 * paths will cause this visitor to be applied to other fields. This will
1206 * cause the value stored in this->result to be modified.
1208 * Make reg constant so that it doesn't get accidentally modified along the
1209 * way. Yes, I actually had this problem. :(
1211 const fs_reg reg(this, ir->type);
1212 fs_reg dst_reg = reg;
1214 if (ir->type->is_array()) {
1215 const unsigned size = type_size(ir->type->fields.array);
1217 for (unsigned i = 0; i < ir->type->length; i++) {
1218 this->result = reg_undef;
1219 ir->array_elements[i]->accept(this);
1220 fs_reg src_reg = this->result;
1222 dst_reg.type = src_reg.type;
1223 for (unsigned j = 0; j < size; j++) {
1224 emit(BRW_OPCODE_MOV, dst_reg, src_reg);
1225 src_reg.reg_offset++;
1226 dst_reg.reg_offset++;
1229 } else if (ir->type->is_record()) {
1230 foreach_list(node, &ir->components) {
1231 ir_instruction *const field = (ir_instruction *) node;
1232 const unsigned size = type_size(field->type);
1234 this->result = reg_undef;
1235 field->accept(this);
1236 fs_reg src_reg = this->result;
1238 dst_reg.type = src_reg.type;
1239 for (unsigned j = 0; j < size; j++) {
1240 emit(BRW_OPCODE_MOV, dst_reg, src_reg);
1241 src_reg.reg_offset++;
1242 dst_reg.reg_offset++;
1246 const unsigned size = type_size(ir->type);
1248 for (unsigned i = 0; i < size; i++) {
1249 switch (ir->type->base_type) {
1250 case GLSL_TYPE_FLOAT:
1251 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i]));
1253 case GLSL_TYPE_UINT:
1254 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i]));
1257 emit(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i]));
1259 case GLSL_TYPE_BOOL:
1260 emit(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i]));
1263 assert(!"Non-float/uint/int/bool constant");
1265 dst_reg.reg_offset++;
1273 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1275 ir_expression *expr = ir->as_expression();
1281 assert(expr->get_num_operands() <= 2);
1282 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1283 assert(expr->operands[i]->type->is_scalar());
1285 this->result = reg_undef;
1286 expr->operands[i]->accept(this);
1287 op[i] = this->result;
1290 switch (expr->operation) {
1291 case ir_unop_logic_not:
1292 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1));
1293 inst->conditional_mod = BRW_CONDITIONAL_Z;
1296 case ir_binop_logic_xor:
1297 inst = emit(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]);
1298 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1301 case ir_binop_logic_or:
1302 inst = emit(BRW_OPCODE_OR, reg_null_d, op[0], op[1]);
1303 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1306 case ir_binop_logic_and:
1307 inst = emit(BRW_OPCODE_AND, reg_null_d, op[0], op[1]);
1308 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1312 if (intel->gen >= 6) {
1313 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0.0f));
1315 inst = emit(BRW_OPCODE_MOV, reg_null_f, op[0]);
1317 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1321 if (intel->gen >= 6) {
1322 inst = emit(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0));
1324 inst = emit(BRW_OPCODE_MOV, reg_null_d, op[0]);
1326 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1329 case ir_binop_greater:
1330 case ir_binop_gequal:
1332 case ir_binop_lequal:
1333 case ir_binop_equal:
1334 case ir_binop_all_equal:
1335 case ir_binop_nequal:
1336 case ir_binop_any_nequal:
1337 inst = emit(BRW_OPCODE_CMP, reg_null_cmp, op[0], op[1]);
1338 inst->conditional_mod =
1339 brw_conditional_for_comparison(expr->operation);
1343 assert(!"not reached");
1344 fail("bad cond code\n");
1350 this->result = reg_undef;
1353 if (intel->gen >= 6) {
1354 fs_inst *inst = emit(BRW_OPCODE_AND, reg_null_d, this->result, fs_reg(1));
1355 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1357 fs_inst *inst = emit(BRW_OPCODE_MOV, reg_null_d, this->result);
1358 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1363 * Emit a gen6 IF statement with the comparison folded into the IF
1367 fs_visitor::emit_if_gen6(ir_if *ir)
1369 ir_expression *expr = ir->condition->as_expression();
1376 assert(expr->get_num_operands() <= 2);
1377 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1378 assert(expr->operands[i]->type->is_scalar());
1380 this->result = reg_undef;
1381 expr->operands[i]->accept(this);
1382 op[i] = this->result;
1385 switch (expr->operation) {
1386 case ir_unop_logic_not:
1387 inst = emit(BRW_OPCODE_IF, temp, op[0], fs_reg(0));
1388 inst->conditional_mod = BRW_CONDITIONAL_Z;
1391 case ir_binop_logic_xor:
1392 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]);
1393 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1396 case ir_binop_logic_or:
1397 temp = fs_reg(this, glsl_type::bool_type);
1398 emit(BRW_OPCODE_OR, temp, op[0], op[1]);
1399 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0));
1400 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1403 case ir_binop_logic_and:
1404 temp = fs_reg(this, glsl_type::bool_type);
1405 emit(BRW_OPCODE_AND, temp, op[0], op[1]);
1406 inst = emit(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0));
1407 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1411 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
1412 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1416 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0));
1417 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1420 case ir_binop_greater:
1421 case ir_binop_gequal:
1423 case ir_binop_lequal:
1424 case ir_binop_equal:
1425 case ir_binop_all_equal:
1426 case ir_binop_nequal:
1427 case ir_binop_any_nequal:
1428 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], op[1]);
1429 inst->conditional_mod =
1430 brw_conditional_for_comparison(expr->operation);
1433 assert(!"not reached");
1434 inst = emit(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0));
1435 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1436 fail("bad condition\n");
1442 this->result = reg_undef;
1443 ir->condition->accept(this);
1445 fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0));
1446 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1450 fs_visitor::visit(ir_if *ir)
1454 if (intel->gen < 6 && c->dispatch_width == 16) {
1455 fail("Can't support (non-uniform) control flow on 16-wide\n");
1458 /* Don't point the annotation at the if statement, because then it plus
1459 * the then and else blocks get printed.
1461 this->base_ir = ir->condition;
1463 if (intel->gen == 6) {
1466 emit_bool_to_cond_code(ir->condition);
1468 inst = emit(BRW_OPCODE_IF);
1469 inst->predicated = true;
1472 foreach_iter(exec_list_iterator, iter, ir->then_instructions) {
1473 ir_instruction *ir = (ir_instruction *)iter.get();
1475 this->result = reg_undef;
1479 if (!ir->else_instructions.is_empty()) {
1480 emit(BRW_OPCODE_ELSE);
1482 foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
1483 ir_instruction *ir = (ir_instruction *)iter.get();
1485 this->result = reg_undef;
1490 emit(BRW_OPCODE_ENDIF);
1494 fs_visitor::visit(ir_loop *ir)
1496 fs_reg counter = reg_undef;
1498 if (c->dispatch_width == 16) {
1499 fail("Can't support (non-uniform) control flow on 16-wide\n");
1503 this->base_ir = ir->counter;
1504 ir->counter->accept(this);
1505 counter = *(variable_storage(ir->counter));
1508 this->result = counter;
1510 this->base_ir = ir->from;
1511 this->result = counter;
1512 ir->from->accept(this);
1514 if (!this->result.equals(&counter))
1515 emit(BRW_OPCODE_MOV, counter, this->result);
1519 emit(BRW_OPCODE_DO);
1522 this->base_ir = ir->to;
1523 this->result = reg_undef;
1524 ir->to->accept(this);
1526 fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result);
1527 inst->conditional_mod = brw_conditional_for_comparison(ir->cmp);
1529 inst = emit(BRW_OPCODE_BREAK);
1530 inst->predicated = true;
1533 foreach_iter(exec_list_iterator, iter, ir->body_instructions) {
1534 ir_instruction *ir = (ir_instruction *)iter.get();
1537 this->result = reg_undef;
1541 if (ir->increment) {
1542 this->base_ir = ir->increment;
1543 this->result = reg_undef;
1544 ir->increment->accept(this);
1545 emit(BRW_OPCODE_ADD, counter, counter, this->result);
1548 emit(BRW_OPCODE_WHILE);
1552 fs_visitor::visit(ir_loop_jump *ir)
1555 case ir_loop_jump::jump_break:
1556 emit(BRW_OPCODE_BREAK);
1558 case ir_loop_jump::jump_continue:
1559 emit(BRW_OPCODE_CONTINUE);
1565 fs_visitor::visit(ir_call *ir)
1567 assert(!"FINISHME");
1571 fs_visitor::visit(ir_return *ir)
1573 assert(!"FINISHME");
1577 fs_visitor::visit(ir_function *ir)
1579 /* Ignore function bodies other than main() -- we shouldn't see calls to
1580 * them since they should all be inlined before we get to ir_to_mesa.
1582 if (strcmp(ir->name, "main") == 0) {
1583 const ir_function_signature *sig;
1586 sig = ir->matching_signature(&empty);
1590 foreach_iter(exec_list_iterator, iter, sig->body) {
1591 ir_instruction *ir = (ir_instruction *)iter.get();
1593 this->result = reg_undef;
1600 fs_visitor::visit(ir_function_signature *ir)
1602 assert(!"not reached");
1607 fs_visitor::emit(fs_inst inst)
1609 fs_inst *list_inst = new(mem_ctx) fs_inst;
1612 if (force_uncompressed_stack > 0)
1613 list_inst->force_uncompressed = true;
1614 else if (force_sechalf_stack > 0)
1615 list_inst->force_sechalf = true;
1617 list_inst->annotation = this->current_annotation;
1618 list_inst->ir = this->base_ir;
1620 this->instructions.push_tail(list_inst);
1625 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1627 fs_visitor::emit_dummy_fs()
1629 /* Everyone's favorite color. */
1630 emit(BRW_OPCODE_MOV, fs_reg(MRF, 2), fs_reg(1.0f));
1631 emit(BRW_OPCODE_MOV, fs_reg(MRF, 3), fs_reg(0.0f));
1632 emit(BRW_OPCODE_MOV, fs_reg(MRF, 4), fs_reg(1.0f));
1633 emit(BRW_OPCODE_MOV, fs_reg(MRF, 5), fs_reg(0.0f));
1636 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
1637 write->base_mrf = 0;
1640 /* The register location here is relative to the start of the URB
1641 * data. It will get adjusted to be a real location before
1642 * generate_code() time.
1645 fs_visitor::interp_reg(int location, int channel)
1647 int regnr = urb_setup[location] * 2 + channel / 2;
1648 int stride = (channel & 1) * 4;
1650 assert(urb_setup[location] != -1);
1652 return brw_vec1_grf(regnr, stride);
1655 /** Emits the interpolation for the varying inputs. */
1657 fs_visitor::emit_interpolation_setup_gen4()
1659 this->current_annotation = "compute pixel centers";
1660 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1661 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1662 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1663 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1665 emit(FS_OPCODE_PIXEL_X, this->pixel_x);
1666 emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
1668 this->current_annotation = "compute pixel deltas from v0";
1670 this->delta_x = fs_reg(this, glsl_type::vec2_type);
1671 this->delta_y = this->delta_x;
1672 this->delta_y.reg_offset++;
1674 this->delta_x = fs_reg(this, glsl_type::float_type);
1675 this->delta_y = fs_reg(this, glsl_type::float_type);
1677 emit(BRW_OPCODE_ADD, this->delta_x,
1678 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0))));
1679 emit(BRW_OPCODE_ADD, this->delta_y,
1680 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1))));
1682 this->current_annotation = "compute pos.w and 1/pos.w";
1683 /* Compute wpos.w. It's always in our setup, since it's needed to
1684 * interpolate the other attributes.
1686 this->wpos_w = fs_reg(this, glsl_type::float_type);
1687 emit(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
1688 interp_reg(FRAG_ATTRIB_WPOS, 3));
1689 /* Compute the pixel 1/W value from wpos.w. */
1690 this->pixel_w = fs_reg(this, glsl_type::float_type);
1691 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
1692 this->current_annotation = NULL;
1695 /** Emits the interpolation for the varying inputs. */
1697 fs_visitor::emit_interpolation_setup_gen6()
1699 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1701 /* If the pixel centers end up used, the setup is the same as for gen4. */
1702 this->current_annotation = "compute pixel centers";
1703 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
1704 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
1705 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
1706 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
1707 emit(BRW_OPCODE_ADD,
1709 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1710 fs_reg(brw_imm_v(0x10101010)));
1711 emit(BRW_OPCODE_ADD,
1713 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1714 fs_reg(brw_imm_v(0x11001100)));
1716 /* As of gen6, we can no longer mix float and int sources. We have
1717 * to turn the integer pixel centers into floats for their actual
1720 this->pixel_x = fs_reg(this, glsl_type::float_type);
1721 this->pixel_y = fs_reg(this, glsl_type::float_type);
1722 emit(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x);
1723 emit(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y);
1725 this->current_annotation = "compute pos.w";
1726 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
1727 this->wpos_w = fs_reg(this, glsl_type::float_type);
1728 emit_math(FS_OPCODE_RCP, this->wpos_w, this->pixel_w);
1730 this->delta_x = fs_reg(brw_vec8_grf(2, 0));
1731 this->delta_y = fs_reg(brw_vec8_grf(3, 0));
1733 this->current_annotation = NULL;
1737 fs_visitor::emit_color_write(int index, int first_color_mrf, fs_reg color)
1739 int reg_width = c->dispatch_width / 8;
1742 if (c->dispatch_width == 8 || intel->gen >= 6) {
1743 /* SIMD8 write looks like:
1749 * gen6 SIMD16 DP write looks like:
1759 inst = emit(BRW_OPCODE_MOV,
1760 fs_reg(MRF, first_color_mrf + index * reg_width),
1762 inst->saturate = c->key.clamp_fragment_color;
1764 /* pre-gen6 SIMD16 single source DP write looks like:
1774 if (brw->has_compr4) {
1775 /* By setting the high bit of the MRF register number, we
1776 * indicate that we want COMPR4 mode - instead of doing the
1777 * usual destination + 1 for the second half we get
1780 inst = emit(BRW_OPCODE_MOV,
1781 fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index),
1783 inst->saturate = c->key.clamp_fragment_color;
1785 push_force_uncompressed();
1786 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index),
1788 inst->saturate = c->key.clamp_fragment_color;
1789 pop_force_uncompressed();
1791 push_force_sechalf();
1792 color.sechalf = true;
1793 inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, first_color_mrf + index + 4),
1795 inst->saturate = c->key.clamp_fragment_color;
1796 pop_force_sechalf();
1797 color.sechalf = false;
1803 fs_visitor::emit_fb_writes()
1805 this->current_annotation = "FB write header";
1806 GLboolean header_present = GL_TRUE;
1808 int reg_width = c->dispatch_width / 8;
1810 if (intel->gen >= 6 &&
1811 !this->kill_emitted &&
1812 c->key.nr_color_regions == 1) {
1813 header_present = false;
1816 if (header_present) {
1821 if (c->aa_dest_stencil_reg) {
1822 push_force_uncompressed();
1823 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1824 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0)));
1825 pop_force_uncompressed();
1828 /* Reserve space for color. It'll be filled in per MRT below. */
1830 nr += 4 * reg_width;
1832 if (c->source_depth_to_render_target) {
1833 if (intel->gen == 6 && c->dispatch_width == 16) {
1834 /* For outputting oDepth on gen6, SIMD8 writes have to be
1835 * used. This would require 8-wide moves of each half to
1836 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1837 * Just bail on doing so for now.
1839 fail("Missing support for simd16 depth writes on gen6\n");
1842 if (c->computes_depth) {
1843 /* Hand over gl_FragDepth. */
1844 assert(this->frag_depth);
1845 fs_reg depth = *(variable_storage(this->frag_depth));
1847 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth);
1849 /* Pass through the payload depth. */
1850 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr),
1851 fs_reg(brw_vec8_grf(c->source_depth_reg, 0)));
1856 if (c->dest_depth_reg) {
1857 emit(BRW_OPCODE_MOV, fs_reg(MRF, nr),
1858 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0)));
1862 fs_reg color = reg_undef;
1863 if (this->frag_color)
1864 color = *(variable_storage(this->frag_color));
1865 else if (this->frag_data) {
1866 color = *(variable_storage(this->frag_data));
1867 color.type = BRW_REGISTER_TYPE_F;
1870 for (int target = 0; target < c->key.nr_color_regions; target++) {
1871 this->current_annotation = ralloc_asprintf(this->mem_ctx,
1872 "FB write target %d",
1874 if (this->frag_color || this->frag_data) {
1875 for (int i = 0; i < 4; i++) {
1876 emit_color_write(i, color_mrf, color);
1881 if (this->frag_color)
1882 color.reg_offset -= 4;
1884 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
1885 inst->target = target;
1888 if (target == c->key.nr_color_regions - 1)
1890 inst->header_present = header_present;
1893 if (c->key.nr_color_regions == 0) {
1894 if (c->key.alpha_test && (this->frag_color || this->frag_data)) {
1895 /* If the alpha test is enabled but there's no color buffer,
1896 * we still need to send alpha out the pipeline to our null
1899 color.reg_offset += 3;
1900 emit_color_write(3, color_mrf, color);
1903 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
1907 inst->header_present = header_present;
1910 this->current_annotation = NULL;