2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
33 #include <sys/types.h>
35 #include "main/macros.h"
36 #include "main/shaderobj.h"
37 #include "main/uniforms.h"
38 #include "program/prog_parameter.h"
39 #include "program/prog_print.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "../glsl/glsl_types.h"
50 #include "../glsl/ir_print_visitor.h"
52 #define MAX_INSTRUCTION (1 << 30)
55 fs_visitor::type_size(const struct glsl_type *type)
59 switch (type->base_type) {
64 return type->components();
66 return type_size(type->fields.array) * type->length;
67 case GLSL_TYPE_STRUCT:
69 for (i = 0; i < type->length; i++) {
70 size += type_size(type->fields.structure[i].type);
73 case GLSL_TYPE_SAMPLER:
74 /* Samplers take up no register space, since they're baked in at
79 assert(!"not reached");
85 fs_visitor::fail(const char *format, ...)
96 msg = ralloc_vasprintf(mem_ctx, format, va);
98 msg = ralloc_asprintf(mem_ctx, "FS compile failed: %s\n", msg);
100 this->fail_msg = msg;
102 if (INTEL_DEBUG & DEBUG_WM) {
103 fprintf(stderr, "%s", msg);
108 fs_visitor::push_force_uncompressed()
110 force_uncompressed_stack++;
114 fs_visitor::pop_force_uncompressed()
116 force_uncompressed_stack--;
117 assert(force_uncompressed_stack >= 0);
121 fs_visitor::push_force_sechalf()
123 force_sechalf_stack++;
127 fs_visitor::pop_force_sechalf()
129 force_sechalf_stack--;
130 assert(force_sechalf_stack >= 0);
134 * Returns how many MRFs an FS opcode will write over.
136 * Note that this is not the 0 or 1 implied writes in an actual gen
137 * instruction -- the FS opcodes often generate MOVs in addition.
140 fs_visitor::implied_mrf_writes(fs_inst *inst)
145 switch (inst->opcode) {
153 return 1 * c->dispatch_width / 8;
155 return 2 * c->dispatch_width / 8;
161 case FS_OPCODE_FB_WRITE:
163 case FS_OPCODE_PULL_CONSTANT_LOAD:
164 case FS_OPCODE_UNSPILL:
166 case FS_OPCODE_SPILL:
169 assert(!"not reached");
175 fs_visitor::virtual_grf_alloc(int size)
177 if (virtual_grf_array_size <= virtual_grf_next) {
178 if (virtual_grf_array_size == 0)
179 virtual_grf_array_size = 16;
181 virtual_grf_array_size *= 2;
182 virtual_grf_sizes = reralloc(mem_ctx, virtual_grf_sizes, int,
183 virtual_grf_array_size);
185 /* This slot is always unused. */
186 virtual_grf_sizes[0] = 0;
188 virtual_grf_sizes[virtual_grf_next] = size;
189 return virtual_grf_next++;
192 /** Fixed HW reg constructor. */
193 fs_reg::fs_reg(enum register_file file, int hw_reg)
197 this->hw_reg = hw_reg;
198 this->type = BRW_REGISTER_TYPE_F;
201 /** Fixed HW reg constructor. */
202 fs_reg::fs_reg(enum register_file file, int hw_reg, uint32_t type)
206 this->hw_reg = hw_reg;
210 /** Automatic reg constructor. */
211 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
216 this->reg = v->virtual_grf_alloc(v->type_size(type));
217 this->reg_offset = 0;
218 this->type = brw_type_for_base_type(type);
222 fs_visitor::variable_storage(ir_variable *var)
224 return (fs_reg *)hash_table_find(this->variable_ht, var);
228 import_uniforms_callback(const void *key,
232 struct hash_table *dst_ht = (struct hash_table *)closure;
233 const fs_reg *reg = (const fs_reg *)data;
235 if (reg->file != UNIFORM)
238 hash_table_insert(dst_ht, data, key);
241 /* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
242 * This brings in those uniform definitions
245 fs_visitor::import_uniforms(struct hash_table *src_variable_ht)
247 hash_table_call_foreach(src_variable_ht,
248 import_uniforms_callback,
252 /* Our support for uniforms is piggy-backed on the struct
253 * gl_fragment_program, because that's where the values actually
254 * get stored, rather than in some global gl_shader_program uniform
258 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
260 unsigned int offset = 0;
262 if (type->is_matrix()) {
263 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
264 type->vector_elements,
267 for (unsigned int i = 0; i < type->matrix_columns; i++) {
268 offset += setup_uniform_values(loc + offset, column);
274 switch (type->base_type) {
275 case GLSL_TYPE_FLOAT:
279 for (unsigned int i = 0; i < type->vector_elements; i++) {
280 unsigned int param = c->prog_data.nr_params++;
282 assert(param < ARRAY_SIZE(c->prog_data.param));
284 switch (type->base_type) {
285 case GLSL_TYPE_FLOAT:
286 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
289 c->prog_data.param_convert[param] = PARAM_CONVERT_F2U;
292 c->prog_data.param_convert[param] = PARAM_CONVERT_F2I;
295 c->prog_data.param_convert[param] = PARAM_CONVERT_F2B;
298 assert(!"not reached");
299 c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
302 this->param_index[param] = loc;
303 this->param_offset[param] = i;
307 case GLSL_TYPE_STRUCT:
308 for (unsigned int i = 0; i < type->length; i++) {
309 offset += setup_uniform_values(loc + offset,
310 type->fields.structure[i].type);
314 case GLSL_TYPE_ARRAY:
315 for (unsigned int i = 0; i < type->length; i++) {
316 offset += setup_uniform_values(loc + offset, type->fields.array);
320 case GLSL_TYPE_SAMPLER:
321 /* The sampler takes up a slot, but we don't use any values from it. */
325 assert(!"not reached");
331 /* Our support for builtin uniforms is even scarier than non-builtin.
332 * It sits on top of the PROG_STATE_VAR parameters that are
333 * automatically updated from GL context state.
336 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
338 const ir_state_slot *const slots = ir->state_slots;
339 assert(ir->state_slots != NULL);
341 for (unsigned int i = 0; i < ir->num_state_slots; i++) {
342 /* This state reference has already been setup by ir_to_mesa, but we'll
343 * get the same index back here.
345 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
346 (gl_state_index *)slots[i].tokens);
348 /* Add each of the unique swizzles of the element as a parameter.
349 * This'll end up matching the expected layout of the
350 * array/matrix/structure we're trying to fill in.
353 for (unsigned int j = 0; j < 4; j++) {
354 int swiz = GET_SWZ(slots[i].swizzle, j);
355 if (swiz == last_swiz)
359 c->prog_data.param_convert[c->prog_data.nr_params] =
361 this->param_index[c->prog_data.nr_params] = index;
362 this->param_offset[c->prog_data.nr_params] = swiz;
363 c->prog_data.nr_params++;
369 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
371 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
373 bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo;
376 if (ir->pixel_center_integer) {
377 emit(BRW_OPCODE_MOV, wpos, this->pixel_x);
379 emit(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f));
384 if (!flip && ir->pixel_center_integer) {
385 emit(BRW_OPCODE_MOV, wpos, this->pixel_y);
387 fs_reg pixel_y = this->pixel_y;
388 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
391 pixel_y.negate = true;
392 offset += c->key.drawable_height - 1.0;
395 emit(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset));
400 if (intel->gen >= 6) {
401 emit(BRW_OPCODE_MOV, wpos,
402 fs_reg(brw_vec8_grf(c->source_depth_reg, 0)));
404 emit(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
405 interp_reg(FRAG_ATTRIB_WPOS, 2));
409 /* gl_FragCoord.w: Already set up in emit_interpolation */
410 emit(BRW_OPCODE_MOV, wpos, this->wpos_w);
416 fs_visitor::emit_general_interpolation(ir_variable *ir)
418 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
419 /* Interpolation is always in floating point regs. */
420 reg->type = BRW_REGISTER_TYPE_F;
423 unsigned int array_elements;
424 const glsl_type *type;
426 if (ir->type->is_array()) {
427 array_elements = ir->type->length;
428 if (array_elements == 0) {
429 fail("dereferenced array '%s' has length 0\n", ir->name);
431 type = ir->type->fields.array;
437 int location = ir->location;
438 for (unsigned int i = 0; i < array_elements; i++) {
439 for (unsigned int j = 0; j < type->matrix_columns; j++) {
440 if (urb_setup[location] == -1) {
441 /* If there's no incoming setup data for this slot, don't
442 * emit interpolation for it.
444 attr.reg_offset += type->vector_elements;
450 location == FRAG_ATTRIB_COL0 || location == FRAG_ATTRIB_COL1;
452 if (c->key.flat_shade && is_gl_Color) {
453 /* Constant interpolation (flat shading) case. The SF has
454 * handed us defined values in only the constant offset
455 * field of the setup reg.
457 for (unsigned int k = 0; k < type->vector_elements; k++) {
458 struct brw_reg interp = interp_reg(location, k);
459 interp = suboffset(interp, 3);
460 emit(FS_OPCODE_CINTERP, attr, fs_reg(interp));
464 /* Perspective interpolation case. */
465 for (unsigned int k = 0; k < type->vector_elements; k++) {
466 /* FINISHME: At some point we probably want to push
467 * this farther by giving similar treatment to the
468 * other potentially constant components of the
469 * attribute, as well as making brw_vs_constval.c
470 * handle varyings other than gl_TexCoord.
472 if (location >= FRAG_ATTRIB_TEX0 &&
473 location <= FRAG_ATTRIB_TEX7 &&
474 k == 3 && !(c->key.proj_attrib_mask & (1 << location))) {
475 emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
477 struct brw_reg interp = interp_reg(location, k);
478 emit(FS_OPCODE_LINTERP, attr,
479 this->delta_x, this->delta_y, fs_reg(interp));
484 if (intel->gen < 6) {
485 attr.reg_offset -= type->vector_elements;
486 for (unsigned int k = 0; k < type->vector_elements; k++) {
487 emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
500 fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
502 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
504 /* The frontfacing comes in as a bit in the thread payload. */
505 if (intel->gen >= 6) {
506 emit(BRW_OPCODE_ASR, *reg,
507 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
509 emit(BRW_OPCODE_NOT, *reg, *reg);
510 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1));
512 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
513 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
516 fs_inst *inst = emit(BRW_OPCODE_CMP, *reg,
519 inst->conditional_mod = BRW_CONDITIONAL_L;
520 emit(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u));
527 fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
539 assert(!"not reached: bad math opcode");
543 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
544 * might be able to do better by doing execsize = 1 math and then
545 * expanding that result out, but we would need to be careful with
548 * The hardware ignores source modifiers (negate and abs) on math
549 * instructions, so we also move to a temp to set those up.
551 if (intel->gen >= 6 && (src.file == UNIFORM ||
554 fs_reg expanded = fs_reg(this, glsl_type::float_type);
555 emit(BRW_OPCODE_MOV, expanded, src);
559 fs_inst *inst = emit(opcode, dst, src);
561 if (intel->gen < 6) {
563 inst->mlen = c->dispatch_width / 8;
570 fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1)
575 assert(opcode == FS_OPCODE_POW);
577 if (intel->gen >= 6) {
578 /* Can't do hstride == 0 args to gen6 math, so expand it out.
580 * The hardware ignores source modifiers (negate and abs) on math
581 * instructions, so we also move to a temp to set those up.
583 if (src0.file == UNIFORM || src0.abs || src0.negate) {
584 fs_reg expanded = fs_reg(this, glsl_type::float_type);
585 emit(BRW_OPCODE_MOV, expanded, src0);
589 if (src1.file == UNIFORM || src1.abs || src1.negate) {
590 fs_reg expanded = fs_reg(this, glsl_type::float_type);
591 emit(BRW_OPCODE_MOV, expanded, src1);
595 inst = emit(opcode, dst, src0, src1);
597 emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1);
598 inst = emit(opcode, dst, src0, reg_null_f);
600 inst->base_mrf = base_mrf;
601 inst->mlen = 2 * c->dispatch_width / 8;
607 * To be called after the last _mesa_add_state_reference() call, to
608 * set up prog_data.param[] for assign_curb_setup() and
609 * setup_pull_constants().
612 fs_visitor::setup_paramvalues_refs()
614 if (c->dispatch_width != 8)
617 /* Set up the pointers to ParamValues now that that array is finalized. */
618 for (unsigned int i = 0; i < c->prog_data.nr_params; i++) {
619 c->prog_data.param[i] =
620 (const float *)fp->Base.Parameters->ParameterValues[this->param_index[i]] +
621 this->param_offset[i];
626 fs_visitor::assign_curb_setup()
628 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
629 if (c->dispatch_width == 8) {
630 c->prog_data.first_curbe_grf = c->nr_payload_regs;
632 c->prog_data.first_curbe_grf_16 = c->nr_payload_regs;
635 /* Map the offsets in the UNIFORM file to fixed HW regs. */
636 foreach_list(node, &this->instructions) {
637 fs_inst *inst = (fs_inst *)node;
639 for (unsigned int i = 0; i < 3; i++) {
640 if (inst->src[i].file == UNIFORM) {
641 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
642 struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs +
646 inst->src[i].file = FIXED_HW_REG;
647 inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
654 fs_visitor::calculate_urb_setup()
656 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
661 /* Figure out where each of the incoming setup attributes lands. */
662 if (intel->gen >= 6) {
663 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
664 if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
665 urb_setup[i] = urb_next++;
669 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
670 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
671 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
674 if (i >= VERT_RESULT_VAR0)
675 fp_index = i - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
676 else if (i <= VERT_RESULT_TEX7)
682 urb_setup[fp_index] = urb_next++;
687 /* Each attribute is 4 setup channels, each of which is half a reg. */
688 c->prog_data.urb_read_length = urb_next * 2;
692 fs_visitor::assign_urb_setup()
694 int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length;
696 /* Offset all the urb_setup[] index by the actual position of the
697 * setup regs, now that the location of the constants has been chosen.
699 foreach_list(node, &this->instructions) {
700 fs_inst *inst = (fs_inst *)node;
702 if (inst->opcode == FS_OPCODE_LINTERP) {
703 assert(inst->src[2].file == FIXED_HW_REG);
704 inst->src[2].fixed_hw_reg.nr += urb_start;
707 if (inst->opcode == FS_OPCODE_CINTERP) {
708 assert(inst->src[0].file == FIXED_HW_REG);
709 inst->src[0].fixed_hw_reg.nr += urb_start;
713 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
717 * Split large virtual GRFs into separate components if we can.
719 * This is mostly duplicated with what brw_fs_vector_splitting does,
720 * but that's really conservative because it's afraid of doing
721 * splitting that doesn't result in real progress after the rest of
722 * the optimization phases, which would cause infinite looping in
723 * optimization. We can do it once here, safely. This also has the
724 * opportunity to split interpolated values, or maybe even uniforms,
725 * which we don't have at the IR level.
727 * We want to split, because virtual GRFs are what we register
728 * allocate and spill (due to contiguousness requirements for some
729 * instructions), and they're what we naturally generate in the
730 * codegen process, but most virtual GRFs don't actually need to be
731 * contiguous sets of GRFs. If we split, we'll end up with reduced
732 * live intervals and better dead code elimination and coalescing.
735 fs_visitor::split_virtual_grfs()
737 int num_vars = this->virtual_grf_next;
738 bool split_grf[num_vars];
739 int new_virtual_grf[num_vars];
741 /* Try to split anything > 0 sized. */
742 for (int i = 0; i < num_vars; i++) {
743 if (this->virtual_grf_sizes[i] != 1)
746 split_grf[i] = false;
750 /* PLN opcodes rely on the delta_xy being contiguous. */
751 split_grf[this->delta_x.reg] = false;
754 foreach_list(node, &this->instructions) {
755 fs_inst *inst = (fs_inst *)node;
757 /* Texturing produces 4 contiguous registers, so no splitting. */
758 if (inst->is_tex()) {
759 split_grf[inst->dst.reg] = false;
763 /* Allocate new space for split regs. Note that the virtual
764 * numbers will be contiguous.
766 for (int i = 0; i < num_vars; i++) {
768 new_virtual_grf[i] = virtual_grf_alloc(1);
769 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
770 int reg = virtual_grf_alloc(1);
771 assert(reg == new_virtual_grf[i] + j - 1);
774 this->virtual_grf_sizes[i] = 1;
778 foreach_list(node, &this->instructions) {
779 fs_inst *inst = (fs_inst *)node;
781 if (inst->dst.file == GRF &&
782 split_grf[inst->dst.reg] &&
783 inst->dst.reg_offset != 0) {
784 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
785 inst->dst.reg_offset - 1);
786 inst->dst.reg_offset = 0;
788 for (int i = 0; i < 3; i++) {
789 if (inst->src[i].file == GRF &&
790 split_grf[inst->src[i].reg] &&
791 inst->src[i].reg_offset != 0) {
792 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
793 inst->src[i].reg_offset - 1);
794 inst->src[i].reg_offset = 0;
798 this->live_intervals_valid = false;
802 * Choose accesses from the UNIFORM file to demote to using the pull
805 * We allow a fragment shader to have more than the specified minimum
806 * maximum number of fragment shader uniform components (64). If
807 * there are too many of these, they'd fill up all of register space.
808 * So, this will push some of them out to the pull constant buffer and
809 * update the program to load them.
812 fs_visitor::setup_pull_constants()
814 /* Only allow 16 registers (128 uniform components) as push constants. */
815 unsigned int max_uniform_components = 16 * 8;
816 if (c->prog_data.nr_params <= max_uniform_components)
819 if (c->dispatch_width == 16) {
820 fail("Pull constants not supported in 16-wide\n");
824 /* Just demote the end of the list. We could probably do better
825 * here, demoting things that are rarely used in the program first.
827 int pull_uniform_base = max_uniform_components;
828 int pull_uniform_count = c->prog_data.nr_params - pull_uniform_base;
830 foreach_list(node, &this->instructions) {
831 fs_inst *inst = (fs_inst *)node;
833 for (int i = 0; i < 3; i++) {
834 if (inst->src[i].file != UNIFORM)
837 int uniform_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
838 if (uniform_nr < pull_uniform_base)
841 fs_reg dst = fs_reg(this, glsl_type::float_type);
842 fs_inst *pull = new(mem_ctx) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD,
844 pull->offset = ((uniform_nr - pull_uniform_base) * 4) & ~15;
846 pull->annotation = inst->annotation;
850 inst->insert_before(pull);
852 inst->src[i].file = GRF;
853 inst->src[i].reg = dst.reg;
854 inst->src[i].reg_offset = 0;
855 inst->src[i].smear = (uniform_nr - pull_uniform_base) & 3;
859 for (int i = 0; i < pull_uniform_count; i++) {
860 c->prog_data.pull_param[i] = c->prog_data.param[pull_uniform_base + i];
861 c->prog_data.pull_param_convert[i] =
862 c->prog_data.param_convert[pull_uniform_base + i];
864 c->prog_data.nr_params -= pull_uniform_count;
865 c->prog_data.nr_pull_params = pull_uniform_count;
869 fs_visitor::calculate_live_intervals()
871 int num_vars = this->virtual_grf_next;
872 int *def = ralloc_array(mem_ctx, int, num_vars);
873 int *use = ralloc_array(mem_ctx, int, num_vars);
877 if (this->live_intervals_valid)
880 for (int i = 0; i < num_vars; i++) {
881 def[i] = MAX_INSTRUCTION;
886 foreach_list(node, &this->instructions) {
887 fs_inst *inst = (fs_inst *)node;
889 if (inst->opcode == BRW_OPCODE_DO) {
890 if (loop_depth++ == 0)
892 } else if (inst->opcode == BRW_OPCODE_WHILE) {
895 if (loop_depth == 0) {
896 /* Patches up the use of vars marked for being live across
899 for (int i = 0; i < num_vars; i++) {
900 if (use[i] == loop_start) {
906 for (unsigned int i = 0; i < 3; i++) {
907 if (inst->src[i].file == GRF && inst->src[i].reg != 0) {
908 int reg = inst->src[i].reg;
913 def[reg] = MIN2(loop_start, def[reg]);
914 use[reg] = loop_start;
916 /* Nobody else is going to go smash our start to
917 * later in the loop now, because def[reg] now
918 * points before the bb header.
923 if (inst->dst.file == GRF && inst->dst.reg != 0) {
924 int reg = inst->dst.reg;
927 def[reg] = MIN2(def[reg], ip);
929 def[reg] = MIN2(def[reg], loop_start);
937 ralloc_free(this->virtual_grf_def);
938 ralloc_free(this->virtual_grf_use);
939 this->virtual_grf_def = def;
940 this->virtual_grf_use = use;
942 this->live_intervals_valid = true;
946 * Attempts to move immediate constants into the immediate
947 * constant slot of following instructions.
949 * Immediate constants are a bit tricky -- they have to be in the last
950 * operand slot, you can't do abs/negate on them,
954 fs_visitor::propagate_constants()
956 bool progress = false;
958 calculate_live_intervals();
960 foreach_list(node, &this->instructions) {
961 fs_inst *inst = (fs_inst *)node;
963 if (inst->opcode != BRW_OPCODE_MOV ||
965 inst->dst.file != GRF || inst->src[0].file != IMM ||
966 inst->dst.type != inst->src[0].type ||
967 (c->dispatch_width == 16 &&
968 (inst->force_uncompressed || inst->force_sechalf)))
971 /* Don't bother with cases where we should have had the
972 * operation on the constant folded in GLSL already.
977 /* Found a move of a constant to a GRF. Find anything else using the GRF
978 * before it's written, and replace it with the constant if we can.
980 for (fs_inst *scan_inst = (fs_inst *)inst->next;
981 !scan_inst->is_tail_sentinel();
982 scan_inst = (fs_inst *)scan_inst->next) {
983 if (scan_inst->opcode == BRW_OPCODE_DO ||
984 scan_inst->opcode == BRW_OPCODE_WHILE ||
985 scan_inst->opcode == BRW_OPCODE_ELSE ||
986 scan_inst->opcode == BRW_OPCODE_ENDIF) {
990 for (int i = 2; i >= 0; i--) {
991 if (scan_inst->src[i].file != GRF ||
992 scan_inst->src[i].reg != inst->dst.reg ||
993 scan_inst->src[i].reg_offset != inst->dst.reg_offset)
996 /* Don't bother with cases where we should have had the
997 * operation on the constant folded in GLSL already.
999 if (scan_inst->src[i].negate || scan_inst->src[i].abs)
1002 switch (scan_inst->opcode) {
1003 case BRW_OPCODE_MOV:
1004 scan_inst->src[i] = inst->src[0];
1008 case BRW_OPCODE_MUL:
1009 case BRW_OPCODE_ADD:
1011 scan_inst->src[i] = inst->src[0];
1013 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1014 /* Fit this constant in by commuting the operands */
1015 scan_inst->src[0] = scan_inst->src[1];
1016 scan_inst->src[1] = inst->src[0];
1021 case BRW_OPCODE_CMP:
1023 scan_inst->src[i] = inst->src[0];
1025 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1028 new_cmod = brw_swap_cmod(scan_inst->conditional_mod);
1029 if (new_cmod != ~0u) {
1030 /* Fit this constant in by swapping the operands and
1033 scan_inst->src[0] = scan_inst->src[1];
1034 scan_inst->src[1] = inst->src[0];
1035 scan_inst->conditional_mod = new_cmod;
1041 case BRW_OPCODE_SEL:
1043 scan_inst->src[i] = inst->src[0];
1045 } else if (i == 0 && scan_inst->src[1].file != IMM) {
1046 scan_inst->src[0] = scan_inst->src[1];
1047 scan_inst->src[1] = inst->src[0];
1049 /* If this was predicated, flipping operands means
1050 * we also need to flip the predicate.
1052 if (scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) {
1053 scan_inst->predicate_inverse =
1054 !scan_inst->predicate_inverse;
1061 /* The hardware doesn't do math on immediate values
1062 * (because why are you doing that, seriously?), but
1063 * the correct answer is to just constant fold it
1067 if (inst->src[0].imm.f != 0.0f) {
1068 scan_inst->opcode = BRW_OPCODE_MOV;
1069 scan_inst->src[0] = inst->src[0];
1070 scan_inst->src[0].imm.f = 1.0f / scan_inst->src[0].imm.f;
1077 if (scan_inst->dst.file == GRF &&
1078 scan_inst->dst.reg == inst->dst.reg &&
1079 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
1080 scan_inst->is_tex())) {
1087 this->live_intervals_valid = false;
1094 * Attempts to move immediate constants into the immediate
1095 * constant slot of following instructions.
1097 * Immediate constants are a bit tricky -- they have to be in the last
1098 * operand slot, you can't do abs/negate on them,
1102 fs_visitor::opt_algebraic()
1104 bool progress = false;
1106 calculate_live_intervals();
1108 foreach_list(node, &this->instructions) {
1109 fs_inst *inst = (fs_inst *)node;
1111 switch (inst->opcode) {
1112 case BRW_OPCODE_MUL:
1113 if (inst->src[1].file != IMM)
1117 if (inst->src[1].type == BRW_REGISTER_TYPE_F &&
1118 inst->src[1].imm.f == 1.0) {
1119 inst->opcode = BRW_OPCODE_MOV;
1120 inst->src[1] = reg_undef;
1133 * Must be called after calculate_live_intervales() to remove unused
1134 * writes to registers -- register allocation will fail otherwise
1135 * because something deffed but not used won't be considered to
1136 * interfere with other regs.
1139 fs_visitor::dead_code_eliminate()
1141 bool progress = false;
1144 calculate_live_intervals();
1146 foreach_list_safe(node, &this->instructions) {
1147 fs_inst *inst = (fs_inst *)node;
1149 if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
1158 live_intervals_valid = false;
1164 fs_visitor::register_coalesce()
1166 bool progress = false;
1170 foreach_list_safe(node, &this->instructions) {
1171 fs_inst *inst = (fs_inst *)node;
1173 /* Make sure that we dominate the instructions we're going to
1174 * scan for interfering with our coalescing, or we won't have
1175 * scanned enough to see if anything interferes with our
1176 * coalescing. We don't dominate the following instructions if
1177 * we're in a loop or an if block.
1179 switch (inst->opcode) {
1183 case BRW_OPCODE_WHILE:
1189 case BRW_OPCODE_ENDIF:
1193 if (loop_depth || if_depth)
1196 if (inst->opcode != BRW_OPCODE_MOV ||
1199 inst->dst.file != GRF || (inst->src[0].file != GRF &&
1200 inst->src[0].file != UNIFORM)||
1201 inst->dst.type != inst->src[0].type)
1204 bool has_source_modifiers = inst->src[0].abs || inst->src[0].negate;
1206 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
1207 * them: check for no writes to either one until the exit of the
1210 bool interfered = false;
1212 for (fs_inst *scan_inst = (fs_inst *)inst->next;
1213 !scan_inst->is_tail_sentinel();
1214 scan_inst = (fs_inst *)scan_inst->next) {
1215 if (scan_inst->dst.file == GRF) {
1216 if (scan_inst->dst.reg == inst->dst.reg &&
1217 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
1218 scan_inst->is_tex())) {
1222 if (inst->src[0].file == GRF &&
1223 scan_inst->dst.reg == inst->src[0].reg &&
1224 (scan_inst->dst.reg_offset == inst->src[0].reg_offset ||
1225 scan_inst->is_tex())) {
1231 /* The gen6 MATH instruction can't handle source modifiers or
1232 * unusual register regions, so avoid coalescing those for
1233 * now. We should do something more specific.
1235 if (intel->gen >= 6 &&
1236 scan_inst->is_math() &&
1237 (has_source_modifiers || inst->src[0].file == UNIFORM)) {
1246 /* Rewrite the later usage to point at the source of the move to
1249 for (fs_inst *scan_inst = inst;
1250 !scan_inst->is_tail_sentinel();
1251 scan_inst = (fs_inst *)scan_inst->next) {
1252 for (int i = 0; i < 3; i++) {
1253 if (scan_inst->src[i].file == GRF &&
1254 scan_inst->src[i].reg == inst->dst.reg &&
1255 scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
1256 fs_reg new_src = inst->src[0];
1257 new_src.negate ^= scan_inst->src[i].negate;
1258 new_src.abs |= scan_inst->src[i].abs;
1259 scan_inst->src[i] = new_src;
1269 live_intervals_valid = false;
1276 fs_visitor::compute_to_mrf()
1278 bool progress = false;
1281 calculate_live_intervals();
1283 foreach_list_safe(node, &this->instructions) {
1284 fs_inst *inst = (fs_inst *)node;
1289 if (inst->opcode != BRW_OPCODE_MOV ||
1291 inst->dst.file != MRF || inst->src[0].file != GRF ||
1292 inst->dst.type != inst->src[0].type ||
1293 inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
1296 /* Work out which hardware MRF registers are written by this
1299 int mrf_low = inst->dst.hw_reg & ~BRW_MRF_COMPR4;
1301 if (inst->dst.hw_reg & BRW_MRF_COMPR4) {
1302 mrf_high = mrf_low + 4;
1303 } else if (c->dispatch_width == 16 &&
1304 (!inst->force_uncompressed && !inst->force_sechalf)) {
1305 mrf_high = mrf_low + 1;
1310 /* Can't compute-to-MRF this GRF if someone else was going to
1313 if (this->virtual_grf_use[inst->src[0].reg] > ip)
1316 /* Found a move of a GRF to a MRF. Let's see if we can go
1317 * rewrite the thing that made this GRF to write into the MRF.
1320 for (scan_inst = (fs_inst *)inst->prev;
1321 scan_inst->prev != NULL;
1322 scan_inst = (fs_inst *)scan_inst->prev) {
1323 if (scan_inst->dst.file == GRF &&
1324 scan_inst->dst.reg == inst->src[0].reg) {
1325 /* Found the last thing to write our reg we want to turn
1326 * into a compute-to-MRF.
1329 if (scan_inst->is_tex()) {
1330 /* texturing writes several continuous regs, so we can't
1331 * compute-to-mrf that.
1336 /* If it's predicated, it (probably) didn't populate all
1337 * the channels. We might be able to rewrite everything
1338 * that writes that reg, but it would require smarter
1339 * tracking to delay the rewriting until complete success.
1341 if (scan_inst->predicated)
1344 /* If it's half of register setup and not the same half as
1345 * our MOV we're trying to remove, bail for now.
1347 if (scan_inst->force_uncompressed != inst->force_uncompressed ||
1348 scan_inst->force_sechalf != inst->force_sechalf) {
1352 /* SEND instructions can't have MRF as a destination. */
1353 if (scan_inst->mlen)
1356 if (intel->gen >= 6) {
1357 /* gen6 math instructions must have the destination be
1358 * GRF, so no compute-to-MRF for them.
1360 if (scan_inst->is_math()) {
1365 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
1366 /* Found the creator of our MRF's source value. */
1367 scan_inst->dst.file = MRF;
1368 scan_inst->dst.hw_reg = inst->dst.hw_reg;
1369 scan_inst->saturate |= inst->saturate;
1376 /* We don't handle flow control here. Most computation of
1377 * values that end up in MRFs are shortly before the MRF
1380 if (scan_inst->opcode == BRW_OPCODE_DO ||
1381 scan_inst->opcode == BRW_OPCODE_WHILE ||
1382 scan_inst->opcode == BRW_OPCODE_ELSE ||
1383 scan_inst->opcode == BRW_OPCODE_ENDIF) {
1387 /* You can't read from an MRF, so if someone else reads our
1388 * MRF's source GRF that we wanted to rewrite, that stops us.
1390 bool interfered = false;
1391 for (int i = 0; i < 3; i++) {
1392 if (scan_inst->src[i].file == GRF &&
1393 scan_inst->src[i].reg == inst->src[0].reg &&
1394 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
1401 if (scan_inst->dst.file == MRF) {
1402 /* If somebody else writes our MRF here, we can't
1403 * compute-to-MRF before that.
1405 int scan_mrf_low = scan_inst->dst.hw_reg & ~BRW_MRF_COMPR4;
1408 if (scan_inst->dst.hw_reg & BRW_MRF_COMPR4) {
1409 scan_mrf_high = scan_mrf_low + 4;
1410 } else if (c->dispatch_width == 16 &&
1411 (!scan_inst->force_uncompressed &&
1412 !scan_inst->force_sechalf)) {
1413 scan_mrf_high = scan_mrf_low + 1;
1415 scan_mrf_high = scan_mrf_low;
1418 if (mrf_low == scan_mrf_low ||
1419 mrf_low == scan_mrf_high ||
1420 mrf_high == scan_mrf_low ||
1421 mrf_high == scan_mrf_high) {
1426 if (scan_inst->mlen > 0) {
1427 /* Found a SEND instruction, which means that there are
1428 * live values in MRFs from base_mrf to base_mrf +
1429 * scan_inst->mlen - 1. Don't go pushing our MRF write up
1432 if (mrf_low >= scan_inst->base_mrf &&
1433 mrf_low < scan_inst->base_mrf + scan_inst->mlen) {
1436 if (mrf_high >= scan_inst->base_mrf &&
1437 mrf_high < scan_inst->base_mrf + scan_inst->mlen) {
1448 * Walks through basic blocks, locking for repeated MRF writes and
1449 * removing the later ones.
1452 fs_visitor::remove_duplicate_mrf_writes()
1454 fs_inst *last_mrf_move[16];
1455 bool progress = false;
1457 /* Need to update the MRF tracking for compressed instructions. */
1458 if (c->dispatch_width == 16)
1461 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1463 foreach_list_safe(node, &this->instructions) {
1464 fs_inst *inst = (fs_inst *)node;
1466 switch (inst->opcode) {
1468 case BRW_OPCODE_WHILE:
1470 case BRW_OPCODE_ELSE:
1471 case BRW_OPCODE_ENDIF:
1472 memset(last_mrf_move, 0, sizeof(last_mrf_move));
1478 if (inst->opcode == BRW_OPCODE_MOV &&
1479 inst->dst.file == MRF) {
1480 fs_inst *prev_inst = last_mrf_move[inst->dst.hw_reg];
1481 if (prev_inst && inst->equals(prev_inst)) {
1488 /* Clear out the last-write records for MRFs that were overwritten. */
1489 if (inst->dst.file == MRF) {
1490 last_mrf_move[inst->dst.hw_reg] = NULL;
1493 if (inst->mlen > 0) {
1494 /* Found a SEND instruction, which will include two or fewer
1495 * implied MRF writes. We could do better here.
1497 for (int i = 0; i < implied_mrf_writes(inst); i++) {
1498 last_mrf_move[inst->base_mrf + i] = NULL;
1502 /* Clear out any MRF move records whose sources got overwritten. */
1503 if (inst->dst.file == GRF) {
1504 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) {
1505 if (last_mrf_move[i] &&
1506 last_mrf_move[i]->src[0].reg == inst->dst.reg) {
1507 last_mrf_move[i] = NULL;
1512 if (inst->opcode == BRW_OPCODE_MOV &&
1513 inst->dst.file == MRF &&
1514 inst->src[0].file == GRF &&
1515 !inst->predicated) {
1516 last_mrf_move[inst->dst.hw_reg] = inst;
1524 fs_visitor::virtual_grf_interferes(int a, int b)
1526 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
1527 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
1529 /* We can't handle dead register writes here, without iterating
1530 * over the whole instruction stream to find every single dead
1531 * write to that register to compare to the live interval of the
1532 * other register. Just assert that dead_code_eliminate() has been
1535 assert((this->virtual_grf_use[a] != -1 ||
1536 this->virtual_grf_def[a] == MAX_INSTRUCTION) &&
1537 (this->virtual_grf_use[b] != -1 ||
1538 this->virtual_grf_def[b] == MAX_INSTRUCTION));
1540 /* If the register is used to store 16 values of less than float
1541 * size (only the case for pixel_[xy]), then we can't allocate
1542 * another dword-sized thing to that register that would be used in
1543 * the same instruction. This is because when the GPU decodes (for
1546 * (declare (in ) vec4 gl_FragCoord@0x97766a0)
1547 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr };
1549 * it's actually processed as:
1550 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 };
1551 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf };
1553 * so our second half values in g6 got overwritten in the first
1556 if (c->dispatch_width == 16 && (this->pixel_x.reg == a ||
1557 this->pixel_x.reg == b ||
1558 this->pixel_y.reg == a ||
1559 this->pixel_y.reg == b)) {
1560 return start <= end;
1569 uint32_t prog_offset_16 = 0;
1570 uint32_t orig_nr_params = c->prog_data.nr_params;
1572 brw_wm_payload_setup(brw, c);
1574 if (c->dispatch_width == 16) {
1575 /* align to 64 byte boundary. */
1576 while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) {
1580 /* Save off the start of this 16-wide program in case we succeed. */
1581 prog_offset_16 = c->func.nr_insn * sizeof(struct brw_instruction);
1583 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1589 calculate_urb_setup();
1591 emit_interpolation_setup_gen4();
1593 emit_interpolation_setup_gen6();
1595 /* Generate FS IR for main(). (the visitor only descends into
1596 * functions called "main").
1598 foreach_list(node, &*shader->ir) {
1599 ir_instruction *ir = (ir_instruction *)node;
1601 this->result = reg_undef;
1609 split_virtual_grfs();
1611 setup_paramvalues_refs();
1612 setup_pull_constants();
1618 progress = remove_duplicate_mrf_writes() || progress;
1620 progress = propagate_constants() || progress;
1621 progress = opt_algebraic() || progress;
1622 progress = register_coalesce() || progress;
1623 progress = compute_to_mrf() || progress;
1624 progress = dead_code_eliminate() || progress;
1627 schedule_instructions();
1629 assign_curb_setup();
1633 /* Debug of register spilling: Go spill everything. */
1634 int virtual_grf_count = virtual_grf_next;
1635 for (int i = 1; i < virtual_grf_count; i++) {
1641 assign_regs_trivial();
1643 while (!assign_regs()) {
1649 assert(force_uncompressed_stack == 0);
1650 assert(force_sechalf_stack == 0);
1657 if (c->dispatch_width == 8) {
1658 c->prog_data.reg_blocks = brw_register_blocks(grf_used);
1660 c->prog_data.reg_blocks_16 = brw_register_blocks(grf_used);
1661 c->prog_data.prog_offset_16 = prog_offset_16;
1663 /* Make sure we didn't try to sneak in an extra uniform */
1664 assert(orig_nr_params == c->prog_data.nr_params);
1671 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
1672 struct gl_shader_program *prog)
1674 struct intel_context *intel = &brw->intel;
1679 struct brw_shader *shader =
1680 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
1684 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1685 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
1686 _mesa_print_ir(shader->ir, NULL);
1690 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1692 c->dispatch_width = 8;
1694 fs_visitor v(c, prog, shader);
1696 prog->LinkStatus = GL_FALSE;
1697 prog->InfoLog = ralloc_strdup(prog, v.fail_msg);
1702 if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0) {
1703 c->dispatch_width = 16;
1704 fs_visitor v2(c, prog, shader);
1705 v2.import_uniforms(v.variable_ht);
1709 c->prog_data.dispatch_width = 8;
1715 brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
1717 struct brw_context *brw = brw_context(ctx);
1718 struct brw_wm_prog_key key;
1719 struct gl_fragment_program *fp = prog->FragmentProgram;
1720 struct brw_fragment_program *bfp = brw_fragment_program(fp);
1725 memset(&key, 0, sizeof(key));
1728 key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
1730 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
1731 key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
1733 /* Just assume depth testing. */
1734 key.iz_lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
1735 key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
1737 key.vp_outputs_written |= BITFIELD64_BIT(FRAG_ATTRIB_WPOS);
1738 for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1741 if (!(fp->Base.InputsRead & BITFIELD64_BIT(i)))
1744 key.proj_attrib_mask |= 1 << i;
1746 if (i <= FRAG_ATTRIB_TEX7)
1748 else if (i >= FRAG_ATTRIB_VAR0)
1749 vp_index = i - FRAG_ATTRIB_VAR0 + VERT_RESULT_VAR0;
1752 key.vp_outputs_written |= BITFIELD64_BIT(vp_index);
1755 key.clamp_fragment_color = true;
1757 for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) {
1758 if (fp->Base.ShadowSamplers & (1 << i))
1759 key.compare_funcs[i] = GL_LESS;
1761 /* FINISHME: depth compares might use (0,0,0,W) for example */
1762 key.tex_swizzles[i] = SWIZZLE_XYZW;
1765 if (fp->Base.InputsRead & FRAG_BIT_WPOS) {
1766 key.drawable_height = ctx->DrawBuffer->Height;
1767 key.render_to_fbo = ctx->DrawBuffer->Name != 0;
1770 key.nr_color_regions = 1;
1772 key.program_string_id = bfp->id;
1774 uint32_t old_prog_offset = brw->wm.prog_offset;
1775 struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
1777 bool success = do_wm_prog(brw, prog, bfp, &key);
1779 brw->wm.prog_offset = old_prog_offset;
1780 brw->wm.prog_data = old_prog_data;