2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
43 * URB - uniform resource buffer. A mid-sized buffer which is
44 * partitioned between the fixed function units and used for passing
45 * values (vertices, primitives, constants) between them.
47 * CURBE - constant URB entry. An urb region (entry) used to hold
48 * constant values which the fixed function units can be instructed to
49 * preload into the GRF when spawning a thread.
51 * VUE - vertex URB entry. An urb entry holding a vertex and usually
52 * a vertex header. The header contains control information and
53 * things like primitive type, Begin/end flags and clip codes.
55 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
56 * unit holding rasterization and interpolation parameters.
58 * GRF - general register file. One of several register files
59 * addressable by programmed threads. The inputs (r0, payload, curbe,
60 * urb) of the thread are preloaded to this area before the thread is
61 * spawned. The registers are individually 8 dwords wide and suitable
62 * for general usage. Registers holding thread input values are not
63 * special and may be overwritten.
65 * MRF - message register file. Threads communicate (and terminate)
66 * by sending messages. Message parameters are placed in contiguous
67 * MRF registers. All program output is via these messages. URB
68 * entries are populated by sending a message to the shared URB
69 * function containing the new data, together with a control word,
70 * often an unmodified copy of R0.
72 * R0 - GRF register 0. Typically holds control information used when
73 * sending messages to other threads.
75 * EU or GEN4 EU: The name of the programmable subsystem of the
76 * i965 hardware. Threads are executed by the EU, the registers
77 * described above are part of the EU architecture.
79 * Fixed function units:
81 * CS - Command streamer. Notional first unit, little software
82 * interaction. Holds the URB entries used for constant data, ie the
85 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
86 * this unit is responsible for pulling vertices out of vertex buffers
87 * in vram and injecting them into the processing pipe as VUEs. If
88 * enabled, it first passes them to a VS thread which is a good place
89 * for the driver to implement any active vertex shader.
91 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
92 * enabled, incoming strips etc are passed to GS threads in individual
93 * line/triangle/point units. The GS thread may perform arbitary
94 * computation and emit whatever primtives with whatever vertices it
95 * chooses. This makes GS an excellent place to implement GL's
96 * unfilled polygon modes, though of course it is capable of much
97 * more. Additionally, GS is used to translate away primitives not
98 * handled by latter units, including Quads and Lineloops.
100 * CS - Clipper. Mesa's clipping algorithms are imported to run on
101 * this unit. The fixed function part performs cliptesting against
102 * the 6 fixed clipplanes and makes descisions on whether or not the
103 * incoming primitive needs to be passed to a thread for clipping.
104 * User clip planes are handled via cooperation with the VS thread.
106 * SF - Strips Fans or Setup: Triangles are prepared for
107 * rasterization. Interpolation coefficients are calculated.
108 * Flatshading and two-side lighting usually performed here.
110 * WM - Windower. Interpolation of vertex attributes performed here.
111 * Fragment shader implemented here. SIMD aspects of EU taken full
112 * advantage of, as pixels are processed in blocks of 16.
114 * CC - Color Calculator. No EU threads associated with this unit.
115 * Handles blending and (presumably) depth and stencil testing.
119 #define BRW_MAX_CURBE (32*16)
125 BRW_STATE_FRAGMENT_PROGRAM,
126 BRW_STATE_VERTEX_PROGRAM,
127 BRW_STATE_INPUT_DIMENSIONS,
128 BRW_STATE_CURBE_OFFSETS,
129 BRW_STATE_REDUCED_PRIMITIVE,
132 BRW_STATE_WM_INPUT_DIMENSIONS,
134 BRW_STATE_WM_SURFACES,
135 BRW_STATE_VS_BINDING_TABLE,
136 BRW_STATE_GS_BINDING_TABLE,
137 BRW_STATE_PS_BINDING_TABLE,
141 BRW_STATE_NR_WM_SURFACES,
142 BRW_STATE_NR_VS_SURFACES,
143 BRW_STATE_INDEX_BUFFER,
144 BRW_STATE_VS_CONSTBUF,
145 BRW_STATE_PROGRAM_CACHE,
146 BRW_STATE_STATE_BASE_ADDRESS,
149 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
150 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
151 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
152 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
153 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
154 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
155 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
156 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
157 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
158 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
159 #define BRW_NEW_WM_SURFACES (1 << BRW_STATE_WM_SURFACES)
160 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
161 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
162 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
163 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
164 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
166 * Used for any batch entry with a relocated pointer that will be used
167 * by any 3D rendering.
169 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
170 /** \see brw.state.depth_region */
171 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
172 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
173 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
174 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
176 struct brw_state_flags {
177 /** State update flags signalled by mesa internals */
180 * State update flags signalled as the result of brw_tracked_state updates
183 /** State update flags signalled by brw_state_cache.c searches */
187 enum state_struct_type {
188 AUB_TRACE_VS_STATE = 1,
189 AUB_TRACE_GS_STATE = 2,
190 AUB_TRACE_CLIP_STATE = 3,
191 AUB_TRACE_SF_STATE = 4,
192 AUB_TRACE_WM_STATE = 5,
193 AUB_TRACE_CC_STATE = 6,
194 AUB_TRACE_CLIP_VP_STATE = 7,
195 AUB_TRACE_SF_VP_STATE = 8,
196 AUB_TRACE_CC_VP_STATE = 0x9,
197 AUB_TRACE_SAMPLER_STATE = 0xa,
198 AUB_TRACE_KERNEL_INSTRUCTIONS = 0xb,
199 AUB_TRACE_SCRATCH_SPACE = 0xc,
200 AUB_TRACE_SAMPLER_DEFAULT_COLOR = 0xd,
202 AUB_TRACE_SCISSOR_STATE = 0x15,
203 AUB_TRACE_BLEND_STATE = 0x16,
204 AUB_TRACE_DEPTH_STENCIL_STATE = 0x17,
206 /* Not written to .aub files the same way the structures above are. */
207 AUB_TRACE_NO_TYPE = 0x100,
208 AUB_TRACE_BINDING_TABLE = 0x101,
209 AUB_TRACE_SURFACE_STATE = 0x102,
210 AUB_TRACE_VS_CONSTANTS = 0x103,
211 AUB_TRACE_WM_CONSTANTS = 0x104,
214 /** Subclass of Mesa vertex program */
215 struct brw_vertex_program {
216 struct gl_vertex_program program;
218 bool use_const_buffer;
222 /** Subclass of Mesa fragment program */
223 struct brw_fragment_program {
224 struct gl_fragment_program program;
225 GLuint id; /**< serial no. to identify frag progs, never re-used */
229 struct gl_shader base;
231 /** Shader IR transformed for native compile, at link time. */
232 struct exec_list *ir;
235 struct brw_shader_program {
236 struct gl_shader_program base;
239 enum param_conversion {
247 /* Data about a particular attempt to compile a program. Note that
248 * there can be many of these, each in a different GL state
249 * corresponding to a different brw_wm_prog_key struct, with different
252 struct brw_wm_prog_data {
253 GLuint curb_read_length;
254 GLuint urb_read_length;
256 GLuint first_curbe_grf;
257 GLuint first_curbe_grf_16;
259 GLuint reg_blocks_16;
260 GLuint total_scratch;
262 GLuint nr_params; /**< number of float params/constants */
263 GLuint nr_pull_params;
266 uint32_t prog_offset_16;
268 /* Pointer to tracked values (only valid once
269 * _mesa_load_state_parameters has been called at runtime).
271 const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
272 enum param_conversion param_convert[MAX_UNIFORMS * 4];
273 const float *pull_param[MAX_UNIFORMS * 4];
274 enum param_conversion pull_param_convert[MAX_UNIFORMS * 4];
278 * Enum representing the i965-specific vertex results that don't correspond
279 * exactly to any element of gl_vert_result. The values of this enum are
280 * assigned such that they don't conflict with gl_vert_result.
284 BRW_VERT_RESULT_NDC = VERT_RESULT_MAX,
285 BRW_VERT_RESULT_HPOS_DUPLICATE,
292 * Data structure recording the relationship between the gl_vert_result enum
293 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
294 * single octaword within the VUE (128 bits).
296 * Note that each BRW register contains 256 bits (2 octawords), so when
297 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
298 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
299 * in a vertex shader), each register corresponds to a single VUE slot, since
300 * it contains data for two separate vertices.
304 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
305 * not stored in a slot (because they are not written, or because
306 * additional processing is applied before storing them in the VUE), the
309 int vert_result_to_slot[BRW_VERT_RESULT_MAX];
312 * Map from VUE slot to gl_vert_result value. For slots that do not
313 * directly correspond to a gl_vert_result, the value comes from
316 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
317 * simplifies code that uses the value stored in slot_to_vert_result to
318 * create a bit mask).
320 int slot_to_vert_result[BRW_VERT_RESULT_MAX];
323 * Total number of VUE slots in use
329 * Convert a VUE slot number into a byte offset within the VUE.
331 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
337 * Convert a vert_result into a byte offset within the VUE.
339 static inline GLuint brw_vert_result_to_offset(struct brw_vue_map *vue_map,
342 return brw_vue_slot_to_offset(vue_map->vert_result_to_slot[vert_result]);
346 struct brw_sf_prog_data {
347 GLuint urb_read_length;
350 /* Each vertex may have upto 12 attributes, 4 components each,
351 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
354 * Actually we use 4 for each, so call it 12 rows.
356 GLuint urb_entry_size;
359 struct brw_clip_prog_data {
360 GLuint curb_read_length; /* user planes? */
362 GLuint urb_read_length;
366 struct brw_gs_prog_data {
367 GLuint urb_read_length;
371 struct brw_vs_prog_data {
372 GLuint curb_read_length;
373 GLuint urb_read_length;
375 GLbitfield64 outputs_written;
376 GLuint nr_params; /**< number of float params/constants */
377 GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
378 GLuint total_scratch;
382 /* Used for calculating urb partitions:
384 GLuint urb_entry_size;
386 const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
387 const float *pull_param[MAX_UNIFORMS * 4];
389 bool uses_new_param_layout;
393 /* Size == 0 if output either not written, or always [0,0,0,1]
395 struct brw_vs_ouput_sizes {
396 GLubyte output_size[VERT_RESULT_MAX];
400 /** Number of texture sampler units */
401 #define BRW_MAX_TEX_UNIT 16
403 /** Max number of render targets in a shader */
404 #define BRW_MAX_DRAW_BUFFERS 8
407 * Helpers to create Surface Binding Table indexes for draw buffers,
408 * textures, and constant buffers.
410 * Shader threads access surfaces via numeric handles, rather than directly
411 * using pointers. The binding table maps these numeric handles to the
412 * address of the actual buffer.
414 * For example, a shader might ask to sample from "surface 7." In this case,
415 * bind[7] would contain a pointer to a texture.
417 * Although the hardware supports separate binding tables per pipeline stage
418 * (VS, HS, DS, GS, PS), we currently share a single binding table for all of
419 * them. This is purely for convenience.
421 * Currently our binding tables are (arbitrarily) programmed as follows:
423 * +-------------------------------+
424 * | 0 | Draw buffer 0 | .
426 * | : | : | > Only relevant to the WM.
427 * | 7 | Draw buffer 7 | /
428 * |-----|-------------------------| `
429 * | 8 | VS Pull Constant Buffer |
430 * | 9 | WM Pull Constant Buffer |
431 * |-----|-------------------------|
435 * | 25 | Texture 15 |
436 * +-------------------------------+
438 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
439 * the identity function or things will break. We do want to keep draw buffers
440 * first so we can use headerless render target writes for RT 0.
442 #define SURF_INDEX_DRAW(d) (d)
443 #define SURF_INDEX_VERT_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 0)
444 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
445 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
447 /** Maximum size of the binding table. */
448 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 2)
452 BRW_DEPTH_STENCIL_STATE,
453 BRW_COLOR_CALC_STATE,
461 BRW_SF_UNIT, /* scissor state on gen6 */
473 struct brw_cache_item {
475 * Effectively part of the key, cache_id identifies what kind of state
476 * buffer is involved, and also which brw->state.dirty.cache flag should
477 * be set when this cache item is chosen.
479 enum brw_cache_id cache_id;
480 /** 32-bit hash of the key data */
482 GLuint key_size; /* for variable-sized keys */
489 struct brw_cache_item *next;
495 struct brw_context *brw;
497 struct brw_cache_item **items;
499 GLuint size, n_items;
501 uint32_t next_offset;
506 /* Considered adding a member to this struct to document which flags
507 * an update might raise so that ordering of the state atoms can be
508 * checked or derived at runtime. Dropped the idea in favor of having
509 * a debug mode where the state is monitored for flags which are
510 * raised that have already been tested against.
512 struct brw_tracked_state {
513 struct brw_state_flags dirty;
514 void (*emit)( struct brw_context *brw );
517 /* Flags for brw->state.cache.
519 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
520 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
521 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
522 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
523 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
524 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
525 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
526 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
527 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
528 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
529 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
530 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
531 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
532 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
533 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
534 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
535 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
536 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
538 struct brw_cached_batch_item {
539 struct header *header;
541 struct brw_cached_batch_item *next;
546 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
547 * be easier if C allowed arrays of packed elements?
549 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
551 struct brw_vertex_buffer {
552 /** Buffer object containing the uploaded vertex data */
555 /** Byte stride between elements in the uploaded array */
558 struct brw_vertex_element {
559 const struct gl_client_array *glarray;
563 /** The corresponding Mesa vertex attribute */
564 gl_vert_attrib attrib;
565 /** Size of a complete element */
567 /** Offset of the first element within the buffer object */
573 struct brw_vertex_info {
574 GLuint sizes[ATTRIB_BIT_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */
577 struct brw_query_object {
578 struct gl_query_object Base;
580 /** Last query BO associated with this query. */
582 /** First index in bo with query data for this object. */
584 /** Last index in bo with query data for this object. */
590 * brw_context is derived from intel_context.
594 struct intel_context intel; /**< base class, must be first field */
595 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
597 bool emit_state_always;
598 bool has_surface_tile_offset;
600 bool has_negative_rhw_bug;
601 bool has_aa_line_parameters;
606 struct brw_state_flags dirty;
609 struct brw_cache cache;
610 struct brw_cached_batch_item *cached_batch_items;
613 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
614 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
619 } current_buffers[VERT_ATTRIB_MAX];
621 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
623 GLuint nr_buffers, nr_current_buffers;
625 /* Summary of size and varying of active arrays, so we can check
626 * for changes to this state:
628 struct brw_vertex_info info;
629 unsigned int min_index, max_index;
631 /* Offset from start of vertex buffer so we can avoid redefining
632 * the same VB packed over and over again.
634 unsigned int start_vertex_bias;
639 * Index buffer for this draw_prims call.
641 * Updates are signaled by BRW_NEW_INDICES.
643 const struct _mesa_index_buffer *ib;
645 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
649 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
650 * avoid re-uploading the IB packet over and over if we're actually
651 * referencing the same index buffer.
653 unsigned int start_vertex_offset;
656 /* Active vertex program:
658 const struct gl_vertex_program *vertex_program;
659 const struct gl_fragment_program *fragment_program;
661 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
662 uint32_t CMD_VF_STATISTICS;
663 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
664 uint32_t CMD_PIPELINE_SELECT;
667 * Platform specific constants containing the maximum number of threads
668 * for each pipeline stage.
674 /* BRW_NEW_URB_ALLOCATIONS:
677 GLuint vsize; /* vertex size plus header in urb registers */
678 GLuint csize; /* constant buffer size in urb registers */
679 GLuint sfsize; /* setup data size in urb registers */
683 GLuint max_vs_entries; /* Maximum number of VS entries */
684 GLuint max_gs_entries; /* Maximum number of GS entries */
686 GLuint nr_vs_entries;
687 GLuint nr_gs_entries;
688 GLuint nr_clip_entries;
689 GLuint nr_sf_entries;
690 GLuint nr_cs_entries;
693 * The length of each URB entry owned by the VS (or GS), as
694 * a number of 1024-bit (128-byte) rows. Should be >= 1.
696 * gen7: Same meaning, but in 512-bit (64-byte) rows.
706 GLuint size; /* Hardware URB size, in KB. */
710 /* BRW_NEW_CURBE_OFFSETS:
713 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
714 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
721 drm_intel_bo *curbe_bo;
722 /** Offset within curbe_bo of space for current curbe entry */
724 /** Offset within curbe_bo of space for next curbe entry */
725 GLuint curbe_next_offset;
728 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
729 * in brw_curbe.c with the same set of constant data to be uploaded,
730 * so we'd rather not upload new constants in that case (it can cause
731 * a pipeline bubble since only up to 4 can be pipelined at a time).
735 * Allocation for where to calculate the next set of CURBEs.
736 * It's a hot enough path that malloc/free of that data matters.
743 /** Binding table of pointers to surf_bo entries */
745 uint32_t surf_offset[BRW_MAX_SURFACES];
748 /** SAMPLER_STATE count and offset */
755 struct brw_vs_prog_data *prog_data;
756 int8_t *constant_map; /* variable array following prog_data */
758 drm_intel_bo *scratch_bo;
759 drm_intel_bo *const_bo;
760 /** Offset in the program cache to the VS program */
761 uint32_t prog_offset;
762 uint32_t state_offset;
764 uint32_t push_const_offset; /* Offset in the batchbuffer */
765 int push_const_size; /* in 256-bit register increments */
767 /** @{ register allocator */
769 struct ra_regs *regs;
772 * Array of the ra classes for the unaligned contiguous register
778 * Mapping for register-allocated objects in *regs to the first
779 * GRF for that object.
781 uint8_t *ra_reg_to_grf;
786 struct brw_gs_prog_data *prog_data;
789 /** Offset in the program cache to the CLIP program pre-gen6 */
790 uint32_t prog_offset;
791 uint32_t state_offset;
795 struct brw_clip_prog_data *prog_data;
797 /** Offset in the program cache to the CLIP program pre-gen6 */
798 uint32_t prog_offset;
800 /* Offset in the batch to the CLIP state on pre-gen6. */
801 uint32_t state_offset;
803 /* As of gen6, this is the offset in the batch to the CLIP VP,
811 struct brw_sf_prog_data *prog_data;
813 /** Offset in the program cache to the CLIP program pre-gen6 */
814 uint32_t prog_offset;
815 uint32_t state_offset;
820 struct brw_wm_prog_data *prog_data;
821 struct brw_wm_compile *compile_data;
823 /** Input sizes, calculated from active vertex program.
824 * One bit per fragment program input attribute.
826 GLbitfield input_size_masks[4];
828 /** offsets in the batch to sampler default colors (texture border color)
830 uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
834 drm_intel_bo *scratch_bo;
836 /** Offset in the program cache to the WM program */
837 uint32_t prog_offset;
839 uint32_t state_offset; /* offset in batchbuffer to pre-gen6 WM state */
841 drm_intel_bo *const_bo; /* pull constant buffer. */
843 * This is offset in the batch to the push constants on gen6.
845 * Pre-gen6, push constants live in the CURBE.
847 uint32_t push_const_offset;
849 /** @{ register allocator */
851 struct ra_regs *regs;
853 /** Array of the ra classes for the unaligned contiguous
854 * register block sizes used.
859 * Mapping for register-allocated objects in *regs to the first
860 * GRF for that object.
862 uint8_t *ra_reg_to_grf;
865 * ra class for the aligned pairs we use for PLN, which doesn't
866 * appear in *classes.
868 int aligned_pairs_class;
875 uint32_t state_offset;
876 uint32_t blend_state_offset;
877 uint32_t depth_stencil_state_offset;
882 struct brw_query_object *obj;
887 /* Used to give every program string a unique id
892 const struct brw_tracked_state **atoms;
894 /* If (INTEL_DEBUG & DEBUG_BATCH) */
898 enum state_struct_type type;
900 int state_batch_count;
905 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
907 struct brw_instruction_info {
913 extern const struct brw_instruction_info brw_opcodes[128];
915 /*======================================================================
918 void brwInitVtbl( struct brw_context *brw );
920 /*======================================================================
923 bool brwCreateContext(int api,
924 const struct gl_config *mesaVis,
925 __DRIcontext *driContextPriv,
926 void *sharedContextPrivate);
928 /*======================================================================
931 void brw_init_queryobj_functions(struct dd_function_table *functions);
932 void brw_prepare_query_begin(struct brw_context *brw);
933 void brw_emit_query_begin(struct brw_context *brw);
934 void brw_emit_query_end(struct brw_context *brw);
936 /*======================================================================
939 void brw_debug_batch(struct intel_context *intel);
941 /*======================================================================
944 void brw_validate_textures( struct brw_context *brw );
947 /*======================================================================
950 void brwInitFragProgFuncs( struct dd_function_table *functions );
952 int brw_get_scratch_size(int size);
953 void brw_get_scratch_bo(struct intel_context *intel,
954 drm_intel_bo **scratch_bo, int size);
959 void brw_upload_urb_fence(struct brw_context *brw);
963 void brw_upload_cs_urb_state(struct brw_context *brw);
966 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
969 void brw_compute_vue_map(struct brw_vue_map *vue_map,
970 const struct intel_context *intel,
971 bool userclip_active,
972 GLbitfield64 outputs_written);
973 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
977 brw_compute_barycentric_interp_modes(bool shade_model_flat,
978 const struct gl_fragment_program *fprog);
980 /* gen6_clip_state.c */
982 brw_fprog_uses_noperspective(const struct gl_fragment_program *fprog);
986 /*======================================================================
987 * Inline conversion functions. These are better-typed than the
988 * macros used previously:
990 static INLINE struct brw_context *
991 brw_context( struct gl_context *ctx )
993 return (struct brw_context *)ctx;
996 static INLINE struct brw_vertex_program *
997 brw_vertex_program(struct gl_vertex_program *p)
999 return (struct brw_vertex_program *) p;
1002 static INLINE const struct brw_vertex_program *
1003 brw_vertex_program_const(const struct gl_vertex_program *p)
1005 return (const struct brw_vertex_program *) p;
1008 static INLINE struct brw_fragment_program *
1009 brw_fragment_program(struct gl_fragment_program *p)
1011 return (struct brw_fragment_program *) p;
1014 static INLINE const struct brw_fragment_program *
1015 brw_fragment_program_const(const struct gl_fragment_program *p)
1017 return (const struct brw_fragment_program *) p;
1021 float convert_param(enum param_conversion conversion, const float *param)
1029 switch (conversion) {
1030 case PARAM_NO_CONVERT:
1032 case PARAM_CONVERT_F2I:
1035 case PARAM_CONVERT_F2U:
1038 case PARAM_CONVERT_F2B:
1044 case PARAM_CONVERT_ZERO:
1052 * Pre-gen6, the register file of the EUs was shared between threads,
1053 * and each thread used some subset allocated on a 16-register block
1054 * granularity. The unit states wanted these block counts.
1057 brw_register_blocks(int reg_count)
1059 return ALIGN(reg_count, 16) / 16 - 1;
1062 static inline uint32_t
1063 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
1064 uint32_t prog_offset)
1066 struct intel_context *intel = &brw->intel;
1068 if (intel->gen >= 5) {
1069 /* Using state base address. */
1073 drm_intel_bo_emit_reloc(intel->batch.bo,
1077 I915_GEM_DOMAIN_INSTRUCTION, 0);
1079 return brw->cache.bo->offset + prog_offset;
1082 bool brw_do_cubemap_normalize(struct exec_list *instructions);