2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
26 #include "glsl/ralloc.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
33 #include "brw_state.h"
37 * Helper function for handling mirror image blits.
39 * If coord0 > coord1, swap them and invert the "mirror" boolean.
42 fixup_mirroring(bool &mirror, GLint &coord0, GLint &coord1)
44 if (coord0 > coord1) {
54 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
55 * destination coordinates.
57 * Return true if there is still blitting to do, false if all pixels got
58 * rejected by the clip and/or scissor.
60 * For clarity, the nomenclature of this function assumes we are clipping and
61 * scissoring the X coordinate; the exact same logic applies for Y
64 * Note: this function may also be used to account for clipping of source
65 * coordinates, by swapping the roles of src and dst.
68 clip_or_scissor(bool mirror, GLint &src_x0, GLint &src_x1, GLint &dst_x0,
69 GLint &dst_x1, GLint fb_xmin, GLint fb_xmax)
71 /* If we are going to scissor everything away, stop. */
72 if (!(fb_xmin < fb_xmax &&
79 /* Clip the destination rectangle, and keep track of how many pixels we
80 * clipped off of the left and right sides of it.
82 GLint pixels_clipped_left = 0;
83 GLint pixels_clipped_right = 0;
84 if (dst_x0 < fb_xmin) {
85 pixels_clipped_left = fb_xmin - dst_x0;
88 if (fb_xmax < dst_x1) {
89 pixels_clipped_right = dst_x1 - fb_xmax;
93 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
94 * the source coordinates, we need to flip them to account for the
98 GLint tmp = pixels_clipped_left;
99 pixels_clipped_left = pixels_clipped_right;
100 pixels_clipped_right = tmp;
103 /* Adjust the source rectangle to remove the pixels corresponding to those
104 * that were clipped/scissored out of the destination rectangle.
106 src_x0 += pixels_clipped_left;
107 src_x1 -= pixels_clipped_right;
114 try_blorp_blit(struct intel_context *intel,
115 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
116 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
117 GLenum filter, GLbitfield buffer_bit)
119 struct gl_context *ctx = &intel->ctx;
121 /* Sync up the state of window system buffers. We need to do this before
122 * we go looking for the buffers.
124 intel_prepare_render(intel);
127 const struct gl_framebuffer *read_fb = ctx->ReadBuffer;
128 const struct gl_framebuffer *draw_fb = ctx->DrawBuffer;
129 struct gl_renderbuffer *src_rb;
130 struct gl_renderbuffer *dst_rb;
131 switch (buffer_bit) {
132 case GL_COLOR_BUFFER_BIT:
133 src_rb = read_fb->_ColorReadBuffer;
136 draw_fb->_ColorDrawBufferIndexes[0]].Renderbuffer;
138 case GL_DEPTH_BUFFER_BIT:
139 src_rb = read_fb->Attachment[BUFFER_DEPTH].Renderbuffer;
140 dst_rb = draw_fb->Attachment[BUFFER_DEPTH].Renderbuffer;
142 case GL_STENCIL_BUFFER_BIT:
143 src_rb = read_fb->Attachment[BUFFER_STENCIL].Renderbuffer;
144 dst_rb = draw_fb->Attachment[BUFFER_STENCIL].Renderbuffer;
150 /* Validate source */
151 if (!src_rb) return false;
152 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
153 struct intel_mipmap_tree *src_mt = src_irb->mt;
154 if (!src_mt) return false;
155 if (buffer_bit == GL_STENCIL_BUFFER_BIT && src_mt->stencil_mt)
156 src_mt = src_mt->stencil_mt;
158 /* Validate destination */
159 if (!dst_rb) return false;
160 struct intel_renderbuffer *dst_irb = intel_renderbuffer(dst_rb);
161 struct intel_mipmap_tree *dst_mt = dst_irb->mt;
162 if (!dst_mt) return false;
163 if (buffer_bit == GL_STENCIL_BUFFER_BIT && dst_mt->stencil_mt)
164 dst_mt = dst_mt->stencil_mt;
166 /* Blorp blits can't translate from one format to another. For that we'll
167 * have to fall back to the meta-op blit. Note: the meta-op blit doesn't
168 * support multisampled blits, but fortunately this is ok because
169 * multisampled blits require identical source and destination formats.
171 if (src_mt->format != dst_mt->format)
174 /* Account for the fact that in the system framebuffer, the origin is at
177 if (read_fb->Name == 0) {
178 srcY0 = read_fb->Height - srcY0;
179 srcY1 = read_fb->Height - srcY1;
181 if (draw_fb->Name == 0) {
182 dstY0 = draw_fb->Height - dstY0;
183 dstY1 = draw_fb->Height - dstY1;
186 /* Detect if the blit needs to be mirrored */
187 bool mirror_x = false, mirror_y = false;
188 fixup_mirroring(mirror_x, srcX0, srcX1);
189 fixup_mirroring(mirror_x, dstX0, dstX1);
190 fixup_mirroring(mirror_y, srcY0, srcY1);
191 fixup_mirroring(mirror_y, dstY0, dstY1);
193 /* Make sure width and height match */
194 GLsizei width = srcX1 - srcX0;
195 GLsizei height = srcY1 - srcY0;
196 if (width != dstX1 - dstX0) return false;
197 if (height != dstY1 - dstY0) return false;
199 /* If the destination rectangle needs to be clipped or scissored, do so.
201 if (!(clip_or_scissor(mirror_x, srcX0, srcX1, dstX0, dstX1,
202 draw_fb->_Xmin, draw_fb->_Xmax) &&
203 clip_or_scissor(mirror_y, srcY0, srcY1, dstY0, dstY1,
204 draw_fb->_Ymin, draw_fb->_Ymax))) {
205 /* Everything got clipped/scissored away, so the blit was successful. */
209 /* If the source rectangle needs to be clipped or scissored, do so. */
210 if (!(clip_or_scissor(mirror_x, dstX0, dstX1, srcX0, srcX1,
211 0, read_fb->Width) &&
212 clip_or_scissor(mirror_y, dstY0, dstY1, srcY0, srcY1,
213 0, read_fb->Height))) {
214 /* Everything got clipped/scissored away, so the blit was successful. */
218 /* Get ready to blit. This includes depth resolving the src and dst
219 * buffers if necessary.
221 intel_renderbuffer_resolve_depth(intel, src_irb);
222 intel_renderbuffer_resolve_depth(intel, dst_irb);
225 brw_blorp_blit_params params(brw_context(ctx), src_mt, dst_mt,
226 srcX0, srcY0, dstX0, dstY0, dstX1, dstY1,
228 brw_blorp_exec(intel, ¶ms);
230 /* Mark the dst buffer as needing a HiZ resolve if necessary. */
231 intel_renderbuffer_set_needs_hiz_resolve(dst_irb);
237 brw_blorp_framebuffer(struct intel_context *intel,
238 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
239 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
240 GLbitfield mask, GLenum filter)
242 /* BLORP is not supported before Gen6. */
246 static GLbitfield buffer_bits[] = {
249 GL_STENCIL_BUFFER_BIT,
252 for (unsigned int i = 0; i < ARRAY_SIZE(buffer_bits); ++i) {
253 if ((mask & buffer_bits[i]) &&
254 try_blorp_blit(intel,
255 srcX0, srcY0, srcX1, srcY1,
256 dstX0, dstY0, dstX1, dstY1,
257 filter, buffer_bits[i])) {
258 mask &= ~buffer_bits[i];
267 * Enum to specify the order of arguments in a sampler message
269 enum sampler_message_arg
271 SAMPLER_MESSAGE_ARG_U_FLOAT,
272 SAMPLER_MESSAGE_ARG_V_FLOAT,
273 SAMPLER_MESSAGE_ARG_U_INT,
274 SAMPLER_MESSAGE_ARG_V_INT,
275 SAMPLER_MESSAGE_ARG_SI_INT,
276 SAMPLER_MESSAGE_ARG_MCS_INT,
277 SAMPLER_MESSAGE_ARG_ZERO_INT,
281 * Generator for WM programs used in BLORP blits.
283 * The bulk of the work done by the WM program is to wrap and unwrap the
284 * coordinate transformations used by the hardware to store surfaces in
285 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
286 * sample index for a multisampled surface) to a memory offset by the
287 * following formulas:
289 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
290 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
292 * For a single-sampled surface, or for a multisampled surface using
293 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
296 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
297 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
298 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
299 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
301 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
302 * embeds the sample number into bit 1 of the X and Y coordinates:
304 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
305 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
306 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
307 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
308 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
309 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
310 * S = (Y & 0b10) | (X & 0b10) >> 1
312 * For X tiling, tile() combines together the low-order bits of the X and Y
313 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
314 * bytes wide and 8 rows high:
316 * tile(x_tiled, X, Y, S) = A
317 * where A = tile_num << 12 | offset
318 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
319 * offset = (Y' & 0b111) << 9
320 * | (X & 0b111111111)
322 * Y' = Y + S * qpitch
323 * detile(x_tiled, A) = (X, Y, S)
327 * Y' = (tile_num / tile_pitch) << 3
328 * | (A & 0b111000000000) >> 9
329 * X' = (tile_num % tile_pitch) << 9
330 * | (A & 0b111111111)
332 * (In all tiling formulas, cpp is the number of bytes occupied by a single
333 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
334 * to fill the width of the surface, and qpitch is the spacing (in rows)
335 * between array slices).
337 * For Y tiling, tile() combines together the low-order bits of the X and Y
338 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
339 * bytes wide and 32 rows high:
341 * tile(y_tiled, X, Y, S) = A
342 * where A = tile_num << 12 | offset
343 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
344 * offset = (X' & 0b1110000) << 5
345 * | (Y' & 0b11111) << 4
348 * Y' = Y + S * qpitch
349 * detile(y_tiled, A) = (X, Y, S)
353 * Y' = (tile_num / tile_pitch) << 5
354 * | (A & 0b111110000) >> 4
355 * X' = (tile_num % tile_pitch) << 7
356 * | (A & 0b111000000000) >> 5
359 * For W tiling, tile() combines together the low-order bits of the X and Y
360 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
361 * bytes wide and 64 rows high (note that W tiling is only used for stencil
362 * buffers, which always have cpp = 1 and S=0):
364 * tile(w_tiled, X, Y, S) = A
365 * where A = tile_num << 12 | offset
366 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
367 * offset = (X' & 0b111000) << 6
368 * | (Y' & 0b111100) << 3
369 * | (X' & 0b100) << 2
375 * Y' = Y + S * qpitch
376 * detile(w_tiled, A) = (X, Y, S)
377 * where X = X' / cpp = X'
378 * Y = Y' % qpitch = Y'
380 * Y' = (tile_num / tile_pitch) << 6
381 * | (A & 0b111100000) >> 3
382 * | (A & 0b1000) >> 2
384 * X' = (tile_num % tile_pitch) << 6
385 * | (A & 0b111000000000) >> 6
386 * | (A & 0b10000) >> 2
390 * Finally, for a non-tiled surface, tile() simply combines together the X and
391 * Y coordinates in the natural way:
393 * tile(untiled, X, Y, S) = A
394 * where A = Y * pitch + X'
396 * Y' = Y + S * qpitch
397 * detile(untiled, A) = (X, Y, S)
404 * (In these formulas, pitch is the number of bytes occupied by a single row
407 class brw_blorp_blit_program
410 brw_blorp_blit_program(struct brw_context *brw,
411 const brw_blorp_blit_prog_key *key);
412 ~brw_blorp_blit_program();
414 const GLuint *compile(struct brw_context *brw, GLuint *program_size);
416 brw_blorp_prog_data prog_data;
420 void alloc_push_const_regs(int base_reg);
421 void compute_frag_coords();
422 void translate_tiling(bool old_tiled_w, bool new_tiled_w);
423 void encode_msaa(unsigned num_samples, intel_msaa_layout layout);
424 void decode_msaa(unsigned num_samples, intel_msaa_layout layout);
425 void kill_if_outside_dst_rect();
426 void translate_dst_to_src();
427 void single_to_blend();
429 void sample(struct brw_reg dst);
430 void texel_fetch(struct brw_reg dst);
432 void expand_to_32_bits(struct brw_reg src, struct brw_reg dst);
433 void texture_lookup(struct brw_reg dst, GLuint msg_type,
434 const sampler_message_arg *args, int num_args);
435 void render_target_write();
438 * Base-2 logarithm of the maximum number of samples that can be blended.
440 static const unsigned LOG2_MAX_BLEND_SAMPLES = 2;
443 struct brw_context *brw;
444 const brw_blorp_blit_prog_key *key;
445 struct brw_compile func;
447 /* Thread dispatch header */
450 /* Pixel X/Y coordinates (always in R1). */
454 struct brw_reg dst_x0;
455 struct brw_reg dst_x1;
456 struct brw_reg dst_y0;
457 struct brw_reg dst_y1;
459 struct brw_reg multiplier;
460 struct brw_reg offset;
461 } x_transform, y_transform;
463 /* Data read from texture (4 vec16's per array element) */
464 struct brw_reg texture_data[LOG2_MAX_BLEND_SAMPLES + 1];
466 /* Auxiliary storage for the contents of the MCS surface.
468 * Since the sampler always returns 8 registers worth of data, this is 8
469 * registers wide, even though we only use the first 2 registers of it.
471 struct brw_reg mcs_data;
473 /* X coordinates. We have two of them so that we can perform coordinate
474 * transformations easily.
476 struct brw_reg x_coords[2];
478 /* Y coordinates. We have two of them so that we can perform coordinate
479 * transformations easily.
481 struct brw_reg y_coords[2];
483 /* Which element of x_coords and y_coords is currently in use.
487 /* True if, at the point in the program currently being compiled, the
488 * sample index is known to be zero.
492 /* Register storing the sample index when s_is_zero is false. */
493 struct brw_reg sample_index;
499 /* MRF used for sampling and render target writes */
503 brw_blorp_blit_program::brw_blorp_blit_program(
504 struct brw_context *brw,
505 const brw_blorp_blit_prog_key *key)
506 : mem_ctx(ralloc_context(NULL)),
510 brw_init_compile(brw, &func, mem_ctx);
513 brw_blorp_blit_program::~brw_blorp_blit_program()
515 ralloc_free(mem_ctx);
519 brw_blorp_blit_program::compile(struct brw_context *brw,
520 GLuint *program_size)
523 if (key->dst_tiled_w && key->rt_samples > 0) {
524 /* If the destination image is W tiled and multisampled, then the thread
525 * must be dispatched once per sample, not once per pixel. This is
526 * necessary because after conversion between W and Y tiling, there's no
527 * guarantee that all samples corresponding to a single pixel will still
530 assert(key->persample_msaa_dispatch);
534 /* We are blending, which means we won't have an opportunity to
535 * translate the tiling and sample count for the texture surface. So
536 * the surface state for the texture must be configured with the correct
537 * tiling and sample count.
539 assert(!key->src_tiled_w);
540 assert(key->tex_samples == key->src_samples);
541 assert(key->tex_layout == key->src_layout);
542 assert(key->tex_samples > 0);
545 if (key->persample_msaa_dispatch) {
546 /* It only makes sense to do persample dispatch if the render target is
547 * configured as multisampled.
549 assert(key->rt_samples > 0);
552 /* Make sure layout is consistent with sample count */
553 assert((key->tex_layout == INTEL_MSAA_LAYOUT_NONE) ==
554 (key->tex_samples == 0));
555 assert((key->rt_layout == INTEL_MSAA_LAYOUT_NONE) ==
556 (key->rt_samples == 0));
557 assert((key->src_layout == INTEL_MSAA_LAYOUT_NONE) ==
558 (key->src_samples == 0));
559 assert((key->dst_layout == INTEL_MSAA_LAYOUT_NONE) ==
560 (key->dst_samples == 0));
562 /* Set up prog_data */
563 memset(&prog_data, 0, sizeof(prog_data));
564 prog_data.persample_msaa_dispatch = key->persample_msaa_dispatch;
566 brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
569 compute_frag_coords();
571 /* Render target and texture hardware don't support W tiling. */
572 const bool rt_tiled_w = false;
573 const bool tex_tiled_w = false;
575 /* The address that data will be written to is determined by the
576 * coordinates supplied to the WM thread and the tiling and sample count of
577 * the render target, according to the formula:
579 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
581 * If the actual tiling and sample count of the destination surface are not
582 * the same as the configuration of the render target, then these
583 * coordinates are wrong and we have to adjust them to compensate for the
586 if (rt_tiled_w != key->dst_tiled_w ||
587 key->rt_samples != key->dst_samples ||
588 key->rt_layout != key->dst_layout) {
589 encode_msaa(key->rt_samples, key->rt_layout);
590 /* Now (X, Y, S) = detile(rt_tiling, offset) */
591 translate_tiling(rt_tiled_w, key->dst_tiled_w);
592 /* Now (X, Y, S) = detile(dst_tiling, offset) */
593 decode_msaa(key->dst_samples, key->dst_layout);
596 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
598 * That is: X, Y and S now contain the true coordinates and sample index of
599 * the data that the WM thread should output.
601 * If we need to kill pixels that are outside the destination rectangle,
602 * now is the time to do it.
606 kill_if_outside_dst_rect();
608 /* Next, apply a translation to obtain coordinates in the source image. */
609 translate_dst_to_src();
611 /* If the source image is not multisampled, then we want to fetch sample
612 * number 0, because that's the only sample there is.
614 if (key->src_samples == 0)
617 /* X, Y, and S are now the coordinates of the pixel in the source image
618 * that we want to texture from. Exception: if we are blending, then S is
619 * irrelevant, because we are going to fetch all samples.
622 if (brw->intel.gen == 6) {
623 /* Gen6 hardware an automatically blend using the SAMPLE message */
625 sample(texture_data[0]);
627 /* Gen7+ hardware doesn't automaticaly blend. */
631 /* We aren't blending, which means we just want to fetch a single sample
632 * from the source surface. The address that we want to fetch from is
633 * related to the X, Y and S values according to the formula:
635 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
637 * If the actual tiling and sample count of the source surface are not
638 * the same as the configuration of the texture, then we need to adjust
639 * the coordinates to compensate for the difference.
641 if (tex_tiled_w != key->src_tiled_w ||
642 key->tex_samples != key->src_samples ||
643 key->tex_layout != key->src_layout) {
644 encode_msaa(key->src_samples, key->src_layout);
645 /* Now (X, Y, S) = detile(src_tiling, offset) */
646 translate_tiling(key->src_tiled_w, tex_tiled_w);
647 /* Now (X, Y, S) = detile(tex_tiling, offset) */
648 decode_msaa(key->tex_samples, key->tex_layout);
651 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
653 * In other words: X, Y, and S now contain values which, when passed to
654 * the texturing unit, will cause data to be read from the correct
655 * memory location. So we can fetch the texel now.
657 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
659 texel_fetch(texture_data[0]);
662 /* Finally, write the fetched (or blended) value to the render target and
663 * terminate the thread.
665 render_target_write();
666 return brw_get_program(&func, program_size);
670 brw_blorp_blit_program::alloc_push_const_regs(int base_reg)
672 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
673 #define ALLOC_REG(name) \
675 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
681 ALLOC_REG(x_transform.multiplier);
682 ALLOC_REG(x_transform.offset);
683 ALLOC_REG(y_transform.multiplier);
684 ALLOC_REG(y_transform.offset);
690 brw_blorp_blit_program::alloc_regs()
693 this->R0 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW);
694 this->R1 = retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW);
695 prog_data.first_curbe_grf = reg;
696 alloc_push_const_regs(reg);
697 reg += BRW_BLORP_NUM_PUSH_CONST_REGS;
698 for (unsigned i = 0; i < ARRAY_SIZE(texture_data); ++i) {
699 this->texture_data[i] =
700 retype(vec16(brw_vec8_grf(reg, 0)), key->texture_data_type);
704 retype(brw_vec8_grf(reg, 0), BRW_REGISTER_TYPE_UD); reg += 8;
705 for (int i = 0; i < 2; ++i) {
707 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW));
709 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW));
711 this->xy_coord_index = 0;
713 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW));
714 this->t1 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW));
715 this->t2 = vec16(retype(brw_vec8_grf(reg++, 0), BRW_REGISTER_TYPE_UW));
717 /* Make sure we didn't run out of registers */
718 assert(reg <= GEN7_MRF_HACK_START);
721 this->base_mrf = mrf;
724 /* In the code that follows, X and Y can be used to quickly refer to the
725 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
726 * prime") to the inactive elements.
728 * S can be used to quickly refer to sample_index.
730 #define X x_coords[xy_coord_index]
731 #define Y y_coords[xy_coord_index]
732 #define Xp x_coords[!xy_coord_index]
733 #define Yp y_coords[!xy_coord_index]
734 #define S sample_index
736 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
737 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
739 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
742 * Emit code to compute the X and Y coordinates of the pixels being rendered
743 * by this WM invocation.
745 * Assuming the render target is set up for Y tiling, these (X, Y) values are
746 * related to the address offset where outputs will be written by the formula:
748 * (X, Y, S) = decode_msaa(detile(offset)).
750 * (See brw_blorp_blit_program).
753 brw_blorp_blit_program::compute_frag_coords()
755 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
756 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
757 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
758 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
760 * Pixels within a subspan are laid out in this arrangement:
764 * So, to compute the coordinates of each pixel, we need to read every 2nd
765 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
766 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
767 * In other words, the data we want to access is R1.4<2;4,0>UW.
769 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
770 * result, since pixels n+1 and n+3 are in the right half of the subspan.
772 brw_ADD(&func, X, stride(suboffset(R1, 4), 2, 4, 0), brw_imm_v(0x10101010));
774 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
775 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
776 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
779 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
780 * pixels n+2 and n+3 are in the bottom half of the subspan.
782 brw_ADD(&func, Y, stride(suboffset(R1, 5), 2, 4, 0), brw_imm_v(0x11001100));
784 if (key->persample_msaa_dispatch) {
785 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples > 0.
786 * Therefore, subspan 0 will represent sample 0, subspan 1 will
787 * represent sample 1, and so on.
789 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1, 1,
790 * 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to populate a
791 * temporary variable with the sequence (0, 1, 2, 3), and then copy from
792 * it using vstride=1, width=4, hstride=0.
794 * TODO: implement the necessary calculation for 8x multisampling.
796 brw_MOV(&func, t1, brw_imm_v(0x3210));
797 brw_MOV(&func, S, stride(t1, 1, 4, 0));
800 /* Either the destination surface is single-sampled, or the WM will be
801 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
802 * per pixel). In either case, it's not meaningful to compute a sample
803 * value. Just set it to 0.
810 * Emit code to compensate for the difference between Y and W tiling.
812 * This code modifies the X and Y coordinates according to the formula:
814 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
816 * (See brw_blorp_blit_program).
818 * It can only translate between W and Y tiling, so new_tiling and old_tiling
819 * are booleans where true represents W tiling and false represents Y tiling.
822 brw_blorp_blit_program::translate_tiling(bool old_tiled_w, bool new_tiled_w)
824 if (old_tiled_w == new_tiled_w)
827 /* In the code that follows, we can safely assume that S = 0, because W
828 * tiling formats always use IMS layout.
833 /* Given X and Y coordinates that describe an address using Y tiling,
834 * translate to the X and Y coordinates that describe the same address
837 * If we break down the low order bits of X and Y, using a
838 * single letter to represent each low-order bit:
840 * X = A << 7 | 0bBCDEFGH
841 * Y = J << 5 | 0bKLMNP (1)
843 * Then we can apply the Y tiling formula to see the memory offset being
846 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
848 * If we apply the W detiling formula to this memory location, that the
849 * corresponding X' and Y' coordinates are:
851 * X' = A << 6 | 0bBCDPFH (3)
852 * Y' = J << 6 | 0bKLMNEG
854 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
855 * we need to make the following computation:
857 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
858 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
860 brw_AND(&func, t1, X, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
861 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
862 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
863 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
864 brw_OR(&func, t1, t1, t2); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
865 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
866 brw_OR(&func, Xp, t1, t2);
867 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
868 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
869 brw_AND(&func, t2, X, brw_imm_uw(8)); /* X & 0b1000 */
870 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
871 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
872 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */
873 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
874 brw_OR(&func, Yp, t1, t2);
877 /* Applying the same logic as above, but in reverse, we obtain the
880 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
881 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
883 brw_AND(&func, t1, X, brw_imm_uw(0xfffa)); /* X & ~0b101 */
884 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
885 brw_AND(&func, t2, Y, brw_imm_uw(2)); /* Y & 0b10 */
886 brw_SHL(&func, t2, t2, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
887 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
888 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
889 brw_SHL(&func, t2, t2, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
890 brw_OR(&func, t1, t1, t2); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
892 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
893 brw_OR(&func, Xp, t1, t2);
894 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
895 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
896 brw_AND(&func, t2, X, brw_imm_uw(4)); /* X & 0b100 */
897 brw_SHR(&func, t2, t2, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
898 brw_OR(&func, Yp, t1, t2);
904 * Emit code to compensate for the difference between MSAA and non-MSAA
907 * This code modifies the X and Y coordinates according to the formula:
909 * (X', Y', S') = encode_msaa_4x(X, Y, S)
911 * (See brw_blorp_blit_program).
914 brw_blorp_blit_program::encode_msaa(unsigned num_samples,
915 intel_msaa_layout layout)
918 case INTEL_MSAA_LAYOUT_NONE:
919 /* No translation necessary, and S should already be zero. */
922 case INTEL_MSAA_LAYOUT_CMS:
923 /* We can't compensate for compressed layout since at this point in the
924 * program we haven't read from the MCS buffer.
926 assert(!"Bad layout in encode_msaa");
928 case INTEL_MSAA_LAYOUT_UMS:
929 /* No translation necessary. */
931 case INTEL_MSAA_LAYOUT_IMS:
932 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
933 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
934 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
936 brw_AND(&func, t1, X, brw_imm_uw(0xfffe)); /* X & ~0b1 */
938 brw_AND(&func, t2, S, brw_imm_uw(1)); /* S & 0b1 */
939 brw_OR(&func, t1, t1, t2); /* (X & ~0b1) | (S & 0b1) */
941 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b1) << 1
943 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
944 brw_OR(&func, Xp, t1, t2);
945 brw_AND(&func, t1, Y, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
946 brw_SHL(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
948 brw_AND(&func, t2, S, brw_imm_uw(2)); /* S & 0b10 */
949 brw_OR(&func, t1, t1, t2); /* (Y & ~0b1) << 1 | (S & 0b10) */
951 brw_AND(&func, t2, Y, brw_imm_uw(1));
952 brw_OR(&func, Yp, t1, t2);
960 * Emit code to compensate for the difference between MSAA and non-MSAA
963 * This code modifies the X and Y coordinates according to the formula:
965 * (X', Y', S) = decode_msaa(num_samples, X, Y, S)
967 * (See brw_blorp_blit_program).
970 brw_blorp_blit_program::decode_msaa(unsigned num_samples,
971 intel_msaa_layout layout)
974 case INTEL_MSAA_LAYOUT_NONE:
975 /* No translation necessary, and S should already be zero. */
978 case INTEL_MSAA_LAYOUT_CMS:
979 /* We can't compensate for compressed layout since at this point in the
980 * program we don't have access to the MCS buffer.
982 assert(!"Bad layout in encode_msaa");
984 case INTEL_MSAA_LAYOUT_UMS:
985 /* No translation necessary. */
987 case INTEL_MSAA_LAYOUT_IMS:
988 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
989 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
990 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
991 * S = (Y & 0b10) | (X & 0b10) >> 1
994 brw_AND(&func, t1, X, brw_imm_uw(0xfffc)); /* X & ~0b11 */
995 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
996 brw_AND(&func, t2, X, brw_imm_uw(1)); /* X & 0b1 */
997 brw_OR(&func, Xp, t1, t2);
998 brw_AND(&func, t1, Y, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
999 brw_SHR(&func, t1, t1, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1000 brw_AND(&func, t2, Y, brw_imm_uw(1)); /* Y & 0b1 */
1001 brw_OR(&func, Yp, t1, t2);
1002 brw_AND(&func, t1, Y, brw_imm_uw(2)); /* Y & 0b10 */
1003 brw_AND(&func, t2, X, brw_imm_uw(2)); /* X & 0b10 */
1004 brw_SHR(&func, t2, t2, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1005 brw_OR(&func, S, t1, t2);
1013 * Emit code that kills pixels whose X and Y coordinates are outside the
1014 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1018 brw_blorp_blit_program::kill_if_outside_dst_rect()
1020 struct brw_reg f0 = brw_flag_reg();
1021 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1022 struct brw_reg null16 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
1024 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, X, dst_x0);
1025 brw_CMP(&func, null16, BRW_CONDITIONAL_GE, Y, dst_y0);
1026 brw_CMP(&func, null16, BRW_CONDITIONAL_L, X, dst_x1);
1027 brw_CMP(&func, null16, BRW_CONDITIONAL_L, Y, dst_y1);
1029 brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
1030 brw_push_insn_state(&func);
1031 brw_set_mask_control(&func, BRW_MASK_DISABLE);
1032 brw_AND(&func, g1, f0, g1);
1033 brw_pop_insn_state(&func);
1037 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1041 brw_blorp_blit_program::translate_dst_to_src()
1043 brw_MUL(&func, Xp, X, x_transform.multiplier);
1044 brw_MUL(&func, Yp, Y, y_transform.multiplier);
1045 brw_ADD(&func, Xp, Xp, x_transform.offset);
1046 brw_ADD(&func, Yp, Yp, y_transform.offset);
1051 * Emit code to transform the X and Y coordinates as needed for blending
1052 * together the different samples in an MSAA texture.
1055 brw_blorp_blit_program::single_to_blend()
1057 /* When looking up samples in an MSAA texture using the SAMPLE message,
1058 * Gen6 requires the texture coordinates to be odd integers (so that they
1059 * correspond to the center of a 2x2 block representing the four samples
1060 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1061 * each by 2 and then add 1.
1063 brw_SHL(&func, t1, X, brw_imm_w(1));
1064 brw_SHL(&func, t2, Y, brw_imm_w(1));
1065 brw_ADD(&func, Xp, t1, brw_imm_w(1));
1066 brw_ADD(&func, Yp, t2, brw_imm_w(1));
1072 * Count the number of trailing 1 bits in the given value. For example:
1074 * count_trailing_one_bits(0) == 0
1075 * count_trailing_one_bits(7) == 3
1076 * count_trailing_one_bits(11) == 2
1078 inline int count_trailing_one_bits(unsigned value)
1080 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1081 return __builtin_ctz(~value);
1083 return _mesa_bitcount(value & ~(value + 1));
1089 brw_blorp_blit_program::manual_blend()
1091 /* TODO: support num_samples != 4 */
1092 const int num_samples = 4;
1094 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
1097 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1099 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1101 * This ensures that when all samples have the same value, no numerical
1102 * precision is lost, since each addition operation always adds two equal
1103 * values, and summing two equal floating point values does not lose
1106 * We perform this computation by treating the texture_data array as a
1107 * stack and performing the following operations:
1109 * - push sample 0 onto stack
1110 * - push sample 1 onto stack
1111 * - add top two stack entries
1112 * - push sample 2 onto stack
1113 * - push sample 3 onto stack
1114 * - add top two stack entries
1115 * - add top two stack entries
1116 * - divide top stack entry by 4
1118 * Note that after pushing sample i onto the stack, the number of add
1119 * operations we do is equal to the number of trailing 1 bits in i. This
1120 * works provided the total number of samples is a power of two, which it
1121 * always is for i965.
1123 * For integer formats, we replace the add operations with average
1124 * operations and skip the final division.
1126 typedef struct brw_instruction *(*brw_op2_ptr)(struct brw_compile *,
1130 brw_op2_ptr combine_op =
1131 key->texture_data_type == BRW_REGISTER_TYPE_F ? brw_ADD : brw_AVG;
1132 unsigned stack_depth = 0;
1133 for (int i = 0; i < num_samples; ++i) {
1134 assert(stack_depth == _mesa_bitcount(i)); /* Loop invariant */
1136 /* Push sample i onto the stack */
1137 assert(stack_depth < ARRAY_SIZE(texture_data));
1142 brw_MOV(&func, S, brw_imm_uw(i));
1144 texel_fetch(texture_data[stack_depth++]);
1146 if (i == 0 && key->tex_layout == INTEL_MSAA_LAYOUT_CMS) {
1147 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1148 * suggests an optimization:
1150 * "A simple optimization with probable large return in
1151 * performance is to compare the MCS value to zero (indicating
1152 * all samples are on sample slice 0), and sample only from
1153 * sample slice 0 using ld2dss if MCS is zero."
1155 * Note that in the case where the MCS value is zero, sampling from
1156 * sample slice 0 using ld2dss and sampling from sample 0 using
1157 * ld2dms are equivalent (since all samples are on sample slice 0).
1158 * Since we have already sampled from sample 0, all we need to do is
1159 * skip the remaining fetches and averaging if MCS is zero.
1161 brw_CMP(&func, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ,
1162 mcs_data, brw_imm_ud(0));
1163 brw_IF(&func, BRW_EXECUTE_16);
1166 /* Do count_trailing_one_bits(i) times */
1167 for (int j = count_trailing_one_bits(i); j-- > 0; ) {
1168 assert(stack_depth >= 2);
1171 /* TODO: should use a smaller loop bound for non_RGBA formats */
1172 for (int k = 0; k < 4; ++k) {
1173 combine_op(&func, offset(texture_data[stack_depth - 1], 2*k),
1174 offset(vec8(texture_data[stack_depth - 1]), 2*k),
1175 offset(vec8(texture_data[stack_depth]), 2*k));
1180 /* We should have just 1 sample on the stack now. */
1181 assert(stack_depth == 1);
1183 if (key->texture_data_type == BRW_REGISTER_TYPE_F) {
1184 /* Scale the result down by a factor of num_samples */
1185 /* TODO: should use a smaller loop bound for non-RGBA formats */
1186 for (int j = 0; j < 4; ++j) {
1187 brw_MUL(&func, offset(texture_data[0], 2*j),
1188 offset(vec8(texture_data[0]), 2*j),
1189 brw_imm_f(1.0/num_samples));
1193 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS)
1198 * Emit code to look up a value in the texture using the SAMPLE message (which
1199 * does blending of MSAA surfaces).
1202 brw_blorp_blit_program::sample(struct brw_reg dst)
1204 static const sampler_message_arg args[2] = {
1205 SAMPLER_MESSAGE_ARG_U_FLOAT,
1206 SAMPLER_MESSAGE_ARG_V_FLOAT
1209 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE, args, ARRAY_SIZE(args));
1213 * Emit code to look up a value in the texture using the SAMPLE_LD message
1214 * (which does a simple texel fetch).
1217 brw_blorp_blit_program::texel_fetch(struct brw_reg dst)
1219 static const sampler_message_arg gen6_args[5] = {
1220 SAMPLER_MESSAGE_ARG_U_INT,
1221 SAMPLER_MESSAGE_ARG_V_INT,
1222 SAMPLER_MESSAGE_ARG_ZERO_INT, /* R */
1223 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */
1224 SAMPLER_MESSAGE_ARG_SI_INT
1226 static const sampler_message_arg gen7_ld_args[3] = {
1227 SAMPLER_MESSAGE_ARG_U_INT,
1228 SAMPLER_MESSAGE_ARG_ZERO_INT, /* LOD */
1229 SAMPLER_MESSAGE_ARG_V_INT
1231 static const sampler_message_arg gen7_ld2dss_args[3] = {
1232 SAMPLER_MESSAGE_ARG_SI_INT,
1233 SAMPLER_MESSAGE_ARG_U_INT,
1234 SAMPLER_MESSAGE_ARG_V_INT
1236 static const sampler_message_arg gen7_ld2dms_args[4] = {
1237 SAMPLER_MESSAGE_ARG_SI_INT,
1238 SAMPLER_MESSAGE_ARG_MCS_INT,
1239 SAMPLER_MESSAGE_ARG_U_INT,
1240 SAMPLER_MESSAGE_ARG_V_INT
1243 switch (brw->intel.gen) {
1245 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen6_args,
1249 if (key->tex_samples > 0) {
1250 if (key->tex_layout == INTEL_MSAA_LAYOUT_CMS) {
1251 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS,
1252 gen7_ld2dms_args, ARRAY_SIZE(gen7_ld2dms_args));
1254 texture_lookup(dst, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS,
1255 gen7_ld2dss_args, ARRAY_SIZE(gen7_ld2dss_args));
1259 texture_lookup(dst, GEN5_SAMPLER_MESSAGE_SAMPLE_LD, gen7_ld_args,
1260 ARRAY_SIZE(gen7_ld_args));
1264 assert(!"Should not get here.");
1270 brw_blorp_blit_program::mcs_fetch()
1272 static const sampler_message_arg gen7_ld_mcs_args[2] = {
1273 SAMPLER_MESSAGE_ARG_U_INT,
1274 SAMPLER_MESSAGE_ARG_V_INT
1276 texture_lookup(vec16(mcs_data), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS,
1277 gen7_ld_mcs_args, ARRAY_SIZE(gen7_ld_mcs_args));
1281 brw_blorp_blit_program::expand_to_32_bits(struct brw_reg src,
1284 brw_MOV(&func, vec8(dst), vec8(src));
1285 brw_set_compression_control(&func, BRW_COMPRESSION_2NDHALF);
1286 brw_MOV(&func, offset(vec8(dst), 1), suboffset(vec8(src), 8));
1287 brw_set_compression_control(&func, BRW_COMPRESSION_NONE);
1291 brw_blorp_blit_program::texture_lookup(struct brw_reg dst,
1293 const sampler_message_arg *args,
1296 struct brw_reg mrf =
1297 retype(vec16(brw_message_reg(base_mrf)), BRW_REGISTER_TYPE_UD);
1298 for (int arg = 0; arg < num_args; ++arg) {
1299 switch (args[arg]) {
1300 case SAMPLER_MESSAGE_ARG_U_FLOAT:
1301 expand_to_32_bits(X, retype(mrf, BRW_REGISTER_TYPE_F));
1303 case SAMPLER_MESSAGE_ARG_V_FLOAT:
1304 expand_to_32_bits(Y, retype(mrf, BRW_REGISTER_TYPE_F));
1306 case SAMPLER_MESSAGE_ARG_U_INT:
1307 expand_to_32_bits(X, mrf);
1309 case SAMPLER_MESSAGE_ARG_V_INT:
1310 expand_to_32_bits(Y, mrf);
1312 case SAMPLER_MESSAGE_ARG_SI_INT:
1313 /* Note: on Gen7, this code may be reached with s_is_zero==true
1314 * because in Gen7's ld2dss message, the sample index is the first
1315 * argument. When this happens, we need to move a 0 into the
1316 * appropriate message register.
1319 brw_MOV(&func, mrf, brw_imm_ud(0));
1321 expand_to_32_bits(S, mrf);
1323 case SAMPLER_MESSAGE_ARG_MCS_INT:
1324 brw_MOV(&func, mrf, mcs_data);
1326 case SAMPLER_MESSAGE_ARG_ZERO_INT:
1327 brw_MOV(&func, mrf, brw_imm_ud(0));
1334 retype(dst, BRW_REGISTER_TYPE_UW) /* dest */,
1335 base_mrf /* msg_reg_nr */,
1336 brw_message_reg(base_mrf) /* src0 */,
1337 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
1341 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1342 mrf.nr - base_mrf /* msg_length */,
1343 0 /* header_present */,
1344 BRW_SAMPLER_SIMD_MODE_SIMD16,
1345 BRW_SAMPLER_RETURN_FORMAT_FLOAT32);
1353 #undef SWAP_XY_AND_XPYP
1356 brw_blorp_blit_program::render_target_write()
1358 struct brw_reg mrf_rt_write =
1359 retype(vec16(brw_message_reg(base_mrf)), key->texture_data_type);
1362 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1363 * so that the render target knows which pixels we killed.
1365 bool use_header = key->use_kill;
1367 /* Copy R0/1 to MRF */
1368 brw_MOV(&func, retype(mrf_rt_write, BRW_REGISTER_TYPE_UD),
1369 retype(R0, BRW_REGISTER_TYPE_UD));
1373 /* Copy texture data to MRFs */
1374 for (int i = 0; i < 4; ++i) {
1375 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1376 brw_MOV(&func, offset(mrf_rt_write, mrf_offset),
1377 offset(vec8(texture_data[0]), 2*i));
1381 /* Now write to the render target and terminate the thread */
1383 16 /* dispatch_width */,
1384 base_mrf /* msg_reg_nr */,
1385 mrf_rt_write /* src0 */,
1386 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
1387 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
1388 mrf_offset /* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1389 0 /* response_length */,
1396 brw_blorp_coord_transform_params::setup(GLuint src0, GLuint dst0, GLuint dst1,
1400 /* When not mirroring a coordinate (say, X), we need:
1401 * x' - src_x0 = x - dst_x0
1403 * x' = 1*x + (src_x0 - dst_x0)
1406 offset = src0 - dst0;
1408 /* When mirroring X we need:
1409 * x' - src_x0 = dst_x1 - x - 1
1411 * x' = -1*x + (src_x0 + dst_x1 - 1)
1414 offset = src0 + dst1 - 1;
1420 * Determine which MSAA layout the GPU pipeline should be configured for,
1421 * based on the chip generation, the number of samples, and the true layout of
1422 * the image in memory.
1424 inline intel_msaa_layout
1425 compute_msaa_layout_for_pipeline(struct brw_context *brw, unsigned num_samples,
1426 intel_msaa_layout true_layout)
1428 if (num_samples == 0) {
1429 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1430 * format buffers, by transforming coordinates appropriately.
1432 assert(true_layout == INTEL_MSAA_LAYOUT_NONE ||
1433 true_layout == INTEL_MSAA_LAYOUT_IMS);
1434 return INTEL_MSAA_LAYOUT_NONE;
1437 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1438 if (brw->intel.gen == 6) {
1439 assert(true_layout == INTEL_MSAA_LAYOUT_IMS);
1440 return INTEL_MSAA_LAYOUT_IMS;
1443 /* Since blorp uses color textures and render targets to do all its work
1444 * (even when blitting stencil and depth data), we always have to configure
1445 * the Gen7 GPU to use UMS or CMS layout on Gen7.
1447 assert(true_layout == INTEL_MSAA_LAYOUT_UMS ||
1448 true_layout == INTEL_MSAA_LAYOUT_CMS);
1453 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context *brw,
1454 struct intel_mipmap_tree *src_mt,
1455 struct intel_mipmap_tree *dst_mt,
1456 GLuint src_x0, GLuint src_y0,
1457 GLuint dst_x0, GLuint dst_y0,
1458 GLuint dst_x1, GLuint dst_y1,
1459 bool mirror_x, bool mirror_y)
1461 src.set(brw, src_mt, 0, 0);
1462 dst.set(brw, dst_mt, 0, 0);
1465 memset(&wm_prog_key, 0, sizeof(wm_prog_key));
1467 /* texture_data_type indicates the register type that should be used to
1468 * manipulate texture data.
1470 switch (_mesa_get_format_datatype(src_mt->format)) {
1471 case GL_UNSIGNED_NORMALIZED:
1472 case GL_SIGNED_NORMALIZED:
1474 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
1476 case GL_UNSIGNED_INT:
1477 if (src_mt->format == MESA_FORMAT_S8) {
1478 /* We process stencil as though it's an unsigned normalized color */
1479 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_F;
1481 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_UD;
1485 wm_prog_key.texture_data_type = BRW_REGISTER_TYPE_D;
1488 assert(!"Unrecognized blorp format");
1492 if (brw->intel.gen > 6) {
1493 /* Gen7's texturing hardware only supports the IMS layout with the
1494 * ld2dms instruction (which blorp doesn't use). So if the source is
1495 * IMS, we'll have to map it as a single-sampled texture and
1496 * de-interleave the samples ourselves.
1498 if (src_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS)
1499 src.num_samples = 0;
1501 /* Similarly, Gen7's rendering hardware only supports the IMS layout for
1502 * depth and stencil render targets. Blorp always maps its destination
1503 * surface as a color render target (even if it's actually a depth or
1504 * stencil buffer). So if the destination is IMS, we'll have to map it
1505 * as a single-sampled texture and interleave the samples ourselves.
1507 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS)
1508 dst.num_samples = 0;
1511 if (dst.map_stencil_as_y_tiled && dst.num_samples > 0) {
1512 /* If the destination surface is a W-tiled multisampled stencil buffer
1513 * that we're mapping as Y tiled, then we need to arrange for the WM
1514 * program to run once per sample rather than once per pixel, because
1515 * the memory layout of related samples doesn't match between W and Y
1518 wm_prog_key.persample_msaa_dispatch = true;
1521 if (src.num_samples > 0 && dst.num_samples > 0) {
1522 /* We are blitting from a multisample buffer to a multisample buffer, so
1523 * we must preserve samples within a pixel. This means we have to
1524 * arrange for the WM program to run once per sample rather than once
1527 wm_prog_key.persample_msaa_dispatch = true;
1530 /* The render path must be configured to use the same number of samples as
1531 * the destination buffer.
1533 num_samples = dst.num_samples;
1535 GLenum base_format = _mesa_get_format_base_format(src_mt->format);
1536 if (base_format != GL_DEPTH_COMPONENT && /* TODO: what about depth/stencil? */
1537 base_format != GL_STENCIL_INDEX &&
1538 src_mt->num_samples > 0 && dst_mt->num_samples == 0) {
1539 /* We are downsampling a color buffer, so blend. */
1540 wm_prog_key.blend = true;
1543 /* src_samples and dst_samples are the true sample counts */
1544 wm_prog_key.src_samples = src_mt->num_samples;
1545 wm_prog_key.dst_samples = dst_mt->num_samples;
1547 /* tex_samples and rt_samples are the sample counts that are set up in
1550 wm_prog_key.tex_samples = src.num_samples;
1551 wm_prog_key.rt_samples = dst.num_samples;
1553 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1554 * use to access the source and destination surfaces.
1556 wm_prog_key.tex_layout =
1557 compute_msaa_layout_for_pipeline(brw, src.num_samples, src.msaa_layout);
1558 wm_prog_key.rt_layout =
1559 compute_msaa_layout_for_pipeline(brw, dst.num_samples, dst.msaa_layout);
1561 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1564 wm_prog_key.src_layout = src_mt->msaa_layout;
1565 wm_prog_key.dst_layout = dst_mt->msaa_layout;
1567 wm_prog_key.src_tiled_w = src.map_stencil_as_y_tiled;
1568 wm_prog_key.dst_tiled_w = dst.map_stencil_as_y_tiled;
1569 x0 = wm_push_consts.dst_x0 = dst_x0;
1570 y0 = wm_push_consts.dst_y0 = dst_y0;
1571 x1 = wm_push_consts.dst_x1 = dst_x1;
1572 y1 = wm_push_consts.dst_y1 = dst_y1;
1573 wm_push_consts.x_transform.setup(src_x0, dst_x0, dst_x1, mirror_x);
1574 wm_push_consts.y_transform.setup(src_y0, dst_y0, dst_y1, mirror_y);
1576 if (dst.num_samples == 0 && dst_mt->num_samples > 0) {
1577 /* We must expand the rectangle we send through the rendering pipeline,
1578 * to account for the fact that we are mapping the destination region as
1579 * single-sampled when it is in fact multisampled. We must also align
1580 * it to a multiple of the multisampling pattern, because the
1581 * differences between multisampled and single-sampled surface formats
1582 * will mean that pixels are scrambled within the multisampling pattern.
1583 * TODO: what if this makes the coordinates too large?
1585 * Note: this only works if the destination surface uses the IMS layout.
1586 * If it's UMS, then we have no choice but to set up the rendering
1587 * pipeline as multisampled.
1589 assert(dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS);
1592 x1 = ALIGN(x1 * 2, 4);
1593 y1 = ALIGN(y1 * 2, 4);
1594 wm_prog_key.use_kill = true;
1597 if (dst.map_stencil_as_y_tiled) {
1598 /* We must modify the rectangle we send through the rendering pipeline,
1599 * to account for the fact that we are mapping it as Y-tiled when it is
1600 * in fact W-tiled. Y tiles have dimensions 128x32 whereas W tiles have
1601 * dimensions 64x64. We must also align it to a multiple of the tile
1602 * size, because the differences between W and Y tiling formats will
1603 * mean that pixels are scrambled within the tile.
1605 * Note: if the destination surface configured to use IMS layout, then
1606 * the effective tile size we need to align it to is smaller, because
1607 * each pixel covers a 2x2 or a 4x2 block of samples.
1609 * TODO: what if this makes the coordinates too large?
1611 unsigned x_align = 64, y_align = 64;
1612 if (dst_mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
1613 x_align /= (dst_mt->num_samples == 4 ? 2 : 4);
1616 x0 = (x0 & ~(x_align - 1)) * 2;
1617 y0 = (y0 & ~(y_align - 1)) / 2;
1618 x1 = ALIGN(x1, x_align) * 2;
1619 y1 = ALIGN(y1, y_align) / 2;
1620 wm_prog_key.use_kill = true;
1625 brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
1626 brw_blorp_prog_data **prog_data) const
1628 uint32_t prog_offset;
1629 if (!brw_search_cache(&brw->cache, BRW_BLORP_BLIT_PROG,
1630 &this->wm_prog_key, sizeof(this->wm_prog_key),
1631 &prog_offset, prog_data)) {
1632 brw_blorp_blit_program prog(brw, &this->wm_prog_key);
1633 GLuint program_size;
1634 const GLuint *program = prog.compile(brw, &program_size);
1635 brw_upload_cache(&brw->cache, BRW_BLORP_BLIT_PROG,
1636 &this->wm_prog_key, sizeof(this->wm_prog_key),
1637 program, program_size,
1638 &prog.prog_data, sizeof(prog.prog_data),
1639 &prog_offset, prog_data);