src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/imports.h"
  33 #include "main/macros.h"
  34 #include "main/colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_regions.h"
  41 #include "intel_tris.h"
  42 #include "intel_fbo.h"
  43
  44 #include "i915_reg.h"
  45 #include "i915_context.h"
  46
  47 static void
  48 i915_render_prevalidate(struct intel_context *intel)
  49 {
  50    struct i915_context *i915 = i915_context(&intel->ctx);
  51
  52    i915ValidateFragmentProgram(i915);
  53 }
  54
  55 static void
  56 i915_render_start(struct intel_context *intel)
  57 {
  58    intel_prepare_render(intel);
  59 }
  60
  61
  62 static void
  63 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  64 {
  65    struct i915_context *i915 = i915_context(&intel->ctx);
  66    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  67
  68    st1 &= ~ST1_ENABLE;
  69
  70    switch (rprim) {
  71    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  72    case GL_TRIANGLES:
  73       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  74          st1 |= ST1_ENABLE;
  75       break;
  76    case GL_LINES:
  77    case GL_POINTS:
  78    default:
  79       break;
  80    }
  81
  82    i915->intel.reduced_primitive = rprim;
  83
  84    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  85       INTEL_FIREVERTICES(intel);
  86
  87       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  88       i915->state.Stipple[I915_STPREG_ST1] = st1;
  89    }
  90 }
  91
  92
  93 /* Pull apart the vertex format registers and figure out how large a
  94  * vertex is supposed to be.
  95  */
  96 static GLboolean
  97 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
  98 {
  99    struct i915_context *i915 = i915_context(&intel->ctx);
 100    int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
 101    int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
 102    int i, sz = 0;
 103
 104    switch (lis4 & S4_VFMT_XYZW_MASK) {
 105    case S4_VFMT_XY:
 106       sz = 2;
 107       break;
 108    case S4_VFMT_XYZ:
 109       sz = 3;
 110       break;
 111    case S4_VFMT_XYW:
 112       sz = 3;
 113       break;
 114    case S4_VFMT_XYZW:
 115       sz = 4;
 116       break;
 117    default:
 118       fprintf(stderr, "no xyzw specified\n");
 119       return 0;
 120    }
 121
 122    if (lis4 & S4_VFMT_SPEC_FOG)
 123       sz++;
 124    if (lis4 & S4_VFMT_COLOR)
 125       sz++;
 126    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 127       sz++;
 128    if (lis4 & S4_VFMT_POINT_WIDTH)
 129       sz++;
 130    if (lis4 & S4_VFMT_FOG_PARAM)
 131       sz++;
 132
 133    for (i = 0; i < 8; i++) {
 134       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 135       case TEXCOORDFMT_2D:
 136          sz += 2;
 137          break;
 138       case TEXCOORDFMT_3D:
 139          sz += 3;
 140          break;
 141       case TEXCOORDFMT_4D:
 142          sz += 4;
 143          break;
 144       case TEXCOORDFMT_1D:
 145          sz += 1;
 146          break;
 147       case TEXCOORDFMT_2D_16:
 148          sz += 1;
 149          break;
 150       case TEXCOORDFMT_4D_16:
 151          sz += 2;
 152          break;
 153       case TEXCOORDFMT_NOT_PRESENT:
 154          break;
 155       default:
 156          fprintf(stderr, "bad texcoord fmt %d\n", i);
 157          return GL_FALSE;
 158       }
 159       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 160    }
 161
 162    if (sz != expected)
 163       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 164
 165    return sz == expected;
 166 }
 167
 168
 169 static void
 170 i915_emit_invarient_state(struct intel_context *intel)
 171 {
 172    BATCH_LOCALS;
 173
 174    BEGIN_BATCH(17);
 175
 176    OUT_BATCH(_3DSTATE_AA_CMD |
 177              AA_LINE_ECAAR_WIDTH_ENABLE |
 178              AA_LINE_ECAAR_WIDTH_1_0 |
 179              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 180
 181    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 182    OUT_BATCH(0);
 183
 184    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 185    OUT_BATCH(0);
 186
 187    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 188    OUT_BATCH(0);
 189
 190    /* Don't support texture crossbar yet */
 191    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 192              CSB_TCB(0, 0) |
 193              CSB_TCB(1, 1) |
 194              CSB_TCB(2, 2) |
 195              CSB_TCB(3, 3) |
 196              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 197
 198    /* Need to initialize this to zero.
 199     */
 200    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 201    OUT_BATCH(0);
 202
 203    /* XXX: Use this */
 204    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 205
 206    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 207    OUT_BATCH(0);
 208    OUT_BATCH(0);
 209
 210    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 211
 212    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 213    OUT_BATCH(0);
 214
 215    ADVANCE_BATCH();
 216 }
 217
 218
 219 #define emit(intel, state, size )                    \
 220    intel_batchbuffer_data(intel, state, size, false)
 221
 222 static GLuint
 223 get_dirty(struct i915_hw_state *state)
 224 {
 225    GLuint dirty;
 226
 227    /* Workaround the multitex hang - if one texture unit state is
 228     * modified, emit all texture units.
 229     */
 230    dirty = state->active & ~state->emitted;
 231    if (dirty & I915_UPLOAD_TEX_ALL)
 232       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 233    dirty = state->active & ~state->emitted;
 234    return dirty;
 235 }
 236
 237
 238 static GLuint
 239 get_state_size(struct i915_hw_state *state)
 240 {
 241    GLuint dirty = get_dirty(state);
 242    GLuint i;
 243    GLuint sz = 0;
 244
 245    if (dirty & I915_UPLOAD_INVARIENT)
 246       sz += 30 * 4;
 247
 248    if (dirty & I915_UPLOAD_RASTER_RULES)
 249       sz += sizeof(state->RasterRules);
 250
 251    if (dirty & I915_UPLOAD_CTX)
 252       sz += sizeof(state->Ctx);
 253
 254    if (dirty & I915_UPLOAD_BLEND)
 255       sz += sizeof(state->Blend);
 256
 257    if (dirty & I915_UPLOAD_BUFFERS)
 258       sz += sizeof(state->Buffer);
 259
 260    if (dirty & I915_UPLOAD_STIPPLE)
 261       sz += sizeof(state->Stipple);
 262
 263    if (dirty & I915_UPLOAD_TEX_ALL) {
 264       int nr = 0;
 265       for (i = 0; i < I915_TEX_UNITS; i++)
 266          if (dirty & I915_UPLOAD_TEX(i))
 267             nr++;
 268
 269       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 270    }
 271
 272    if (dirty & I915_UPLOAD_CONSTANTS)
 273       sz += state->ConstantSize * sizeof(GLuint);
 274
 275    if (dirty & I915_UPLOAD_PROGRAM)
 276       sz += state->ProgramSize * sizeof(GLuint);
 277
 278    return sz;
 279 }
 280
 281 /* Push the state into the sarea and/or texture memory.
 282  */
 283 static void
 284 i915_emit_state(struct intel_context *intel)
 285 {
 286    struct i915_context *i915 = i915_context(&intel->ctx);
 287    struct i915_hw_state *state = &i915->state;
 288    int i, count, aper_count;
 289    GLuint dirty;
 290    drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
 291    GET_CURRENT_CONTEXT(ctx);
 292    BATCH_LOCALS;
 293
 294    /* We don't hold the lock at this point, so want to make sure that
 295     * there won't be a buffer wrap between the state emits and the primitive
 296     * emit header.
 297     *
 298     * It might be better to talk about explicit places where
 299     * scheduling is allowed, rather than assume that it is whenever a
 300     * batchbuffer fills up.
 301     */
 302    intel_batchbuffer_require_space(intel,
 303                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
 304                                    false);
 305    count = 0;
 306  again:
 307    if (intel->batch.bo == NULL) {
 308       _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 309       assert(0);
 310    }
 311    aper_count = 0;
 312    dirty = get_dirty(state);
 313
 314    aper_array[aper_count++] = intel->batch.bo;
 315    if (dirty & I915_UPLOAD_BUFFERS) {
 316       aper_array[aper_count++] = state->draw_region->buffer;
 317       if (state->depth_region)
 318          aper_array[aper_count++] = state->depth_region->buffer;
 319    }
 320
 321    if (dirty & I915_UPLOAD_TEX_ALL) {
 322       for (i = 0; i < I915_TEX_UNITS; i++) {
 323          if (dirty & I915_UPLOAD_TEX(i)) {
 324             if (state->tex_buffer[i]) {
 325                aper_array[aper_count++] = state->tex_buffer[i];
 326             }
 327          }
 328       }
 329    }
 330
 331    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 332        if (count == 0) {
 333            count++;
 334            intel_batchbuffer_flush(intel);
 335            goto again;
 336        } else {
 337            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 338            assert(0);
 339        }
 340    }
 341
 342    /* work out list of buffers to emit */
 343
 344    /* Do this here as we may have flushed the batchbuffer above,
 345     * causing more state to be dirty!
 346     */
 347    dirty = get_dirty(state);
 348    state->emitted |= dirty;
 349    assert(get_dirty(state) == 0);
 350
 351    if (INTEL_DEBUG & DEBUG_STATE)
 352       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 353
 354    if (dirty & I915_UPLOAD_INVARIENT) {
 355       if (INTEL_DEBUG & DEBUG_STATE)
 356          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 357       i915_emit_invarient_state(intel);
 358    }
 359
 360    if (dirty & I915_UPLOAD_RASTER_RULES) {
 361       if (INTEL_DEBUG & DEBUG_STATE)
 362          fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
 363       emit(intel, state->RasterRules, sizeof(state->RasterRules));
 364    }
 365
 366    if (dirty & I915_UPLOAD_CTX) {
 367       if (INTEL_DEBUG & DEBUG_STATE)
 368          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 369
 370       emit(intel, state->Ctx, sizeof(state->Ctx));
 371    }
 372
 373    if (dirty & I915_UPLOAD_BLEND) {
 374       if (INTEL_DEBUG & DEBUG_STATE)
 375          fprintf(stderr, "I915_UPLOAD_BLEND:\n");
 376
 377       emit(intel, state->Blend, sizeof(state->Blend));
 378    }
 379
 380    if (dirty & I915_UPLOAD_BUFFERS) {
 381       GLuint count;
 382
 383       if (INTEL_DEBUG & DEBUG_STATE)
 384          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 385
 386       count = 14;
 387       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 388          count++;
 389       if (state->depth_region)
 390          count += 3;
 391
 392       BEGIN_BATCH(count);
 393       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 394       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 395       OUT_RELOC(state->draw_region->buffer,
 396                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 397
 398       if (state->depth_region) {
 399          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 400          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 401          OUT_RELOC(state->depth_region->buffer,
 402                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 403       }
 404
 405       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 406       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 407       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 408       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 409       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 410       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 411
 412       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 413          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 414       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 415       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 416       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 417       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 418       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 419
 420       ADVANCE_BATCH();
 421    }
 422
 423    if (dirty & I915_UPLOAD_STIPPLE) {
 424       if (INTEL_DEBUG & DEBUG_STATE)
 425          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 426       emit(intel, state->Stipple, sizeof(state->Stipple));
 427    }
 428
 429    /* Combine all the dirty texture state into a single command to
 430     * avoid lockups on I915 hardware.
 431     */
 432    if (dirty & I915_UPLOAD_TEX_ALL) {
 433       int nr = 0;
 434       GLuint unwind;
 435
 436       for (i = 0; i < I915_TEX_UNITS; i++)
 437          if (dirty & I915_UPLOAD_TEX(i))
 438             nr++;
 439
 440       BEGIN_BATCH(2 + nr * 3);
 441       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 442       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 443       for (i = 0; i < I915_TEX_UNITS; i++)
 444          if (dirty & I915_UPLOAD_TEX(i)) {
 445             OUT_RELOC(state->tex_buffer[i],
 446                       I915_GEM_DOMAIN_SAMPLER, 0,
 447                       state->tex_offset[i]);
 448
 449             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 450             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 451          }
 452       ADVANCE_BATCH();
 453
 454       unwind = intel->batch.used;
 455       BEGIN_BATCH(2 + nr * 3);
 456       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 457       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 458       for (i = 0; i < I915_TEX_UNITS; i++)
 459          if (dirty & I915_UPLOAD_TEX(i)) {
 460             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 461             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 462             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 463          }
 464       ADVANCE_BATCH();
 465       if (i915->last_sampler &&
 466           memcmp(intel->batch.map + i915->last_sampler,
 467                  intel->batch.map + unwind,
 468                  (2 + nr*3)*sizeof(int)) == 0)
 469           intel->batch.used = unwind;
 470       else
 471           i915->last_sampler = unwind;
 472    }
 473
 474    if (dirty & I915_UPLOAD_CONSTANTS) {
 475       if (INTEL_DEBUG & DEBUG_STATE)
 476          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 477       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 478    }
 479
 480    if (dirty & I915_UPLOAD_PROGRAM) {
 481       if (state->ProgramSize) {
 482          if (INTEL_DEBUG & DEBUG_STATE)
 483             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 484
 485          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 486
 487          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 488          if (INTEL_DEBUG & DEBUG_STATE)
 489             i915_disassemble_program(state->Program, state->ProgramSize);
 490       }
 491    }
 492
 493    assert(get_dirty(state) == 0);
 494 }
 495
 496 static void
 497 i915_destroy_context(struct intel_context *intel)
 498 {
 499    GLuint i;
 500    struct i915_context *i915 = i915_context(&intel->ctx);
 501
 502    intel_region_release(&i915->state.draw_region);
 503    intel_region_release(&i915->state.depth_region);
 504
 505    for (i = 0; i < I915_TEX_UNITS; i++) {
 506       if (i915->state.tex_buffer[i] != NULL) {
 507          drm_intel_bo_unreference(i915->state.tex_buffer[i]);
 508          i915->state.tex_buffer[i] = NULL;
 509       }
 510    }
 511
 512    _tnl_free_vertices(&intel->ctx);
 513 }
 514
 515 void
 516 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 517                              uint32_t buffer_id)
 518 {
 519    state[0] = _3DSTATE_BUF_INFO_CMD;
 520    state[1] = buffer_id;
 521
 522    if (region != NULL) {
 523       state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
 524
 525       if (region->tiling != I915_TILING_NONE) {
 526          state[1] |= BUF_3D_TILED_SURFACE;
 527          if (region->tiling == I915_TILING_Y)
 528             state[1] |= BUF_3D_TILE_WALK_Y;
 529       }
 530    }
 531 }
 532
 533 static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 534 {
 535    [MESA_FORMAT_ARGB8888] = DV_PF_8888,
 536    [MESA_FORMAT_XRGB8888] = DV_PF_8888,
 537    [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
 538    [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
 539    [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,
 540 };
 541
 542 static bool
 543 i915_render_target_supported(gl_format format)
 544 {
 545    if (format == MESA_FORMAT_S8_Z24 ||
 546        format == MESA_FORMAT_X8_Z24 ||
 547        format == MESA_FORMAT_Z16) {
 548       return true;
 549    }
 550
 551    return i915_render_target_format_for_mesa_format[format] != 0;
 552 }
 553
 554 static void
 555 i915_set_draw_region(struct intel_context *intel,
 556                      struct intel_region *color_regions[],
 557                      struct intel_region *depth_region,
 558                      GLuint num_regions)
 559 {
 560    struct i915_context *i915 = i915_context(&intel->ctx);
 561    struct gl_context *ctx = &intel->ctx;
 562    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 563    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 564    GLuint value;
 565    struct i915_hw_state *state = &i915->state;
 566    uint32_t draw_x, draw_y, draw_offset;
 567
 568    if (state->draw_region != color_regions[0]) {
 569       intel_region_release(&state->draw_region);
 570       intel_region_reference(&state->draw_region, color_regions[0]);
 571    }
 572    if (state->depth_region != depth_region) {
 573       intel_region_release(&state->depth_region);
 574       intel_region_reference(&state->depth_region, depth_region);
 575    }
 576
 577    /*
 578     * Set stride/cpp values
 579     */
 580    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
 581                                 color_regions[0], BUF_3D_ID_COLOR_BACK);
 582
 583    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
 584                                 depth_region, BUF_3D_ID_DEPTH);
 585
 586    /*
 587     * Compute/set I915_DESTREG_DV1 value
 588     */
 589    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 590             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 591             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 592    if (irb != NULL) {
 593       value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
 594    }
 595
 596    /* This isn't quite safe, thus being hidden behind an option.  When changing
 597     * the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
 598     * can only be set when a depth buffer is already defined.
 599     */
 600    if (intel->is_945 && intel->use_early_z &&
 601        depth_region->tiling != I915_TILING_NONE)
 602       value |= CLASSIC_EARLY_DEPTH;
 603
 604    if (depth_region && depth_region->cpp == 4) {
 605       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 606    }
 607    else {
 608       value |= DEPTH_FRMT_16_FIXED;
 609    }
 610    state->Buffer[I915_DESTREG_DV1] = value;
 611
 612    /* We set up the drawing rectangle to be offset into the color
 613     * region's location in the miptree.  If it doesn't match with
 614     * depth's offsets, we can't render to it.
 615     *
 616     * (Well, not actually true -- the hw grew a bit to let depth's
 617     * offset get forced to 0,0.  We may want to use that if people are
 618     * hitting that case.  Also, some configurations may be supportable
 619     * by tweaking the start offset of the buffers around, which we
 620     * can't do in general due to tiling)
 621     */
 622    FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
 623             (depth_region && color_regions[0]) &&
 624             (depth_region->draw_x != color_regions[0]->draw_x ||
 625              depth_region->draw_y != color_regions[0]->draw_y));
 626
 627    if (color_regions[0]) {
 628       draw_x = color_regions[0]->draw_x;
 629       draw_y = color_regions[0]->draw_y;
 630    } else if (depth_region) {
 631       draw_x = depth_region->draw_x;
 632       draw_y = depth_region->draw_y;
 633    } else {
 634       draw_x = 0;
 635       draw_y = 0;
 636    }
 637
 638    draw_offset = (draw_y << 16) | draw_x;
 639
 640    /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
 641    if (draw_offset != i915->last_draw_offset) {
 642       FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
 643                (ctx->DrawBuffer->Width + draw_x > 2048) ||
 644                (ctx->DrawBuffer->Height + draw_y > 2048));
 645
 646       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
 647       i915->last_draw_offset = draw_offset;
 648    } else
 649       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 650
 651    state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
 652    state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
 653    state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
 654    state->Buffer[I915_DESTREG_DRAWRECT4] =
 655       ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
 656       ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
 657    state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
 658
 659    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 660 }
 661
 662
 663
 664 static void
 665 i915_new_batch(struct intel_context *intel)
 666 {
 667    struct i915_context *i915 = i915_context(&intel->ctx);
 668
 669    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 670     * Using hardware contexts would be an alternative, but they have some
 671     * difficulties associated with them (physical address requirements).
 672     */
 673    i915->state.emitted = 0;
 674    i915->last_draw_offset = 0;
 675    i915->last_sampler = 0;
 676
 677    i915->current_vb_bo = NULL;
 678    i915->current_vertex_size = 0;
 679 }
 680
 681 static void
 682 i915_assert_not_dirty( struct intel_context *intel )
 683 {
 684    struct i915_context *i915 = i915_context(&intel->ctx);
 685    GLuint dirty = get_dirty(&i915->state);
 686    assert(!dirty);
 687    (void) dirty;
 688 }
 689
 690 /** Return false; i915 does not support HiZ. */
 691 static bool
 692 i915_is_hiz_depth_format(struct intel_context *intel,
 693                          gl_format format)
 694 {
 695    return false;
 696 }
 697
 698 void
 699 i915InitVtbl(struct i915_context *i915)
 700 {
 701    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 702    i915->intel.vtbl.destroy = i915_destroy_context;
 703    i915->intel.vtbl.emit_state = i915_emit_state;
 704    i915->intel.vtbl.new_batch = i915_new_batch;
 705    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 706    i915->intel.vtbl.render_start = i915_render_start;
 707    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 708    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 709    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 710    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 711    i915->intel.vtbl.finish_batch = intel_finish_vb;
 712    i915->intel.vtbl.render_target_supported = i915_render_target_supported;
 713    i915->intel.vtbl.is_hiz_depth_format = i915_is_hiz_depth_format;
 714 }