1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
35 #include "main/renderbuffer.h"
36 #include "main/framebuffer.h"
39 #include "tnl/t_context.h"
40 #include "tnl/t_vertex.h"
41 #include "swrast_setup/swrast_setup.h"
43 #include "intel_batchbuffer.h"
44 #include "intel_regions.h"
45 #include "intel_tris.h"
46 #include "intel_fbo.h"
47 #include "intel_buffers.h"
50 #include "i915_context.h"
53 i915_render_prevalidate(struct intel_context *intel)
55 struct i915_context *i915 = i915_context(&intel->ctx);
57 i915ValidateFragmentProgram(i915);
61 i915_render_start(struct intel_context *intel)
63 intel_prepare_render(intel);
68 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
70 struct i915_context *i915 = i915_context(&intel->ctx);
71 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
76 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
78 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
87 i915->intel.reduced_primitive = rprim;
89 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
90 INTEL_FIREVERTICES(intel);
92 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
93 i915->state.Stipple[I915_STPREG_ST1] = st1;
98 /* Pull apart the vertex format registers and figure out how large a
99 * vertex is supposed to be.
102 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
104 struct i915_context *i915 = i915_context(&intel->ctx);
105 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
106 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
109 switch (lis4 & S4_VFMT_XYZW_MASK) {
123 fprintf(stderr, "no xyzw specified\n");
127 if (lis4 & S4_VFMT_SPEC_FOG)
129 if (lis4 & S4_VFMT_COLOR)
131 if (lis4 & S4_VFMT_DEPTH_OFFSET)
133 if (lis4 & S4_VFMT_POINT_WIDTH)
135 if (lis4 & S4_VFMT_FOG_PARAM)
138 for (i = 0; i < 8; i++) {
139 switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
152 case TEXCOORDFMT_2D_16:
155 case TEXCOORDFMT_4D_16:
158 case TEXCOORDFMT_NOT_PRESENT:
161 fprintf(stderr, "bad texcoord fmt %d\n", i);
164 lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
168 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
170 return sz == expected;
175 i915_emit_invarient_state(struct intel_context *intel)
181 OUT_BATCH(_3DSTATE_AA_CMD |
182 AA_LINE_ECAAR_WIDTH_ENABLE |
183 AA_LINE_ECAAR_WIDTH_1_0 |
184 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
186 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
189 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
192 OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
195 /* Don't support texture crossbar yet */
196 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
201 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
203 /* Need to initialize this to zero.
205 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
209 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
211 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
215 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
217 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
224 #define emit(intel, state, size ) \
225 intel_batchbuffer_data(intel, state, size, false)
228 get_dirty(struct i915_hw_state *state)
232 /* Workaround the multitex hang - if one texture unit state is
233 * modified, emit all texture units.
235 dirty = state->active & ~state->emitted;
236 if (dirty & I915_UPLOAD_TEX_ALL)
237 state->emitted &= ~I915_UPLOAD_TEX_ALL;
238 dirty = state->active & ~state->emitted;
244 get_state_size(struct i915_hw_state *state)
246 GLuint dirty = get_dirty(state);
250 if (dirty & I915_UPLOAD_INVARIENT)
253 if (dirty & I915_UPLOAD_RASTER_RULES)
254 sz += sizeof(state->RasterRules);
256 if (dirty & I915_UPLOAD_CTX)
257 sz += sizeof(state->Ctx);
259 if (dirty & I915_UPLOAD_BLEND)
260 sz += sizeof(state->Blend);
262 if (dirty & I915_UPLOAD_BUFFERS)
263 sz += sizeof(state->Buffer);
265 if (dirty & I915_UPLOAD_STIPPLE)
266 sz += sizeof(state->Stipple);
268 if (dirty & I915_UPLOAD_TEX_ALL) {
270 for (i = 0; i < I915_TEX_UNITS; i++)
271 if (dirty & I915_UPLOAD_TEX(i))
274 sz += (2 + nr * 3) * sizeof(GLuint) * 2;
277 if (dirty & I915_UPLOAD_CONSTANTS)
278 sz += state->ConstantSize * sizeof(GLuint);
280 if (dirty & I915_UPLOAD_PROGRAM)
281 sz += state->ProgramSize * sizeof(GLuint);
286 /* Push the state into the sarea and/or texture memory.
289 i915_emit_state(struct intel_context *intel)
291 struct i915_context *i915 = i915_context(&intel->ctx);
292 struct i915_hw_state *state = &i915->state;
293 int i, count, aper_count;
295 drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
296 GET_CURRENT_CONTEXT(ctx);
299 /* We don't hold the lock at this point, so want to make sure that
300 * there won't be a buffer wrap between the state emits and the primitive
303 * It might be better to talk about explicit places where
304 * scheduling is allowed, rather than assume that it is whenever a
305 * batchbuffer fills up.
307 intel_batchbuffer_require_space(intel,
308 get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
312 if (intel->batch.bo == NULL) {
313 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
317 dirty = get_dirty(state);
319 aper_array[aper_count++] = intel->batch.bo;
320 if (dirty & I915_UPLOAD_BUFFERS) {
321 aper_array[aper_count++] = state->draw_region->buffer;
322 if (state->depth_region)
323 aper_array[aper_count++] = state->depth_region->buffer;
326 if (dirty & I915_UPLOAD_TEX_ALL) {
327 for (i = 0; i < I915_TEX_UNITS; i++) {
328 if (dirty & I915_UPLOAD_TEX(i)) {
329 if (state->tex_buffer[i]) {
330 aper_array[aper_count++] = state->tex_buffer[i];
336 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
339 intel_batchbuffer_flush(intel);
342 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
347 /* work out list of buffers to emit */
349 /* Do this here as we may have flushed the batchbuffer above,
350 * causing more state to be dirty!
352 dirty = get_dirty(state);
353 state->emitted |= dirty;
354 assert(get_dirty(state) == 0);
356 if (INTEL_DEBUG & DEBUG_STATE)
357 fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
359 if (dirty & I915_UPLOAD_INVARIENT) {
360 if (INTEL_DEBUG & DEBUG_STATE)
361 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
362 i915_emit_invarient_state(intel);
365 if (dirty & I915_UPLOAD_RASTER_RULES) {
366 if (INTEL_DEBUG & DEBUG_STATE)
367 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
368 emit(intel, state->RasterRules, sizeof(state->RasterRules));
371 if (dirty & I915_UPLOAD_CTX) {
372 if (INTEL_DEBUG & DEBUG_STATE)
373 fprintf(stderr, "I915_UPLOAD_CTX:\n");
375 emit(intel, state->Ctx, sizeof(state->Ctx));
378 if (dirty & I915_UPLOAD_BLEND) {
379 if (INTEL_DEBUG & DEBUG_STATE)
380 fprintf(stderr, "I915_UPLOAD_BLEND:\n");
382 emit(intel, state->Blend, sizeof(state->Blend));
385 if (dirty & I915_UPLOAD_BUFFERS) {
388 if (INTEL_DEBUG & DEBUG_STATE)
389 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
392 if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
394 if (state->depth_region)
398 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
399 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
400 OUT_RELOC(state->draw_region->buffer,
401 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
403 if (state->depth_region) {
404 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
405 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
406 OUT_RELOC(state->depth_region->buffer,
407 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
410 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
411 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
412 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
413 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
414 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
415 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
417 if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
418 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
419 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
420 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
421 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
422 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
423 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
428 if (dirty & I915_UPLOAD_STIPPLE) {
429 if (INTEL_DEBUG & DEBUG_STATE)
430 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
431 emit(intel, state->Stipple, sizeof(state->Stipple));
434 /* Combine all the dirty texture state into a single command to
435 * avoid lockups on I915 hardware.
437 if (dirty & I915_UPLOAD_TEX_ALL) {
441 for (i = 0; i < I915_TEX_UNITS; i++)
442 if (dirty & I915_UPLOAD_TEX(i))
445 BEGIN_BATCH(2 + nr * 3);
446 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
447 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
448 for (i = 0; i < I915_TEX_UNITS; i++)
449 if (dirty & I915_UPLOAD_TEX(i)) {
450 OUT_RELOC(state->tex_buffer[i],
451 I915_GEM_DOMAIN_SAMPLER, 0,
452 state->tex_offset[i]);
454 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
455 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
459 unwind = intel->batch.used;
460 BEGIN_BATCH(2 + nr * 3);
461 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
462 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
463 for (i = 0; i < I915_TEX_UNITS; i++)
464 if (dirty & I915_UPLOAD_TEX(i)) {
465 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
466 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
467 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
470 if (i915->last_sampler &&
471 memcmp(intel->batch.map + i915->last_sampler,
472 intel->batch.map + unwind,
473 (2 + nr*3)*sizeof(int)) == 0)
474 intel->batch.used = unwind;
476 i915->last_sampler = unwind;
479 if (dirty & I915_UPLOAD_CONSTANTS) {
480 if (INTEL_DEBUG & DEBUG_STATE)
481 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
482 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
485 if (dirty & I915_UPLOAD_PROGRAM) {
486 if (state->ProgramSize) {
487 if (INTEL_DEBUG & DEBUG_STATE)
488 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
490 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
492 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
493 if (INTEL_DEBUG & DEBUG_STATE)
494 i915_disassemble_program(state->Program, state->ProgramSize);
498 assert(get_dirty(state) == 0);
502 i915_destroy_context(struct intel_context *intel)
505 struct i915_context *i915 = i915_context(&intel->ctx);
507 intel_region_release(&i915->state.draw_region);
508 intel_region_release(&i915->state.depth_region);
510 for (i = 0; i < I915_TEX_UNITS; i++) {
511 if (i915->state.tex_buffer[i] != NULL) {
512 drm_intel_bo_unreference(i915->state.tex_buffer[i]);
513 i915->state.tex_buffer[i] = NULL;
517 _tnl_free_vertices(&intel->ctx);
521 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
524 state[0] = _3DSTATE_BUF_INFO_CMD;
525 state[1] = buffer_id;
527 if (region != NULL) {
528 state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
530 if (region->tiling != I915_TILING_NONE) {
531 state[1] |= BUF_3D_TILED_SURFACE;
532 if (region->tiling == I915_TILING_Y)
533 state[1] |= BUF_3D_TILE_WALK_Y;
538 static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
540 [MESA_FORMAT_ARGB8888] = DV_PF_8888,
541 [MESA_FORMAT_XRGB8888] = DV_PF_8888,
542 [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
543 [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
544 [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,
548 i915_render_target_supported(gl_format format)
550 if (format == MESA_FORMAT_S8_Z24 ||
551 format == MESA_FORMAT_X8_Z24 ||
552 format == MESA_FORMAT_Z16) {
556 return i915_render_target_format_for_mesa_format[format] != 0;
560 i915_set_draw_region(struct intel_context *intel,
561 struct intel_region *color_regions[],
562 struct intel_region *depth_region,
565 struct i915_context *i915 = i915_context(&intel->ctx);
566 struct gl_context *ctx = &intel->ctx;
567 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
568 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
569 struct gl_renderbuffer *drb;
570 struct intel_renderbuffer *idrb = NULL;
572 struct i915_hw_state *state = &i915->state;
573 uint32_t draw_x, draw_y, draw_offset;
575 if (state->draw_region != color_regions[0]) {
576 intel_region_release(&state->draw_region);
577 intel_region_reference(&state->draw_region, color_regions[0]);
579 if (state->depth_region != depth_region) {
580 intel_region_release(&state->depth_region);
581 intel_region_reference(&state->depth_region, depth_region);
585 * Set stride/cpp values
587 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
588 color_regions[0], BUF_3D_ID_COLOR_BACK);
590 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
591 depth_region, BUF_3D_ID_DEPTH);
594 * Compute/set I915_DESTREG_DV1 value
596 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
597 DSTORG_VERT_BIAS(0x8) | /* .5 */
598 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
600 value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
603 /* This isn't quite safe, thus being hidden behind an option. When changing
604 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
605 * can only be set when a depth buffer is already defined.
607 if (intel->is_945 && intel->use_early_z &&
608 depth_region->tiling != I915_TILING_NONE)
609 value |= CLASSIC_EARLY_DEPTH;
611 if (depth_region && depth_region->cpp == 4) {
612 value |= DEPTH_FRMT_24_FIXED_8_OTHER;
615 value |= DEPTH_FRMT_16_FIXED;
617 state->Buffer[I915_DESTREG_DV1] = value;
619 drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
621 drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
624 idrb = intel_renderbuffer(drb);
626 /* We set up the drawing rectangle to be offset into the color
627 * region's location in the miptree. If it doesn't match with
628 * depth's offsets, we can't render to it.
630 * (Well, not actually true -- the hw grew a bit to let depth's
631 * offset get forced to 0,0. We may want to use that if people are
632 * hitting that case. Also, some configurations may be supportable
633 * by tweaking the start offset of the buffers around, which we
634 * can't do in general due to tiling)
636 FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
637 idrb && irb && (idrb->draw_x != irb->draw_x ||
638 idrb->draw_y != irb->draw_y));
641 draw_x = irb->draw_x;
642 draw_y = irb->draw_y;
644 draw_x = idrb->draw_x;
645 draw_y = idrb->draw_y;
651 draw_offset = (draw_y << 16) | draw_x;
653 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
654 if (draw_offset != i915->last_draw_offset) {
655 FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
656 (ctx->DrawBuffer->Width + draw_x > 2048) ||
657 (ctx->DrawBuffer->Height + draw_y > 2048));
659 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
660 i915->last_draw_offset = draw_offset;
662 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
664 state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
665 state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
666 state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
667 state->Buffer[I915_DESTREG_DRAWRECT4] =
668 ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
669 ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
670 state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
672 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
676 * Update the hardware state for drawing into a window or framebuffer object.
678 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
679 * places within the driver.
681 * Basically, this needs to be called any time the current framebuffer
682 * changes, the renderbuffers change, or we need to draw into different
686 i915_update_draw_buffer(struct intel_context *intel)
688 struct gl_context *ctx = &intel->ctx;
689 struct gl_framebuffer *fb = ctx->DrawBuffer;
690 struct intel_region *colorRegions[MAX_DRAW_BUFFERS], *depthRegion = NULL;
691 struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL;
692 bool fb_has_hiz = intel_framebuffer_has_hiz(fb);
695 /* this can happen during the initial context initialization */
699 irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH);
700 irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL);
702 /* Do this here, not core Mesa, since this function is called from
703 * many places within the driver.
705 if (ctx->NewState & _NEW_BUFFERS) {
706 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
707 _mesa_update_framebuffer(ctx);
708 /* this updates the DrawBuffer's Width/Height if it's a FBO */
709 _mesa_update_draw_buffer_bounds(ctx);
712 if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
713 /* this may occur when we're called by glBindFrameBuffer() during
714 * the process of someone setting up renderbuffers, etc.
716 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
720 /* How many color buffers are we drawing into?
722 * If there are zero buffers or the buffer is too big, don't configure any
723 * regions for hardware drawing. We'll fallback to software below. Not
724 * having regions set makes some of the software fallback paths faster.
726 if ((fb->Width > ctx->Const.MaxRenderbufferSize)
727 || (fb->Height > ctx->Const.MaxRenderbufferSize)
728 || (fb->_NumColorDrawBuffers == 0)) {
730 colorRegions[0] = NULL;
732 else if (fb->_NumColorDrawBuffers > 1) {
734 struct intel_renderbuffer *irb;
736 for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
737 irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]);
738 colorRegions[i] = irb ? irb->region : NULL;
742 /* Get the intel_renderbuffer for the single colorbuffer we're drawing
746 /* drawing to window system buffer */
747 if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)
748 colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT);
750 colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT);
753 /* drawing to user-created FBO */
754 struct intel_renderbuffer *irb;
755 irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]);
756 colorRegions[0] = (irb && irb->region) ? irb->region : NULL;
760 if (!colorRegions[0]) {
761 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, GL_TRUE);
764 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, GL_FALSE);
767 /* Check for depth fallback. */
768 if (irbDepth && irbDepth->region) {
769 assert(!fb_has_hiz || irbDepth->Base.Format != MESA_FORMAT_S8_Z24);
770 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
771 depthRegion = irbDepth->region;
772 } else if (irbDepth && !irbDepth->region) {
773 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_TRUE);
775 } else { /* !irbDepth */
776 /* No fallback is needed because there is no depth buffer. */
777 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, GL_FALSE);
781 /* Check for stencil fallback. */
782 if (irbStencil && irbStencil->region) {
783 assert(irbStencil->Base.Format == MESA_FORMAT_S8_Z24);
784 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
785 } else if (irbStencil && !irbStencil->region) {
786 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_TRUE);
787 } else { /* !irbStencil */
788 /* No fallback is needed because there is no stencil buffer. */
789 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, GL_FALSE);
792 /* If we have a (packed) stencil buffer attached but no depth buffer,
793 * we still need to set up the shared depth/stencil state so we can use it.
795 if (depthRegion == NULL && irbStencil && irbStencil->region
796 && irbStencil->Base.Format == MESA_FORMAT_S8_Z24) {
797 depthRegion = irbStencil->region;
801 * Update depth and stencil test state
803 ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
804 ctx->Driver.Enable(ctx, GL_STENCIL_TEST, ctx->Stencil.Enabled);
806 intel->vtbl.set_draw_region(intel, colorRegions, depthRegion,
807 fb->_NumColorDrawBuffers);
808 intel->NewGLState |= _NEW_BUFFERS;
810 /* update viewport since it depends on window size */
811 intelCalcViewport(ctx);
813 /* Set state we know depends on drawable parameters:
815 ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y,
816 ctx->Scissor.Width, ctx->Scissor.Height);
817 ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far);
819 /* Update culling direction which changes depending on the
820 * orientation of the buffer:
822 ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace);
826 i915_new_batch(struct intel_context *intel)
828 struct i915_context *i915 = i915_context(&intel->ctx);
830 /* Mark all state as needing to be emitted when starting a new batchbuffer.
831 * Using hardware contexts would be an alternative, but they have some
832 * difficulties associated with them (physical address requirements).
834 i915->state.emitted = 0;
835 i915->last_draw_offset = 0;
836 i915->last_sampler = 0;
838 i915->current_vb_bo = NULL;
839 i915->current_vertex_size = 0;
843 i915_assert_not_dirty( struct intel_context *intel )
845 struct i915_context *i915 = i915_context(&intel->ctx);
846 GLuint dirty = get_dirty(&i915->state);
851 /** Return false; i915 does not support HiZ. */
853 i915_is_hiz_depth_format(struct intel_context *intel,
860 i915_invalidate_state(struct intel_context *intel, GLuint new_state)
862 struct gl_context *ctx = &intel->ctx;
864 _swsetup_InvalidateState(ctx, new_state);
865 _tnl_InvalidateState(ctx, new_state);
866 _tnl_invalidate_vertex_state(ctx, new_state);
870 i915InitVtbl(struct i915_context *i915)
872 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
873 i915->intel.vtbl.destroy = i915_destroy_context;
874 i915->intel.vtbl.emit_state = i915_emit_state;
875 i915->intel.vtbl.new_batch = i915_new_batch;
876 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
877 i915->intel.vtbl.render_start = i915_render_start;
878 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
879 i915->intel.vtbl.set_draw_region = i915_set_draw_region;
880 i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer;
881 i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
882 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
883 i915->intel.vtbl.finish_batch = intel_finish_vb;
884 i915->intel.vtbl.invalidate_state = i915_invalidate_state;
885 i915->intel.vtbl.render_target_supported = i915_render_target_supported;
886 i915->intel.vtbl.is_hiz_depth_format = i915_is_hiz_depth_format;