1 // Licensed to the .NET Foundation under one or more agreements.
2 // The .NET Foundation licenses this file to you under the MIT license.
3 // See the LICENSE file in the project root for more information.
5 /*****************************************************************************/
9 #if defined(FEATURE_CORECLR) && defined(_TARGET_UNIX_)
10 #define FEATURE_VARARG 0
11 #else // !(defined(FEATURE_CORECLR) && defined(_TARGET_UNIX_))
12 #define FEATURE_VARARG 1
13 #endif // !(defined(FEATURE_CORECLR) && defined(_TARGET_UNIX_))
15 /*****************************************************************************/
16 // The following are human readable names for the target architectures
17 #if defined(_TARGET_X86_)
18 #define TARGET_READABLE_NAME "X86"
19 #elif defined(_TARGET_AMD64_)
20 #define TARGET_READABLE_NAME "AMD64"
21 #elif defined(_TARGET_ARM_)
22 #define TARGET_READABLE_NAME "ARM"
23 #elif defined(_TARGET_ARM64_)
24 #define TARGET_READABLE_NAME "ARM64"
26 #error Unsupported or unset target architecture
29 /*****************************************************************************/
30 // The following are intended to capture only those #defines that cannot be replaced
31 // with static const members of Target
32 #if defined(_TARGET_X86_) && defined(LEGACY_BACKEND)
33 #define REGMASK_BITS 8 // number of bits used to represent register mask
34 #elif defined(_TARGET_XARCH_)
35 #define REGMASK_BITS 32
37 #elif defined(_TARGET_ARM_)
38 #define REGMASK_BITS 64
40 #elif defined(_TARGET_ARM64_)
41 #define REGMASK_BITS 64
44 #error Unsupported or unset target architecture
47 //------------------------------------------------------------------------
49 // Each register list in register.h must declare REG_STK as the last value.
50 // In the following enum declarations, the following REG_XXX are created beyond
51 // the "real" registers:
52 // REG_STK - Used to indicate something evaluated onto the stack.
53 // ACTUAL_REG_COUNT - The number of physical registers. (same as REG_STK).
54 // REG_COUNT - The number of physical register + REG_STK. This is the count of values that may
55 // be assigned during register allocation.
56 // REG_NA - Used to indicate that a register is either not yet assigned or not required.
58 #if defined(_TARGET_ARM_)
59 enum _regNumber_enum : unsigned
61 #define REGDEF(name, rnum, mask, sname) REG_##name = rnum,
62 #define REGALIAS(alias, realname) REG_##alias = REG_##realname,
67 ACTUAL_REG_COUNT = REG_COUNT - 1 // everything but REG_STK (only real regs)
70 enum _regMask_enum : unsigned __int64
73 #define REGDEF(name, rnum, mask, sname) RBM_##name = mask,
74 #define REGALIAS(alias, realname) RBM_##alias = RBM_##realname,
78 #elif defined(_TARGET_ARM64_)
80 enum _regNumber_enum : unsigned
82 #define REGDEF(name, rnum, mask, xname, wname) REG_##name = rnum,
83 #define REGALIAS(alias, realname) REG_##alias = REG_##realname,
88 ACTUAL_REG_COUNT = REG_COUNT - 1 // everything but REG_STK (only real regs)
91 enum _regMask_enum : unsigned __int64
94 #define REGDEF(name, rnum, mask, xname, wname) RBM_##name = mask,
95 #define REGALIAS(alias, realname) RBM_##alias = RBM_##realname,
99 #elif defined(_TARGET_AMD64_)
101 enum _regNumber_enum : unsigned
103 #define REGDEF(name, rnum, mask, sname) REG_##name = rnum,
104 #define REGALIAS(alias, realname) REG_##alias = REG_##realname,
105 #include "register.h"
109 ACTUAL_REG_COUNT = REG_COUNT - 1 // everything but REG_STK (only real regs)
112 enum _regMask_enum : unsigned
116 #define REGDEF(name, rnum, mask, sname) RBM_##name = mask,
117 #define REGALIAS(alias, realname) RBM_##alias = RBM_##realname,
118 #include "register.h"
121 #elif defined(_TARGET_X86_)
123 #ifndef LEGACY_BACKEND
124 enum _regNumber_enum : unsigned
126 #define REGDEF(name, rnum, mask, sname) REG_##name = rnum,
127 #define REGALIAS(alias, realname) REG_##alias = REG_##realname,
128 #include "register.h"
132 ACTUAL_REG_COUNT = REG_COUNT - 1 // everything but REG_STK (only real regs)
135 enum _regMask_enum : unsigned
139 #define REGDEF(name, rnum, mask, sname) RBM_##name = mask,
140 #define REGALIAS(alias, realname) RBM_##alias = RBM_##realname,
141 #include "register.h"
144 #else // LEGACY_BACKEND
145 enum _regNumber_enum : unsigned
147 #define REGDEF(name, rnum, mask, sname) REG_##name = rnum,
148 #define REGALIAS(alias, realname) REG_##alias = REG_##realname,
149 #include "register.h"
153 ACTUAL_REG_COUNT = REG_COUNT - 1, // everything but REG_STK (only real regs)
155 #define REGDEF(name, rnum, mask, sname) REG_##name = rnum,
156 #include "registerfp.h"
159 REG_FPNONE = REG_FPCOUNT,
161 #define REGDEF(name, rnum, mask, sname) REG_##name = rnum,
162 #include "registerxmm.h"
167 enum _regMask_enum : unsigned
171 #define REGDEF(name, rnum, mask, sname) RBM_##name = mask,
172 #define REGALIAS(alias, realname) RBM_##alias = RBM_##realname,
173 #include "register.h"
175 #define REGDEF(name, rnum, mask, sname) RBM_##name = mask,
176 #include "registerfp.h"
178 #define REGDEF(name, rnum, mask, sname) RBM_##name = mask,
179 #include "registerxmm.h"
182 #endif // LEGACY_BACKEND
184 #error Unsupported target architecture
187 /* The following are used to hold 'long' (64-bit integer) operands */
190 The following yield the number of bits and the mask of a register
191 number in a register pair.
195 #define REG_PAIR_NBITS 6
197 #define REG_PAIR_NBITS 4
199 #define REG_PAIR_NMASK ((1 << REG_PAIR_NBITS) - 1)
202 // Under DEBUG, we want to make sure that code doesn't accidentally confuse a reg pair value
203 // with a simple register number. Thus, we offset the reg pair numbers so they are distinct
204 // from all register numbers. Note that this increases the minimum size of a regPairNoSmall
205 // type due to the additional bits used for this offset.
206 #define REG_PAIR_FIRST (7 << REG_PAIR_NBITS)
207 #define REG_PAIR_NBITS_DEBUG \
209 3) // extra bits needed by the debug shifting (3 instead of 0 because we shift "7", not "1", above).
210 C_ASSERT(REG_COUNT < REG_PAIR_FIRST); // make sure the register numbers (including REG_NA, ignoring fp/xmm regs on
211 // x86/x64) are distinct from the pair numbers
213 #define REG_PAIR_FIRST 0
216 enum _regPairNo_enum : unsigned
218 #define PAIRDEF(rlo, rhi) REG_PAIR_##rlo##rhi = REG_##rlo + (REG_##rhi << REG_PAIR_NBITS) + REG_PAIR_FIRST,
221 REG_PAIR_LAST = (REG_COUNT - 1) + ((REG_COUNT - 1) << REG_PAIR_NBITS) + REG_PAIR_FIRST,
223 REG_PAIR_NONE = REG_PAIR_LAST + 1
228 #define PAIRDEF(rlo, rhi) RBM_PAIR_##rlo##rhi = (RBM_##rlo | RBM_##rhi),
232 /*****************************************************************************/
234 // TODO-Cleanup: The types defined below are mildly confusing: why are there both?
235 // regMaskSmall is large enough to represent the entire set of registers.
236 // If regMaskSmall is smaller than a "natural" integer type, regMaskTP is wider, based
237 // on a belief by the original authors of the JIT that in some situations it is more
238 // efficient to have the wider representation. This belief should be tested, and if it
239 // is false, then we should coalesce these two types into one (the Small width, probably).
240 // In any case, we believe that is OK to freely cast between these types; no information will
243 #ifdef _TARGET_ARMARCH_
244 typedef unsigned __int64 regMaskTP;
246 typedef unsigned regMaskTP;
249 #if REGMASK_BITS == 8
250 typedef unsigned char regMaskSmall;
251 #define REG_MASK_INT_FMT "%02X"
252 #define REG_MASK_ALL_FMT "%02X"
253 #elif REGMASK_BITS == 16
254 typedef unsigned short regMaskSmall;
255 #define REG_MASK_INT_FMT "%04X"
256 #define REG_MASK_ALL_FMT "%04X"
257 #elif REGMASK_BITS == 32
258 typedef unsigned regMaskSmall;
259 #define REG_MASK_INT_FMT "%08X"
260 #define REG_MASK_ALL_FMT "%08X"
262 typedef unsigned __int64 regMaskSmall;
263 #define REG_MASK_INT_FMT "%04llX"
264 #define REG_MASK_ALL_FMT "%016llX"
267 typedef _regNumber_enum regNumber;
268 typedef _regPairNo_enum regPairNo;
270 // LSRA currently converts freely between regNumber and regPairNo, so make sure they are the same size.
271 C_ASSERT(sizeof(regPairNo) == sizeof(regNumber));
273 typedef unsigned char regNumberSmall;
277 // Under DEBUG, we shift the reg pair numbers to be independent of the regNumber range,
278 // so we need additional bits. See the definition of REG_PAIR_FIRST for details.
280 #if ((2 * REG_PAIR_NBITS) + REG_PAIR_NBITS_DEBUG) <= 16
281 C_ASSERT(((2 * REG_PAIR_NBITS) + REG_PAIR_NBITS_DEBUG) > 8); // assert that nobody fits in 8 bits
282 typedef unsigned short regPairNoSmall; // x86/x64: need 15 bits
284 C_ASSERT(((2 * REG_PAIR_NBITS) + REG_PAIR_NBITS_DEBUG) <= 32);
285 typedef unsigned regPairNoSmall; // arm: need 21 bits
290 #if (2 * REG_PAIR_NBITS) <= 8
291 typedef unsigned char regPairNoSmall; // x86/x64: need 8 bits
293 C_ASSERT((2 * REG_PAIR_NBITS) <= 16); // assert that nobody needs more than 16 bits
294 typedef unsigned short regPairNoSmall; // arm: need 12 bits
299 /*****************************************************************************/
301 #define LEA_AVAILABLE 1
302 #define SCALED_ADDR_MODES 1
304 /*****************************************************************************/
307 #define DSP_SRC_OPER_LEFT 0
308 #define DSP_SRC_OPER_RIGHT 1
309 #define DSP_DST_OPER_LEFT 1
310 #define DSP_DST_OPER_RIGHT 0
313 /*****************************************************************************/
315 // The pseudorandom nop insertion is not necessary for current CoreCLR scenarios
316 // #if defined(FEATURE_CORECLR) && !defined(_TARGET_ARM_)
317 // #define PSEUDORANDOM_NOP_INSERTION
320 /*****************************************************************************/
323 #if defined(_TARGET_X86_)
325 #define CPU_LOAD_STORE_ARCH 0
327 #ifdef LEGACY_BACKEND
328 #define CPU_LONG_USES_REGPAIR 1
330 #define CPU_LONG_USES_REGPAIR 0 // RyuJIT x86 doesn't use the regPairNo field to record register pairs for long
331 // type tree nodes, and instead either decomposes them (for non-atomic operations)
332 // or stores multiple regNumber values for operations such as calls where the
333 // register definitions are effectively "atomic".
334 #endif // LEGACY_BACKEND
336 #define CPU_HAS_FP_SUPPORT 1
337 #define ROUND_FLOAT 1 // round intermed float expression results
338 #define CPU_HAS_BYTE_REGS 1
339 #define CPU_USES_BLOCK_MOVE 1
341 #ifndef LEGACY_BACKEND
342 // TODO-CQ: Fine tune the following xxBlk threshold values:
344 #define CPBLK_MOVS_LIMIT 16 // When generating code for CpBlk, this is the buffer size
345 // threshold to stop generating rep movs and switch to the helper call.
346 // NOTE: Using rep movs is currently disabled since we found it has bad performance
347 // on pre-Ivy Bridge hardware.
349 #define CPBLK_UNROLL_LIMIT 64 // Upper bound to let the code generator to loop unroll CpBlk.
350 #define INITBLK_STOS_LIMIT 64 // When generating code for InitBlk, this is the buffer size
351 // NOTE: Using rep stos is currently disabled since we found it has bad performance
352 // on pre-Ivy Bridge hardware.
353 // threshold to stop generating rep movs and switch to the helper call.
354 #define INITBLK_UNROLL_LIMIT 128 // Upper bound to let the code generator to loop unroll InitBlk.
355 #define CPOBJ_NONGC_SLOTS_LIMIT 4 // For CpObj code generation, this is the the threshold of the number
356 // of contiguous non-gc slots that trigger generating rep movsq instead of
357 // sequences of movsq instructions
358 // The way we're currently disabling rep movs/stos is by setting a limit less than
359 // its unrolling counterparts. When lower takes the decision on which one to make it
360 // always asks for the unrolling limit first so you can say the JIT 'favors' unrolling.
361 // Setting the limit to something lower than that makes lower to never consider it.
363 #endif // !LEGACY_BACKEND
366 #define ALIGN_SIMD_TYPES 1 // whether SIMD type locals are to be aligned
367 #endif // FEATURE_SIMD
369 #define FEATURE_WRITE_BARRIER 1 // Generate the proper WriteBarrier calls for GC
370 #define FEATURE_FIXED_OUT_ARGS 0 // X86 uses push instructions to pass args
371 #define FEATURE_STRUCTPROMOTE 1 // JIT Optimization to promote fields of structs into registers
372 #define FEATURE_MULTIREG_STRUCT_PROMOTE 0 // True when we want to promote fields of a multireg struct into registers
373 #define FEATURE_FASTTAILCALL 0 // Tail calls made as epilog+jmp
374 #define FEATURE_TAILCALL_OPT 0 // opportunistic Tail calls (without ".tail" prefix) made as fast tail calls.
375 #define FEATURE_SET_FLAGS 0 // Set to true to force the JIT to mark the trees with GTF_SET_FLAGS when
376 // the flags need to be set
377 #ifdef LEGACY_BACKEND
378 #define FEATURE_MULTIREG_ARGS_OR_RET 0 // Support for passing and/or returning single values in more than one register
379 #define FEATURE_MULTIREG_ARGS 0 // Support for passing a single argument in more than one register
380 #define FEATURE_MULTIREG_RET 0 // Support for returning a single value in more than one register
381 #define MAX_PASS_MULTIREG_BYTES 0 // No multireg arguments
382 #define MAX_RET_MULTIREG_BYTES 0 // No multireg return values
384 #define FEATURE_MULTIREG_ARGS_OR_RET 1 // Support for passing and/or returning single values in more than one register
385 #define FEATURE_MULTIREG_ARGS 0 // Support for passing a single argument in more than one register
386 #define FEATURE_MULTIREG_RET 1 // Support for returning a single value in more than one register
387 #define MAX_PASS_MULTIREG_BYTES 0 // No multireg arguments (note this seems wrong as MAX_ARG_REG_COUNT is 2)
388 #define MAX_RET_MULTIREG_BYTES 8 // Maximum size of a struct that could be returned in more than one register
391 #define MAX_ARG_REG_COUNT 2 // Maximum registers used to pass an argument.
392 #define MAX_RET_REG_COUNT 2 // Maximum registers used to return a value.
394 #ifdef FEATURE_USE_ASM_GC_WRITE_BARRIERS
395 #define NOGC_WRITE_BARRIERS 1 // We have specialized WriteBarrier JIT Helpers that DO-NOT trash the
396 // RBM_CALLEE_TRASH registers
398 #define NOGC_WRITE_BARRIERS 0 // Do not modify this -- modify the definition above. (If we're not using
399 // ASM barriers we definitely don't have NOGC barriers).
401 #define USER_ARGS_COME_LAST 0
402 #define EMIT_TRACK_STACK_DEPTH 1
403 #define TARGET_POINTER_SIZE 4 // equal to sizeof(void*) and the managed pointer size in bytes for this
405 #define FEATURE_EH 1 // To aid platform bring-up, eliminate exceptional EH clauses (catch, filter,
406 // filter-handler, fault) and directly execute 'finally' clauses.
407 #if defined(FEATURE_PAL) && !defined(LEGACY_BACKEND)
408 #define FEATURE_EH_FUNCLETS 1
409 #else // FEATURE_PAL && !LEGACY_BACKEND
410 #define FEATURE_EH_FUNCLETS 0
411 #endif // FEATURE_PAL && !LEGACY_BACKEND
412 #define FEATURE_EH_CALLFINALLY_THUNKS 0 // Generate call-to-finally code in "thunks" in the enclosing EH region,
413 // protected by "cloned finally" clauses.
414 #ifndef LEGACY_BACKEND
415 #define FEATURE_STACK_FP_X87 0
416 #else // LEGACY_BACKEND
417 #define FEATURE_STACK_FP_X87 1 // Use flat register file model
418 #endif // LEGACY_BACKEND
419 #define FEATURE_X87_DOUBLES 0 // FP tree temps always use x87 doubles (when 1) or can be double or float
421 #define ETW_EBP_FRAMED 1 // if 1 we cannot use EBP as a scratch register and must create EBP based
422 // frames for most methods
423 #define CSE_CONSTS 1 // Enable if we want to CSE constants
425 #ifndef LEGACY_BACKEND
426 // The following defines are useful for iterating a regNumber
427 #define REG_FIRST REG_EAX
428 #define REG_INT_FIRST REG_EAX
429 #define REG_INT_LAST REG_EDI
430 #define REG_INT_COUNT (REG_INT_LAST - REG_INT_FIRST + 1)
431 #define REG_NEXT(reg) ((regNumber)((unsigned)(reg) + 1))
432 #define REG_PREV(reg) ((regNumber)((unsigned)(reg) - 1))
434 #define REG_FP_FIRST REG_XMM0
435 #define REG_FP_LAST REG_XMM7
436 #define FIRST_FP_ARGREG REG_XMM0
437 #define LAST_FP_ARGREG REG_XMM3
438 #define REG_FLTARG_0 REG_XMM0
439 #define REG_FLTARG_1 REG_XMM1
440 #define REG_FLTARG_2 REG_XMM2
441 #define REG_FLTARG_3 REG_XMM3
443 #define RBM_FLTARG_0 RBM_XMM0
444 #define RBM_FLTARG_1 RBM_XMM1
445 #define RBM_FLTARG_2 RBM_XMM2
446 #define RBM_FLTARG_3 RBM_XMM3
448 #define RBM_FLTARG_REGS (RBM_FLTARG_0|RBM_FLTARG_1|RBM_FLTARG_2|RBM_FLTARG_3)
450 #define RBM_ALLFLOAT (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM3 | RBM_XMM4 | RBM_XMM5 | RBM_XMM6 | RBM_XMM7)
451 #define RBM_ALLDOUBLE RBM_ALLFLOAT
453 // TODO-CQ: Currently we are following the x86 ABI for SSE2 registers.
454 // This should be reconsidered.
455 #define RBM_FLT_CALLEE_SAVED RBM_NONE
456 #define RBM_FLT_CALLEE_TRASH RBM_ALLFLOAT
457 #define REG_VAR_ORDER_FLT REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7
459 #define REG_FLT_CALLEE_SAVED_FIRST REG_XMM6
460 #define REG_FLT_CALLEE_SAVED_LAST REG_XMM7
462 #define XMM_REGSIZE_BYTES 16 // XMM register size in bytes
463 #define YMM_REGSIZE_BYTES 32 // YMM register size in bytes
465 #define REGNUM_BITS 6 // number of bits in a REG_*
466 #define TINY_REGNUM_BITS 6 // number used in a tiny instrdesc (same)
468 #else // LEGACY_BACKEND
469 #define FEATURE_FP_REGALLOC 0 // Enabled if RegAlloc is used to enregister Floating Point LclVars
471 #define FP_STK_SIZE 8
472 #define RBM_ALLFLOAT (RBM_FPV0 | RBM_FPV1 | RBM_FPV2 | RBM_FPV3 | RBM_FPV4 | RBM_FPV5 | RBM_FPV6)
473 #define REG_FP_FIRST REG_FPV0
474 #define REG_FP_LAST REG_FPV7
475 #define FIRST_FP_ARGREG REG_NA
476 #define LAST_FP_ARGREG REG_NA
479 #define REGNUM_BITS 3 // number of bits in a REG_*
480 #define TINY_REGNUM_BITS 3
481 #define REGMASK_BITS 8 // number of bits in a REGNUM_MASK
483 #define RBM_FLTARG_REGS 0
484 #define RBM_FLT_CALLEE_SAVED 0
485 #define RBM_FLT_CALLEE_TRASH 0
487 #endif // LEGACY_BACKEND
489 #define REGSIZE_BYTES 4 // number of bytes in one register
490 #define MIN_ARG_AREA_FOR_CALL 0 // Minimum required outgoing argument space for a call.
492 #define CODE_ALIGN 1 // code alignment requirement
493 #if !defined(UNIX_X86_ABI)
494 #define STACK_ALIGN 4 // stack alignment requirement
495 #define STACK_ALIGN_SHIFT 2 // Shift-right amount to convert stack size in bytes to size in DWORD_PTRs
496 #define STACK_ALIGN_SHIFT_ALL 2 // Shift-right amount to convert stack size in bytes to size in STACK_ALIGN units
498 #define STACK_ALIGN 16 // stack alignment requirement
499 #define STACK_ALIGN_SHIFT 4 // Shift-right amount to convert stack size in bytes to size in DWORD_PTRs
500 #define STACK_ALIGN_SHIFT_ALL 4 // Shift-right amount to convert stack size in bytes to size in STACK_ALIGN units
501 #endif // !UNIX_X86_ABI
503 #define RBM_INT_CALLEE_SAVED (RBM_EBX|RBM_ESI|RBM_EDI)
504 #define RBM_INT_CALLEE_TRASH (RBM_EAX|RBM_ECX|RBM_EDX)
506 #define RBM_CALLEE_SAVED (RBM_INT_CALLEE_SAVED | RBM_FLT_CALLEE_SAVED)
507 #define RBM_CALLEE_TRASH (RBM_INT_CALLEE_TRASH | RBM_FLT_CALLEE_TRASH)
509 #define RBM_ALLINT (RBM_INT_CALLEE_SAVED | RBM_INT_CALLEE_TRASH)
511 #define REG_VAR_ORDER REG_EAX,REG_EDX,REG_ECX,REG_ESI,REG_EDI,REG_EBX
512 #define MAX_VAR_ORDER_SIZE 6
513 #define REG_TMP_ORDER REG_EAX,REG_EDX,REG_ECX,REG_EBX,REG_ESI,REG_EDI
514 #define RBM_TMP_ORDER RBM_EAX,RBM_EDX,RBM_ECX,RBM_EBX,RBM_ESI,RBM_EDI
515 #define REG_TMP_ORDER_COUNT 6
517 #define REG_PREDICT_ORDER REG_EAX,REG_EDX,REG_ECX,REG_EBX,REG_ESI,REG_EDI
519 // The order here is fixed: it must agree with an order assumed in eetwain...
520 #define REG_CALLEE_SAVED_ORDER REG_EDI,REG_ESI,REG_EBX,REG_EBP
521 #define RBM_CALLEE_SAVED_ORDER RBM_EDI,RBM_ESI,RBM_EBX,RBM_EBP
523 #define CNT_CALLEE_SAVED (4)
524 #define CNT_CALLEE_TRASH (3)
525 #define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED-1)
527 #define CNT_CALLEE_SAVED_FLOAT (0)
528 #define CNT_CALLEE_TRASH_FLOAT (6)
530 #define CALLEE_SAVED_REG_MAXSZ (CNT_CALLEE_SAVED*REGSIZE_BYTES) // EBX,ESI,EDI,EBP
532 // We reuse the ESP register as a illegal value in the register predictor
533 #define RBM_ILLEGAL RBM_ESP
534 // We reuse the ESP register as a flag for last use handling in the register predictor
535 #define RBM_LASTUSE RBM_ESP
536 // We're using the encoding for ESP to indicate a half-long on the frame
537 #define REG_L_STK REG_ESP
539 // This is the first register in REG_TMP_ORDER
540 #define REG_TMP_0 REG_EAX
541 #define RBM_TMP_0 RBM_EAX
543 // This is the second register in REG_TMP_ORDER
544 #define REG_TMP_1 REG_EDX
545 #define RBM_TMP_1 RBM_EDX
547 #define REG_PAIR_TMP REG_PAIR_EAXEDX
548 #define REG_PAIR_TMP_REVERSE REG_PAIR_EDXEAX
549 #define RBM_PAIR_TMP (RBM_EAX|RBM_EDX)
550 #define REG_PAIR_TMP_LO REG_EAX
551 #define RBM_PAIR_TMP_LO RBM_EAX
552 #define REG_PAIR_TMP_HI REG_EDX
553 #define RBM_PAIR_TMP_HI RBM_EDX
554 #define PREDICT_PAIR_TMP PREDICT_PAIR_EAXEDX
555 #define PREDICT_PAIR_TMP_LO PREDICT_REG_EAX
557 // Used when calling the 64-bit Variable shift helper
558 #define REG_LNGARG_0 REG_PAIR_EAXEDX
559 #define RBM_LNGARG_0 (RBM_EAX|RBM_EDX)
560 #define PREDICT_PAIR_LNGARG_0 PREDICT_PAIR_EAXEDX
562 #define REG_LNGARG_LO REG_EAX
563 #define RBM_LNGARG_LO RBM_EAX
564 #define REG_LNGARG_HI REG_EDX
565 #define RBM_LNGARG_HI RBM_EDX
566 // register to hold shift amount
567 #define REG_SHIFT REG_ECX
568 #define RBM_SHIFT RBM_ECX
569 #define PREDICT_REG_SHIFT PREDICT_REG_ECX
571 // register to hold shift amount when shifting 64-bit values
572 #define REG_SHIFT_LNG REG_ECX
573 #define RBM_SHIFT_LNG RBM_ECX
574 #define PREDICT_REG_SHIFT_LNG PREDICT_REG_ECX
576 // This is a general scratch register that does not conflict with the argument registers
577 #define REG_SCRATCH REG_EAX
578 #define RBM_SCRATCH RBM_EAX
580 // Where is the exception object on entry to the handler block?
581 #define REG_EXCEPTION_OBJECT REG_EAX
582 #define RBM_EXCEPTION_OBJECT RBM_EAX
584 // Only used on ARM for GTF_CALL_M_VIRTSTUB_REL_INDIRECT
585 #define REG_JUMP_THUNK_PARAM REG_EAX
586 #define RBM_JUMP_THUNK_PARAM RBM_EAX
588 #if NOGC_WRITE_BARRIERS
589 #define REG_WRITE_BARRIER REG_EDX
590 #define RBM_WRITE_BARRIER RBM_EDX
592 // We don't allow using ebp as a source register. Maybe we should only prevent this for ETW_EBP_FRAMED (but that is always set right now).
593 #define RBM_WRITE_BARRIER_SRC (RBM_EAX|RBM_ECX|RBM_EBX|RBM_ESI|RBM_EDI)
595 #define RBM_CALLEE_TRASH_NOGC RBM_EDX
596 #endif // NOGC_WRITE_BARRIERS
598 // GenericPInvokeCalliHelper unmanaged target parameter
599 #define REG_PINVOKE_TARGET_PARAM REG_EAX
600 #define RBM_PINVOKE_TARGET_PARAM RBM_EAX
602 // GenericPInvokeCalliHelper cookie parameter
603 #define REG_PINVOKE_COOKIE_PARAM REG_STK
605 // IL stub's secret parameter (JitFlags::JIT_FLAG_PUBLISH_SECRET_PARAM)
606 #define REG_SECRET_STUB_PARAM REG_EAX
607 #define RBM_SECRET_STUB_PARAM RBM_EAX
609 // VSD target address register
610 #define REG_VIRTUAL_STUB_TARGET REG_EAX
611 #define RBM_VIRTUAL_STUB_TARGET RBM_EAX
613 // Registers used by PInvoke frame setup
614 #define REG_PINVOKE_FRAME REG_EDI // EDI is p/invoke "Frame" pointer argument to CORINFO_HELP_INIT_PINVOKE_FRAME helper
615 #define RBM_PINVOKE_FRAME RBM_EDI
616 #define REG_PINVOKE_TCB REG_ESI // ESI is set to Thread Control Block (TCB) on return from
617 // CORINFO_HELP_INIT_PINVOKE_FRAME helper
618 #define RBM_PINVOKE_TCB RBM_ESI
619 #define REG_PINVOKE_SCRATCH REG_EAX // EAX is trashed by CORINFO_HELP_INIT_PINVOKE_FRAME helper
620 #define RBM_PINVOKE_SCRATCH RBM_EAX
622 #ifdef LEGACY_BACKEND
623 #define REG_SPILL_CHOICE REG_EAX
624 #define RBM_SPILL_CHOICE RBM_EAX
625 #endif // LEGACY_BACKEND
627 // The following defines are useful for iterating a regNumber
628 #define REG_FIRST REG_EAX
629 #define REG_INT_FIRST REG_EAX
630 #define REG_INT_LAST REG_EDI
631 #define REG_INT_COUNT (REG_INT_LAST - REG_INT_FIRST + 1)
632 #define REG_NEXT(reg) ((regNumber)((unsigned)(reg) + 1))
633 #define REG_PREV(reg) ((regNumber)((unsigned)(reg) - 1))
635 // genCodeForCall() moves the target address of the tailcall into this register, before pushing it on the stack
636 #define REG_TAILCALL_ADDR REG_EAX
638 // Which register are int and long values returned in ?
639 #define REG_INTRET REG_EAX
640 #define RBM_INTRET RBM_EAX
641 #define REG_LNGRET REG_PAIR_EAXEDX
642 #define RBM_LNGRET (RBM_EDX|RBM_EAX)
643 #define REG_LNGRET_LO REG_EAX
644 #define RBM_LNGRET_LO RBM_EAX
645 #define REG_LNGRET_HI REG_EDX
646 #define RBM_LNGRET_HI RBM_EDX
648 #define REG_FLOATRET REG_NA
649 #define RBM_FLOATRET RBM_NONE
650 #define RBM_DOUBLERET RBM_NONE
652 // The registers trashed by the CORINFO_HELP_STOP_FOR_GC helper
653 #define RBM_STOP_FOR_GC_TRASH RBM_CALLEE_TRASH
655 // The registers trashed by the CORINFO_HELP_INIT_PINVOKE_FRAME helper. On x86, this helper has a custom calling
656 // convention that takes EDI as argument (but doesn't trash it), trashes EAX, and returns ESI.
657 #define RBM_INIT_PINVOKE_FRAME_TRASH (RBM_PINVOKE_SCRATCH | RBM_PINVOKE_TCB)
659 #define REG_FPBASE REG_EBP
660 #define RBM_FPBASE RBM_EBP
661 #define STR_FPBASE "ebp"
662 #define REG_SPBASE REG_ESP
663 #define RBM_SPBASE RBM_ESP
664 #define STR_SPBASE "esp"
666 #define FIRST_ARG_STACK_OFFS (2*REGSIZE_BYTES) // Caller's saved EBP and return address
668 #define MAX_REG_ARG 2
669 #define MAX_FLOAT_REG_ARG 0
670 #define REG_ARG_FIRST REG_ECX
671 #define REG_ARG_LAST REG_EDX
672 #define INIT_ARG_STACK_SLOT 0 // No outgoing reserved stack slots
674 #define REG_ARG_0 REG_ECX
675 #define REG_ARG_1 REG_EDX
677 SELECTANY const regNumber intArgRegs [] = {REG_ECX, REG_EDX};
678 SELECTANY const regMaskTP intArgMasks[] = {RBM_ECX, RBM_EDX};
679 #if !FEATURE_STACK_FP_X87
680 SELECTANY const regNumber fltArgRegs [] = {REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3};
681 SELECTANY const regMaskTP fltArgMasks[] = {RBM_XMM0, RBM_XMM1, RBM_XMM2, RBM_XMM3};
682 #endif // FEATURE_STACK_FP_X87
684 #define RBM_ARG_0 RBM_ECX
685 #define RBM_ARG_1 RBM_EDX
687 #define RBM_ARG_REGS (RBM_ARG_0|RBM_ARG_1)
689 // The registers trashed by profiler enter/leave/tailcall hook
690 // See vm\i386\asmhelpers.asm for more details.
691 #define RBM_PROFILER_ENTER_TRASH RBM_NONE
692 #define RBM_PROFILER_LEAVE_TRASH RBM_NONE
693 #define RBM_PROFILER_TAILCALL_TRASH (RBM_ALLINT & ~RBM_ARG_REGS)
695 // What sort of reloc do we use for [disp32] address mode
696 #define IMAGE_REL_BASED_DISP32 IMAGE_REL_BASED_HIGHLOW
698 // What sort of reloc to we use for 'moffset' address mode (for 'mov eax, moffset' or 'mov moffset, eax')
699 #define IMAGE_REL_BASED_MOFFSET IMAGE_REL_BASED_HIGHLOW
701 // Pointer-sized string move instructions
702 #define INS_movsp INS_movsd
703 #define INS_r_movsp INS_r_movsd
704 #define INS_stosp INS_stosd
705 #define INS_r_stosp INS_r_stosd
707 #elif defined(_TARGET_AMD64_)
708 // TODO-AMD64-CQ: Fine tune the following xxBlk threshold values:
710 #define CPU_LOAD_STORE_ARCH 0
711 #define CPU_LONG_USES_REGPAIR 0
712 #define CPU_HAS_FP_SUPPORT 1
713 #define ROUND_FLOAT 0 // Do not round intermed float expression results
714 #define CPU_HAS_BYTE_REGS 0
715 #define CPU_USES_BLOCK_MOVE 1
717 #define CPBLK_MOVS_LIMIT 16 // When generating code for CpBlk, this is the buffer size
718 // threshold to stop generating rep movs and switch to the helper call.
719 // NOTE: Using rep movs is currently disabled since we found it has bad performance
720 // on pre-Ivy Bridge hardware.
722 #define CPBLK_UNROLL_LIMIT 64 // Upper bound to let the code generator to loop unroll CpBlk.
723 #define INITBLK_STOS_LIMIT 64 // When generating code for InitBlk, this is the buffer size
724 // NOTE: Using rep stos is currently disabled since we found it has bad performance
725 // on pre-Ivy Bridge hardware.
726 // threshold to stop generating rep movs and switch to the helper call.
727 #define INITBLK_UNROLL_LIMIT 128 // Upper bound to let the code generator to loop unroll InitBlk.
728 #define CPOBJ_NONGC_SLOTS_LIMIT 4 // For CpObj code generation, this is the the threshold of the number
729 // of contiguous non-gc slots that trigger generating rep movsq instead of
730 // sequences of movsq instructions
732 // The way we're currently disabling rep movs/stos is by setting a limit less than
733 // its unrolling counterparts. When lower takes the decision on which one to make it
734 // always asks for the unrolling limit first so you can say the JIT 'favors' unrolling.
735 // Setting the limit to something lower than that makes lower to never consider it.
739 #define ALIGN_SIMD_TYPES 1 // whether SIMD type locals are to be aligned
740 #if defined(UNIX_AMD64_ABI)
741 #define FEATURE_PARTIAL_SIMD_CALLEE_SAVE 0 // Whether SIMD registers are partially saved at calls
742 #else // !UNIX_AMD64_ABI
743 #define FEATURE_PARTIAL_SIMD_CALLEE_SAVE 1 // Whether SIMD registers are partially saved at calls
744 #endif // !UNIX_AMD64_ABI
746 #define FEATURE_WRITE_BARRIER 1 // Generate the WriteBarrier calls for GC (currently not the x86-style register-customized barriers)
747 #define FEATURE_FIXED_OUT_ARGS 1 // Preallocate the outgoing arg area in the prolog
748 #define FEATURE_STRUCTPROMOTE 1 // JIT Optimization to promote fields of structs into registers
749 #define FEATURE_MULTIREG_STRUCT_PROMOTE 0 // True when we want to promote fields of a multireg struct into registers
750 #define FEATURE_FASTTAILCALL 1 // Tail calls made as epilog+jmp
751 #define FEATURE_TAILCALL_OPT 1 // opportunistic Tail calls (i.e. without ".tail" prefix) made as fast tail calls.
752 #define FEATURE_SET_FLAGS 0 // Set to true to force the JIT to mark the trees with GTF_SET_FLAGS when the flags need to be set
753 #ifdef UNIX_AMD64_ABI
754 #define FEATURE_MULTIREG_ARGS_OR_RET 1 // Support for passing and/or returning single values in more than one register
755 #define FEATURE_MULTIREG_ARGS 1 // Support for passing a single argument in more than one register
756 #define FEATURE_MULTIREG_RET 1 // Support for returning a single value in more than one register
757 #define FEATURE_STRUCT_CLASSIFIER 1 // Uses a classifier function to determine if structs are passed/returned in more than one register
758 #define MAX_PASS_MULTIREG_BYTES 32 // Maximum size of a struct that could be passed in more than one register (Max is two SIMD16s)
759 #define MAX_RET_MULTIREG_BYTES 32 // Maximum size of a struct that could be returned in more than one register (Max is two SIMD16s)
760 #define MAX_ARG_REG_COUNT 2 // Maximum registers used to pass a single argument in multiple registers.
761 #define MAX_RET_REG_COUNT 2 // Maximum registers used to return a value.
762 #else // !UNIX_AMD64_ABI
763 #define WINDOWS_AMD64_ABI // Uses the Windows ABI for AMD64
764 #define FEATURE_MULTIREG_ARGS_OR_RET 0 // Support for passing and/or returning single values in more than one register
765 #define FEATURE_MULTIREG_ARGS 0 // Support for passing a single argument in more than one register
766 #define FEATURE_MULTIREG_RET 0 // Support for returning a single value in more than one register
767 #define MAX_PASS_MULTIREG_BYTES 0 // No multireg arguments
768 #define MAX_RET_MULTIREG_BYTES 0 // No multireg return values
769 #define MAX_ARG_REG_COUNT 1 // Maximum registers used to pass a single argument (no arguments are passed using multiple registers)
770 #define MAX_RET_REG_COUNT 1 // Maximum registers used to return a value.
771 #endif // !UNIX_AMD64_ABI
773 #ifdef FEATURE_USE_ASM_GC_WRITE_BARRIERS
774 #define NOGC_WRITE_BARRIERS 0 // We DO-NOT have specialized WriteBarrier JIT Helpers that DO-NOT trash the RBM_CALLEE_TRASH registers
776 #define NOGC_WRITE_BARRIERS 0 // Do not modify this -- modify the definition above. (If we're not using ASM barriers we definitely don't have NOGC barriers).
778 #define USER_ARGS_COME_LAST 1
779 #define EMIT_TRACK_STACK_DEPTH 1
780 #define TARGET_POINTER_SIZE 8 // equal to sizeof(void*) and the managed pointer size in bytes for this target
781 #define FEATURE_EH 1 // To aid platform bring-up, eliminate exceptional EH clauses (catch, filter, filter-handler, fault) and directly execute 'finally' clauses.
782 #define FEATURE_EH_FUNCLETS 1
783 #define FEATURE_EH_CALLFINALLY_THUNKS 1 // Generate call-to-finally code in "thunks" in the enclosing EH region, protected by "cloned finally" clauses.
784 #define FEATURE_STACK_FP_X87 0
785 #ifdef UNIX_AMD64_ABI
786 #define ETW_EBP_FRAMED 1 // if 1 we cannot use EBP as a scratch register and must create EBP based frames for most methods
787 #else // !UNIX_AMD64_ABI
788 #define ETW_EBP_FRAMED 0 // if 1 we cannot use EBP as a scratch register and must create EBP based frames for most methods
789 #endif // !UNIX_AMD64_ABI
790 #define FEATURE_FP_REGALLOC 0 // Enabled if RegAlloc is used to enregister Floating Point LclVars
791 #define CSE_CONSTS 1 // Enable if we want to CSE constants
793 #define RBM_ALLFLOAT (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM3 | RBM_XMM4 | RBM_XMM5 | RBM_XMM6 | RBM_XMM7 | RBM_XMM8 | RBM_XMM9 | RBM_XMM10 | RBM_XMM11 | RBM_XMM12 | RBM_XMM13 | RBM_XMM14 | RBM_XMM15)
794 #define RBM_ALLDOUBLE RBM_ALLFLOAT
795 #define REG_FP_FIRST REG_XMM0
796 #define REG_FP_LAST REG_XMM15
797 #define FIRST_FP_ARGREG REG_XMM0
799 #ifdef UNIX_AMD64_ABI
800 #define LAST_FP_ARGREG REG_XMM7
801 #else // !UNIX_AMD64_ABI
802 #define LAST_FP_ARGREG REG_XMM3
803 #endif // !UNIX_AMD64_ABI
805 #define REGNUM_BITS 6 // number of bits in a REG_*
806 #define TINY_REGNUM_BITS 6 // number used in a tiny instrdesc (same)
807 #define REGMASK_BITS 32 // number of bits in a REGNUM_MASK
808 #define REGSIZE_BYTES 8 // number of bytes in one register
809 #define XMM_REGSIZE_BYTES 16 // XMM register size in bytes
810 #define YMM_REGSIZE_BYTES 32 // YMM register size in bytes
812 #define CODE_ALIGN 1 // code alignment requirement
813 #define STACK_ALIGN 16 // stack alignment requirement
814 #define STACK_ALIGN_SHIFT 3 // Shift-right amount to convert stack size in bytes to size in pointer sized words
815 #define STACK_ALIGN_SHIFT_ALL 4 // Shift-right amount to convert stack size in bytes to size in STACK_ALIGN units
818 #define RBM_ETW_FRAMED_EBP RBM_NONE
819 #define RBM_ETW_FRAMED_EBP_LIST
820 #define REG_ETW_FRAMED_EBP_LIST
821 #define REG_ETW_FRAMED_EBP_COUNT 0
822 #else // !ETW_EBP_FRAMED
823 #define RBM_ETW_FRAMED_EBP RBM_EBP
824 #define RBM_ETW_FRAMED_EBP_LIST RBM_EBP,
825 #define REG_ETW_FRAMED_EBP_LIST REG_EBP,
826 #define REG_ETW_FRAMED_EBP_COUNT 1
827 #endif // !ETW_EBP_FRAMED
829 #ifdef UNIX_AMD64_ABI
830 #define MIN_ARG_AREA_FOR_CALL 0 // Minimum required outgoing argument space for a call.
832 #define RBM_INT_CALLEE_SAVED (RBM_EBX|RBM_ETW_FRAMED_EBP|RBM_R12|RBM_R13|RBM_R14|RBM_R15)
833 #define RBM_INT_CALLEE_TRASH (RBM_EAX|RBM_RDI|RBM_RSI|RBM_EDX|RBM_ECX|RBM_R8|RBM_R9|RBM_R10|RBM_R11)
834 #define RBM_FLT_CALLEE_SAVED (0)
835 #define RBM_FLT_CALLEE_TRASH (RBM_XMM0|RBM_XMM1|RBM_XMM2|RBM_XMM3|RBM_XMM4|RBM_XMM5|RBM_XMM6|RBM_XMM7| \
836 RBM_XMM8|RBM_XMM9|RBM_XMM10|RBM_XMM11|RBM_XMM12|RBM_XMM13|RBM_XMM14|RBM_XMM15)
837 #define REG_PROFILER_ENTER_ARG_0 REG_R14
838 #define RBM_PROFILER_ENTER_ARG_0 RBM_R14
839 #define REG_PROFILER_ENTER_ARG_1 REG_R15
840 #define RBM_PROFILER_ENTER_ARG_1 RBM_R15
842 #define REG_DEFAULT_PROFILER_CALL_TARGET REG_R11
844 #else // !UNIX_AMD64_ABI
845 #define MIN_ARG_AREA_FOR_CALL (4 * REGSIZE_BYTES) // Minimum required outgoing argument space for a call.
847 #define RBM_INT_CALLEE_SAVED (RBM_EBX|RBM_ESI|RBM_EDI|RBM_ETW_FRAMED_EBP|RBM_R12|RBM_R13|RBM_R14|RBM_R15)
848 #define RBM_INT_CALLEE_TRASH (RBM_EAX|RBM_ECX|RBM_EDX|RBM_R8|RBM_R9|RBM_R10|RBM_R11)
849 #define RBM_FLT_CALLEE_SAVED (RBM_XMM6|RBM_XMM7|RBM_XMM8|RBM_XMM9|RBM_XMM10|RBM_XMM11|RBM_XMM12|RBM_XMM13|RBM_XMM14|RBM_XMM15)
850 #define RBM_FLT_CALLEE_TRASH (RBM_XMM0|RBM_XMM1|RBM_XMM2|RBM_XMM3|RBM_XMM4|RBM_XMM5)
851 #endif // !UNIX_AMD64_ABI
853 #define REG_FLT_CALLEE_SAVED_FIRST REG_XMM6
854 #define REG_FLT_CALLEE_SAVED_LAST REG_XMM15
856 #define RBM_CALLEE_TRASH (RBM_INT_CALLEE_TRASH | RBM_FLT_CALLEE_TRASH)
857 #define RBM_CALLEE_SAVED (RBM_INT_CALLEE_SAVED | RBM_FLT_CALLEE_SAVED)
859 #define RBM_CALLEE_TRASH_NOGC RBM_CALLEE_TRASH
861 #define RBM_ALLINT (RBM_INT_CALLEE_SAVED | RBM_INT_CALLEE_TRASH)
864 #define REG_VAR_ORDER REG_EAX,REG_EDX,REG_ECX,REG_ESI,REG_EDI,REG_EBX,REG_ETW_FRAMED_EBP_LIST \
865 REG_R8,REG_R9,REG_R10,REG_R11,REG_R14,REG_R15,REG_R12,REG_R13
867 // TEMPORARY ORDER TO AVOID CALLEE-SAVES
868 // TODO-CQ: Review this and set appropriately
869 #ifdef UNIX_AMD64_ABI
870 #define REG_VAR_ORDER REG_EAX,REG_EDI,REG_ESI, \
871 REG_EDX,REG_ECX,REG_R8,REG_R9, \
872 REG_R10,REG_R11,REG_EBX,REG_ETW_FRAMED_EBP_LIST \
873 REG_R14,REG_R15,REG_R12,REG_R13
874 #else // !UNIX_AMD64_ABI
875 #define REG_VAR_ORDER REG_EAX,REG_EDX,REG_ECX, \
876 REG_R8,REG_R9,REG_R10,REG_R11, \
877 REG_ESI,REG_EDI,REG_EBX,REG_ETW_FRAMED_EBP_LIST \
878 REG_R14,REG_R15,REG_R12,REG_R13
879 #endif // !UNIX_AMD64_ABI
882 #define REG_VAR_ORDER_FLT REG_XMM0,REG_XMM1,REG_XMM2,REG_XMM3,REG_XMM4,REG_XMM5,REG_XMM6,REG_XMM7,REG_XMM8,REG_XMM9,REG_XMM10,REG_XMM11,REG_XMM12,REG_XMM13,REG_XMM14,REG_XMM15
884 #ifdef UNIX_AMD64_ABI
885 #define REG_TMP_ORDER REG_EAX,REG_EDI,REG_ESI,REG_EDX,REG_ECX,REG_EBX,REG_ETW_FRAMED_EBP_LIST \
886 REG_R8,REG_R9,REG_R10,REG_R11,REG_R14,REG_R15,REG_R12,REG_R13
887 #else // !UNIX_AMD64_ABI
888 #define MAX_VAR_ORDER_SIZE (14 + REG_ETW_FRAMED_EBP_COUNT)
889 #define REG_TMP_ORDER REG_EAX,REG_EDX,REG_ECX,REG_EBX,REG_ESI,REG_EDI,REG_ETW_FRAMED_EBP_LIST \
890 REG_R8,REG_R9,REG_R10,REG_R11,REG_R14,REG_R15,REG_R12,REG_R13
891 #endif // !UNIX_AMD64_ABI
893 #ifdef UNIX_AMD64_ABI
894 #define REG_PREDICT_ORDER REG_EAX,REG_EDI,REG_ESI,REG_EDX,REG_ECX,REG_EBX,REG_ETW_FRAMED_EBP_LIST \
895 REG_R8,REG_R9,REG_R10,REG_R11,REG_R14,REG_R15,REG_R12,REG_R13
896 #define CNT_CALLEE_SAVED (5 + REG_ETW_FRAMED_EBP_COUNT)
897 #define CNT_CALLEE_TRASH (9)
898 #define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED)
900 #define CNT_CALLEE_SAVED_FLOAT (0)
901 #define CNT_CALLEE_TRASH_FLOAT (16)
903 #define REG_CALLEE_SAVED_ORDER REG_EBX,REG_ETW_FRAMED_EBP_LIST REG_R12,REG_R13,REG_R14,REG_R15
904 #define RBM_CALLEE_SAVED_ORDER RBM_EBX,RBM_ETW_FRAMED_EBP_LIST RBM_R12,RBM_R13,RBM_R14,RBM_R15
905 #else // !UNIX_AMD64_ABI
906 #define REG_TMP_ORDER_COUNT (14 + REG_ETW_FRAMED_EBP_COUNT)
907 #define REG_PREDICT_ORDER REG_EAX,REG_EDX,REG_ECX,REG_EBX,REG_ESI,REG_EDI,REG_ETW_FRAMED_EBP_LIST \
908 REG_R8,REG_R9,REG_R10,REG_R11,REG_R14,REG_R15,REG_R12,REG_R13
909 #define CNT_CALLEE_SAVED (7 + REG_ETW_FRAMED_EBP_COUNT)
910 #define CNT_CALLEE_TRASH (7)
911 #define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED)
913 #define CNT_CALLEE_SAVED_FLOAT (10)
914 #define CNT_CALLEE_TRASH_FLOAT (6)
916 #define REG_CALLEE_SAVED_ORDER REG_EBX,REG_ESI,REG_EDI,REG_ETW_FRAMED_EBP_LIST REG_R12,REG_R13,REG_R14,REG_R15
917 #define RBM_CALLEE_SAVED_ORDER RBM_EBX,RBM_ESI,RBM_EDI,RBM_ETW_FRAMED_EBP_LIST RBM_R12,RBM_R13,RBM_R14,RBM_R15
918 #endif // !UNIX_AMD64_ABI
920 #define CALLEE_SAVED_REG_MAXSZ (CNT_CALLEE_SAVED*REGSIZE_BYTES)
921 #define CALLEE_SAVED_FLOAT_MAXSZ (CNT_CALLEE_SAVED_FLOAT*16)
923 // We reuse the ESP register as a illegal value in the register predictor
924 #define RBM_ILLEGAL RBM_ESP
925 // We reuse the ESP register as a flag for last use handling in the register predictor
926 #define RBM_LASTUSE RBM_ESP
927 // We're using the encoding for ESP to indicate a half-long on the frame
928 #define REG_L_STK REG_ESP
930 // This is the first register in REG_TMP_ORDER
931 #define REG_TMP_0 REG_EAX
932 #define RBM_TMP_0 RBM_EAX
934 // This is the second register in REG_TMP_ORDER
935 #ifdef UNIX_AMD64_ABI
936 #define REG_TMP_1 REG_EDI
937 #define RBM_TMP_1 RBM_EDI
938 #else // !UNIX_AMD64_ABI
939 #define REG_TMP_1 REG_EDX
940 #define RBM_TMP_1 RBM_EDX
941 #endif // !UNIX_AMD64_ABI
942 #define REG_PAIR_TMP REG_PAIR_EAXEDX
943 #define RBM_PAIR_TMP (RBM_EAX|RBM_EDX)
944 #define REG_PAIR_TMP_LO REG_EAX
945 #define RBM_PAIR_TMP_LO RBM_EAX
946 #define REG_PAIR_TMP_HI REG_EDX
947 #define RBM_PAIR_TMP_HI RBM_EDX
948 #define PREDICT_PAIR_TMP PREDICT_PAIR_RAXRDX
949 #define PREDICT_PAIR_TMP_LO PREDICT_REG_EAX
951 // register to hold shift amount
952 #define REG_SHIFT REG_ECX
953 #define RBM_SHIFT RBM_ECX
954 #define PREDICT_REG_SHIFT PREDICT_REG_ECX
956 // This is a general scratch register that does not conflict with the argument registers
957 #define REG_SCRATCH REG_EAX
958 #define RBM_SCRATCH RBM_EAX
960 // Where is the exception object on entry to the handler block?
961 #ifdef UNIX_AMD64_ABI
962 #define REG_EXCEPTION_OBJECT REG_ESI
963 #define RBM_EXCEPTION_OBJECT RBM_ESI
964 #else // !UNIX_AMD64_ABI
965 #define REG_EXCEPTION_OBJECT REG_EDX
966 #define RBM_EXCEPTION_OBJECT RBM_EDX
967 #endif // !UNIX_AMD64_ABI
969 #define REG_JUMP_THUNK_PARAM REG_EAX
970 #define RBM_JUMP_THUNK_PARAM RBM_EAX
972 #if NOGC_WRITE_BARRIERS
973 #define REG_WRITE_BARRIER REG_EDX
974 #define RBM_WRITE_BARRIER RBM_EDX
977 // Register to be used for emitting helper calls whose call target is an indir of an
978 // absolute memory address in case of Rel32 overflow i.e. a data address could not be
979 // encoded as PC-relative 32-bit offset.
982 // 1) that RAX is callee trash register that is not used for passing parameter and
983 // also results in smaller instruction encoding.
984 // 2) Profiler Leave callback requires the return value to be preserved
985 // in some form. We can use custom calling convention for Leave callback.
986 // For e.g return value could be preserved in rcx so that it is available for
988 #define REG_DEFAULT_HELPER_CALL_TARGET REG_RAX
989 #define RBM_DEFAULT_HELPER_CALL_TARGET RBM_RAX
991 // GenericPInvokeCalliHelper VASigCookie Parameter
992 #define REG_PINVOKE_COOKIE_PARAM REG_R11
993 #define RBM_PINVOKE_COOKIE_PARAM RBM_R11
994 #define PREDICT_REG_PINVOKE_COOKIE_PARAM PREDICT_REG_R11
996 // GenericPInvokeCalliHelper unmanaged target Parameter
997 #define REG_PINVOKE_TARGET_PARAM REG_R10
998 #define RBM_PINVOKE_TARGET_PARAM RBM_R10
999 #define PREDICT_REG_PINVOKE_TARGET_PARAM PREDICT_REG_R10
1001 // IL stub's secret MethodDesc parameter (JitFlags::JIT_FLAG_PUBLISH_SECRET_PARAM)
1002 #define REG_SECRET_STUB_PARAM REG_R10
1003 #define RBM_SECRET_STUB_PARAM RBM_R10
1005 // Registers used by PInvoke frame setup
1006 #define REG_PINVOKE_FRAME REG_EDI
1007 #define RBM_PINVOKE_FRAME RBM_EDI
1008 #define REG_PINVOKE_TCB REG_EAX
1009 #define RBM_PINVOKE_TCB RBM_EAX
1010 #define REG_PINVOKE_SCRATCH REG_EAX
1011 #define RBM_PINVOKE_SCRATCH RBM_EAX
1013 // The following defines are useful for iterating a regNumber
1014 #define REG_FIRST REG_EAX
1015 #define REG_INT_FIRST REG_EAX
1016 #define REG_INT_LAST REG_R15
1017 #define REG_INT_COUNT (REG_INT_LAST - REG_INT_FIRST + 1)
1018 #define REG_NEXT(reg) ((regNumber)((unsigned)(reg) + 1))
1019 #define REG_PREV(reg) ((regNumber)((unsigned)(reg) - 1))
1021 // genCodeForCall() moves the target address of the tailcall into this register, before pushing it on the stack
1022 #define REG_TAILCALL_ADDR REG_RDX
1024 // Which register are int and long values returned in ?
1025 #define REG_INTRET REG_EAX
1026 #define RBM_INTRET RBM_EAX
1028 #define REG_LNGRET REG_EAX
1029 #define RBM_LNGRET RBM_EAX
1031 #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING
1032 #define REG_INTRET_1 REG_RDX
1033 #define RBM_INTRET_1 RBM_RDX
1035 #define REG_LNGRET_1 REG_RDX
1036 #define RBM_LNGRET_1 RBM_RDX
1037 #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING
1040 #define REG_FLOATRET REG_XMM0
1041 #define RBM_FLOATRET RBM_XMM0
1042 #define REG_DOUBLERET REG_XMM0
1043 #define RBM_DOUBLERET RBM_XMM0
1045 #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING
1046 #define REG_FLOATRET_1 REG_XMM1
1047 #define RBM_FLOATRET_1 RBM_XMM1
1049 #define REG_DOUBLERET_1 REG_XMM1
1050 #define RBM_DOUBLERET_1 RBM_XMM1
1051 #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING
1053 #define REG_FPBASE REG_EBP
1054 #define RBM_FPBASE RBM_EBP
1055 #define STR_FPBASE "rbp"
1056 #define REG_SPBASE REG_ESP
1057 #define RBM_SPBASE RBM_ESP
1058 #define STR_SPBASE "rsp"
1060 #define FIRST_ARG_STACK_OFFS (REGSIZE_BYTES) // return address
1062 #ifdef UNIX_AMD64_ABI
1063 #define MAX_REG_ARG 6
1064 #define MAX_FLOAT_REG_ARG 8
1065 #define REG_ARG_FIRST REG_EDI
1066 #define REG_ARG_LAST REG_R9
1067 #define INIT_ARG_STACK_SLOT 0 // No outgoing reserved stack slots
1069 #define REG_ARG_0 REG_EDI
1070 #define REG_ARG_1 REG_ESI
1071 #define REG_ARG_2 REG_EDX
1072 #define REG_ARG_3 REG_ECX
1073 #define REG_ARG_4 REG_R8
1074 #define REG_ARG_5 REG_R9
1076 SELECTANY const regNumber intArgRegs [] = { REG_EDI, REG_ESI, REG_EDX, REG_ECX, REG_R8, REG_R9 };
1077 SELECTANY const regMaskTP intArgMasks[] = { RBM_EDI, RBM_ESI, RBM_EDX, RBM_ECX, RBM_R8, RBM_R9 };
1078 SELECTANY const regNumber fltArgRegs [] = { REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3, REG_XMM4, REG_XMM5, REG_XMM6, REG_XMM7 };
1079 SELECTANY const regMaskTP fltArgMasks[] = { RBM_XMM0, RBM_XMM1, RBM_XMM2, RBM_XMM3, RBM_XMM4, RBM_XMM5, RBM_XMM6, RBM_XMM7 };
1081 #define RBM_ARG_0 RBM_RDI
1082 #define RBM_ARG_1 RBM_RSI
1083 #define RBM_ARG_2 RBM_EDX
1084 #define RBM_ARG_3 RBM_ECX
1085 #define RBM_ARG_4 RBM_R8
1086 #define RBM_ARG_5 RBM_R9
1087 #else // !UNIX_AMD64_ABI
1088 #define MAX_REG_ARG 4
1089 #define MAX_FLOAT_REG_ARG 4
1090 #define REG_ARG_FIRST REG_ECX
1091 #define REG_ARG_LAST REG_R9
1092 #define INIT_ARG_STACK_SLOT 4 // 4 outgoing reserved stack slots
1094 #define REG_ARG_0 REG_ECX
1095 #define REG_ARG_1 REG_EDX
1096 #define REG_ARG_2 REG_R8
1097 #define REG_ARG_3 REG_R9
1099 SELECTANY const regNumber intArgRegs [] = { REG_ECX, REG_EDX, REG_R8, REG_R9 };
1100 SELECTANY const regMaskTP intArgMasks[] = { RBM_ECX, RBM_EDX, RBM_R8, RBM_R9 };
1101 SELECTANY const regNumber fltArgRegs [] = { REG_XMM0, REG_XMM1, REG_XMM2, REG_XMM3 };
1102 SELECTANY const regMaskTP fltArgMasks[] = { RBM_XMM0, RBM_XMM1, RBM_XMM2, RBM_XMM3 };
1104 #define RBM_ARG_0 RBM_ECX
1105 #define RBM_ARG_1 RBM_EDX
1106 #define RBM_ARG_2 RBM_R8
1107 #define RBM_ARG_3 RBM_R9
1108 #endif // !UNIX_AMD64_ABI
1110 #define REG_FLTARG_0 REG_XMM0
1111 #define REG_FLTARG_1 REG_XMM1
1112 #define REG_FLTARG_2 REG_XMM2
1113 #define REG_FLTARG_3 REG_XMM3
1115 #define RBM_FLTARG_0 RBM_XMM0
1116 #define RBM_FLTARG_1 RBM_XMM1
1117 #define RBM_FLTARG_2 RBM_XMM2
1118 #define RBM_FLTARG_3 RBM_XMM3
1120 #ifdef UNIX_AMD64_ABI
1121 #define REG_FLTARG_4 REG_XMM4
1122 #define REG_FLTARG_5 REG_XMM5
1123 #define REG_FLTARG_6 REG_XMM6
1124 #define REG_FLTARG_7 REG_XMM7
1126 #define RBM_FLTARG_4 RBM_XMM4
1127 #define RBM_FLTARG_5 RBM_XMM5
1128 #define RBM_FLTARG_6 RBM_XMM6
1129 #define RBM_FLTARG_7 RBM_XMM7
1131 #define RBM_ARG_REGS (RBM_ARG_0|RBM_ARG_1|RBM_ARG_2|RBM_ARG_3|RBM_ARG_4|RBM_ARG_5)
1132 #define RBM_FLTARG_REGS (RBM_FLTARG_0|RBM_FLTARG_1|RBM_FLTARG_2|RBM_FLTARG_3|RBM_FLTARG_4|RBM_FLTARG_5|RBM_FLTARG_6|RBM_FLTARG_7)
1133 #else // !UNIX_AMD64_ABI
1134 #define RBM_ARG_REGS (RBM_ARG_0|RBM_ARG_1|RBM_ARG_2|RBM_ARG_3)
1135 #define RBM_FLTARG_REGS (RBM_FLTARG_0|RBM_FLTARG_1|RBM_FLTARG_2|RBM_FLTARG_3)
1136 #endif // !UNIX_AMD64_ABI
1138 // The registers trashed by profiler enter/leave/tailcall hook
1139 // See vm\amd64\asmhelpers.asm for more details.
1140 #define RBM_PROFILER_ENTER_TRASH RBM_CALLEE_TRASH
1141 #define RBM_PROFILER_LEAVE_TRASH (RBM_CALLEE_TRASH & ~(RBM_FLOATRET | RBM_INTRET))
1142 #define RBM_PROFILER_TAILCALL_TRASH RBM_PROFILER_LEAVE_TRASH
1144 // The registers trashed by the CORINFO_HELP_STOP_FOR_GC helper.
1145 #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING
1146 // See vm\amd64\unixasmhelpers.S for more details.
1148 // On Unix a struct of size >=9 and <=16 bytes in size is returned in two return registers.
1149 // The return registers could be any two from the set { RAX, RDX, XMM0, XMM1 }.
1150 // STOP_FOR_GC helper preserves all the 4 possible return registers.
1151 #define RBM_STOP_FOR_GC_TRASH (RBM_CALLEE_TRASH & ~(RBM_FLOATRET | RBM_INTRET | RBM_FLOATRET_1 | RBM_INTRET_1))
1153 // See vm\amd64\asmhelpers.asm for more details.
1154 #define RBM_STOP_FOR_GC_TRASH (RBM_CALLEE_TRASH & ~(RBM_FLOATRET | RBM_INTRET))
1157 // The registers trashed by the CORINFO_HELP_INIT_PINVOKE_FRAME helper.
1158 #define RBM_INIT_PINVOKE_FRAME_TRASH RBM_CALLEE_TRASH
1160 // What sort of reloc do we use for [disp32] address mode
1161 #define IMAGE_REL_BASED_DISP32 IMAGE_REL_BASED_REL32
1163 // What sort of reloc to we use for 'moffset' address mode (for 'mov eax, moffset' or 'mov moffset, eax')
1164 #define IMAGE_REL_BASED_MOFFSET IMAGE_REL_BASED_DIR64
1166 // Pointer-sized string move instructions
1167 #define INS_movsp INS_movsq
1168 #define INS_r_movsp INS_r_movsq
1169 #define INS_stosp INS_stosq
1170 #define INS_r_stosp INS_r_stosq
1172 #elif defined(_TARGET_ARM_)
1174 // TODO-ARM-CQ: Use shift for division by power of 2
1175 // TODO-ARM-CQ: Check for sdiv/udiv at runtime and generate it if available
1176 #define USE_HELPERS_FOR_INT_DIV 1 // BeagleBoard (ARMv7A) doesn't support SDIV/UDIV
1177 #define CPU_LOAD_STORE_ARCH 1
1178 #ifdef LEGACY_BACKEND
1179 #define CPU_LONG_USES_REGPAIR 1
1181 #define CPU_LONG_USES_REGPAIR 0
1183 #define CPU_HAS_FP_SUPPORT 1
1184 #define ROUND_FLOAT 0 // Do not round intermed float expression results
1185 #define CPU_HAS_BYTE_REGS 0
1186 #define CPU_USES_BLOCK_MOVE 0
1188 #define CPBLK_UNROLL_LIMIT 32 // Upper bound to let the code generator to loop unroll CpBlk.
1189 #define INITBLK_UNROLL_LIMIT 32 // Upper bound to let the code generator to loop unroll InitBlk.
1191 #define FEATURE_WRITE_BARRIER 1 // Generate the proper WriteBarrier calls for GC
1192 #define FEATURE_FIXED_OUT_ARGS 1 // Preallocate the outgoing arg area in the prolog
1193 #define FEATURE_STRUCTPROMOTE 1 // JIT Optimization to promote fields of structs into registers
1194 #define FEATURE_MULTIREG_STRUCT_PROMOTE 0 // True when we want to promote fields of a multireg struct into registers
1195 #define FEATURE_FASTTAILCALL 0 // Tail calls made as epilog+jmp
1196 #define FEATURE_TAILCALL_OPT 0 // opportunistic Tail calls (i.e. without ".tail" prefix) made as fast tail calls.
1197 #define FEATURE_SET_FLAGS 1 // Set to true to force the JIT to mark the trees with GTF_SET_FLAGS when the flags need to be set
1198 #define FEATURE_MULTIREG_ARGS_OR_RET 1 // Support for passing and/or returning single values in more than one register (including HFA support)
1199 #define FEATURE_MULTIREG_ARGS 1 // Support for passing a single argument in more than one register (including passing HFAs)
1200 #define FEATURE_MULTIREG_RET 1 // Support for returning a single value in more than one register (including HFA returns)
1201 #define FEATURE_STRUCT_CLASSIFIER 0 // Uses a classifier function to determine is structs are passed/returned in more than one register
1202 #define MAX_PASS_MULTIREG_BYTES 32 // Maximum size of a struct that could be passed in more than one register (Max is an HFA of 4 doubles)
1203 #define MAX_RET_MULTIREG_BYTES 32 // Maximum size of a struct that could be returned in more than one register (Max is an HFA of 4 doubles)
1204 #define MAX_ARG_REG_COUNT 4 // Maximum registers used to pass a single argument in multiple registers. (max is 4 floats or doubles using an HFA)
1205 #define MAX_RET_REG_COUNT 4 // Maximum registers used to return a value.
1207 #ifdef FEATURE_USE_ASM_GC_WRITE_BARRIERS
1208 #define NOGC_WRITE_BARRIERS 0 // We DO-NOT have specialized WriteBarrier JIT Helpers that DO-NOT trash the RBM_CALLEE_TRASH registers
1210 #define NOGC_WRITE_BARRIERS 0 // Do not modify this -- modify the definition above. (If we're not using ASM barriers we definitely don't have NOGC barriers).
1212 #define USER_ARGS_COME_LAST 1
1213 #define EMIT_TRACK_STACK_DEPTH 1 // This is something of a workaround. For both ARM and AMD64, the frame size is fixed, so we don't really
1214 // need to track stack depth, but this is currently necessary to get GC information reported at call sites.
1215 #define TARGET_POINTER_SIZE 4 // equal to sizeof(void*) and the managed pointer size in bytes for this target
1216 #define FEATURE_EH 1 // To aid platform bring-up, eliminate exceptional EH clauses (catch, filter, filter-handler, fault) and directly execute 'finally' clauses.
1217 #define FEATURE_EH_FUNCLETS 1
1218 #define FEATURE_EH_CALLFINALLY_THUNKS 0 // Generate call-to-finally code in "thunks" in the enclosing EH region, protected by "cloned finally" clauses.
1219 #define FEATURE_STACK_FP_X87 0
1220 #define ETW_EBP_FRAMED 1 // if 1 we cannot use REG_FP as a scratch register and must setup the frame pointer for most methods
1221 #define FEATURE_FP_REGALLOC 1 // Enabled if RegAlloc is used to enregister Floating Point LclVars
1222 #define CSE_CONSTS 1 // Enable if we want to CSE constants
1224 #define REG_FP_FIRST REG_F0
1225 #define REG_FP_LAST REG_F31
1226 #define FIRST_FP_ARGREG REG_F0
1227 #define LAST_FP_ARGREG REG_F15
1229 #define REGNUM_BITS 6 // number of bits in a REG_*
1230 #define TINY_REGNUM_BITS 4 // number of bits we will use for a tiny instr desc (may not use float)
1231 #define REGMASK_BITS 64 // number of bits in a REGNUM_MASK
1232 #define REGSIZE_BYTES 4 // number of bytes in one register
1233 #define MIN_ARG_AREA_FOR_CALL 0 // Minimum required outgoing argument space for a call.
1235 #define CODE_ALIGN 2 // code alignment requirement
1236 #define STACK_ALIGN 8 // stack alignment requirement
1237 #define STACK_ALIGN_SHIFT 2 // Shift-right amount to convert stack size in bytes to size in DWORD_PTRs
1239 #define RBM_INT_CALLEE_SAVED (RBM_R4|RBM_R5|RBM_R6|RBM_R7|RBM_R8|RBM_R9|RBM_R10)
1240 #define RBM_INT_CALLEE_TRASH (RBM_R0|RBM_R1|RBM_R2|RBM_R3|RBM_R12|RBM_LR)
1241 #define RBM_FLT_CALLEE_SAVED (RBM_F16|RBM_F17|RBM_F18|RBM_F19|RBM_F20|RBM_F21|RBM_F22|RBM_F23|RBM_F24|RBM_F25|RBM_F26|RBM_F27|RBM_F28|RBM_F29|RBM_F30|RBM_F31)
1242 #define RBM_FLT_CALLEE_TRASH (RBM_F0|RBM_F1|RBM_F2|RBM_F3|RBM_F4|RBM_F5|RBM_F6|RBM_F7|RBM_F8|RBM_F9|RBM_F10|RBM_F11|RBM_F12|RBM_F13|RBM_F14|RBM_F15)
1244 #define RBM_CALLEE_SAVED (RBM_INT_CALLEE_SAVED | RBM_FLT_CALLEE_SAVED)
1245 #define RBM_CALLEE_TRASH (RBM_INT_CALLEE_TRASH | RBM_FLT_CALLEE_TRASH)
1247 #define REG_DEFAULT_HELPER_CALL_TARGET REG_R12
1248 #define RBM_DEFAULT_HELPER_CALL_TARGET RBM_R12
1250 #define RBM_CALLEE_TRASH_NOGC (RBM_R2|RBM_R3|RBM_LR|RBM_DEFAULT_HELPER_CALL_TARGET)
1252 #define REG_FASTTAILCALL_TARGET REG_R12 // Target register for fast tail call
1253 #define RBM_FASTTAILCALL_TARGET RBM_R12
1255 #define RBM_ALLINT (RBM_INT_CALLEE_SAVED | RBM_INT_CALLEE_TRASH)
1256 #define RBM_ALLFLOAT (RBM_FLT_CALLEE_SAVED | RBM_FLT_CALLEE_TRASH)
1257 #define RBM_ALLDOUBLE (RBM_F0|RBM_F2|RBM_F4|RBM_F6|RBM_F8|RBM_F10|RBM_F12|RBM_F14|RBM_F16|RBM_F18|RBM_F20|RBM_F22|RBM_F24|RBM_F26|RBM_F28|RBM_F30)
1259 #define REG_VAR_ORDER REG_R3,REG_R2,REG_R1,REG_R0,REG_R4,REG_LR,REG_R12,\
1260 REG_R5,REG_R6,REG_R7,REG_R8,REG_R9,REG_R10
1262 #define REG_VAR_ORDER_FLT REG_F8, REG_F9, REG_F10, REG_F11, \
1263 REG_F12, REG_F13, REG_F14, REG_F15, \
1264 REG_F6, REG_F7, REG_F4, REG_F5, \
1265 REG_F2, REG_F3, REG_F0, REG_F1, \
1266 REG_F16, REG_F17, REG_F18, REG_F19, \
1267 REG_F20, REG_F21, REG_F22, REG_F23, \
1268 REG_F24, REG_F25, REG_F26, REG_F27, \
1269 REG_F28, REG_F29, REG_F30, REG_F31,
1271 #define MAX_VAR_ORDER_SIZE 32
1273 #define REG_TMP_ORDER REG_R3,REG_R2,REG_R1,REG_R0, REG_R4,REG_R5,REG_R6,REG_R7,\
1274 REG_LR,REG_R12, REG_R8,REG_R9,REG_R10
1275 #define REG_TMP_ORDER_COUNT 13
1277 #define REG_FLT_TMP_ORDER REG_F14, REG_F15, REG_F12, REG_F13, \
1278 REG_F10, REG_F11, REG_F8, REG_F9, \
1279 REG_F6, REG_F7, REG_F4, REG_F5, \
1280 REG_F2, REG_F3, REG_F0, REG_F1, \
1281 REG_F16, REG_F17, REG_F18, REG_F19, \
1282 REG_F20, REG_F21, REG_F22, REG_F23, \
1283 REG_F24, REG_F25, REG_F26, REG_F27, \
1284 REG_F28, REG_F29, REG_F30, REG_F31,
1286 #define REG_FLT_TMP_ORDER_COUNT 32
1288 #define REG_PREDICT_ORDER REG_LR,REG_R12,REG_R3,REG_R2,REG_R1,REG_R0, \
1289 REG_R7,REG_R6,REG_R5,REG_R4,REG_R8,REG_R9,REG_R10
1291 #define RBM_LOW_REGS (RBM_R0|RBM_R1|RBM_R2|RBM_R3|RBM_R4|RBM_R5|RBM_R6|RBM_R7)
1292 #define RBM_HIGH_REGS (RBM_R8|RBM_R9|RBM_R10|RBM_R11|RBM_R12|RBM_SP|RBM_LR|RBM_PC)
1294 #define REG_CALLEE_SAVED_ORDER REG_R4,REG_R5,REG_R6,REG_R7,REG_R8,REG_R9,REG_R10,REG_R11
1295 #define RBM_CALLEE_SAVED_ORDER RBM_R4,RBM_R5,RBM_R6,RBM_R7,RBM_R8,RBM_R9,RBM_R10,RBM_R11
1297 #define CNT_CALLEE_SAVED (8)
1298 #define CNT_CALLEE_TRASH (6)
1299 #define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED-1)
1301 #define CNT_CALLEE_SAVED_FLOAT (16)
1302 #define CNT_CALLEE_TRASH_FLOAT (16)
1304 #define CALLEE_SAVED_REG_MAXSZ (CNT_CALLEE_SAVED*REGSIZE_BYTES)
1305 #define CALLEE_SAVED_FLOAT_MAXSZ (CNT_CALLEE_SAVED_FLOAT*sizeof(float))
1307 // We reuse the ESP register as a illegal value in the register predictor
1308 #define RBM_ILLEGAL RBM_SP
1309 // We reuse the ESP register as a flag for last use handling in the register predictor
1310 #define RBM_LASTUSE RBM_SP
1311 // We're using the encoding for ESP to indicate a half-long on the frame
1312 #define REG_L_STK REG_SP
1314 // This is the first register in REG_TMP_ORDER
1315 #define REG_TMP_0 REG_R3
1316 #define RBM_TMP_0 RBM_R3
1318 // This is the second register in REG_TMP_ORDER
1319 #define REG_TMP_1 REG_R2
1320 #define RBM_TMP_1 RBM_R2
1322 #ifndef LEGACY_BACKEND
1323 // Temporary registers used for the GS cookie check.
1324 #define REG_GSCOOKIE_TMP_0 REG_R12
1325 #define REG_GSCOOKIE_TMP_1 REG_LR
1326 #endif // !LEGACY_BACKEND
1328 // This is the first register pair in REG_TMP_ORDER
1329 #define REG_PAIR_TMP REG_PAIR_R2R3
1330 #define REG_PAIR_TMP_REVERSE REG_PAIR_R3R2
1331 #define RBM_PAIR_TMP (RBM_R2|RBM_R3)
1332 #define REG_PAIR_TMP_LO REG_R2
1333 #define RBM_PAIR_TMP_LO RBM_R2
1334 #define REG_PAIR_TMP_HI REG_R3
1335 #define RBM_PAIR_TMP_HI RBM_R3
1336 #define PREDICT_PAIR_TMP PREDICT_PAIR_R2R3
1337 #define PREDICT_PAIR_TMP_LO PREDICT_REG_R2
1339 // Used when calling the 64-bit Variable shift helper
1340 #define REG_LNGARG_0 REG_PAIR_R0R1
1341 #define RBM_LNGARG_0 (RBM_R0|RBM_R1)
1342 #define PREDICT_PAIR_LNGARG_0 PREDICT_PAIR_R0R1
1344 // register to hold shift amount; no special register is required on the ARM
1345 #define REG_SHIFT REG_NA
1346 #define RBM_SHIFT RBM_ALLINT
1347 #define PREDICT_REG_SHIFT PREDICT_REG
1349 // register to hold shift amount when shifting 64-bit values (this uses a helper call)
1350 #define REG_SHIFT_LNG REG_R2 // REG_ARG_2
1351 #define RBM_SHIFT_LNG RBM_R2 // RBM_ARG_2
1352 #define PREDICT_REG_SHIFT_LNG PREDICT_REG_R2
1355 // This is a general scratch register that does not conflict with the argument registers
1356 #define REG_SCRATCH REG_LR
1357 #define RBM_SCRATCH RBM_LR
1359 // This is a general register that can be optionally reserved for other purposes during codegen
1360 #define REG_OPT_RSVD REG_R10
1361 #define RBM_OPT_RSVD RBM_R10
1363 // We reserve R9 to store SP on entry for stack unwinding when localloc is used
1364 #define REG_SAVED_LOCALLOC_SP REG_R9
1365 #define RBM_SAVED_LOCALLOC_SP RBM_R9
1367 // Where is the exception object on entry to the handler block?
1368 #define REG_EXCEPTION_OBJECT REG_R0
1369 #define RBM_EXCEPTION_OBJECT RBM_R0
1371 #define REG_JUMP_THUNK_PARAM REG_R12
1372 #define RBM_JUMP_THUNK_PARAM RBM_R12
1374 #if NOGC_WRITE_BARRIERS
1375 #define REG_WRITE_BARRIER REG_R1
1376 #define RBM_WRITE_BARRIER RBM_R1
1379 //In the ARM case, registers of write barrier use the normal argument registers.
1380 #define REG_WRITE_BARRIER_SRC_BYREF REG_ARG_1
1381 #define RBM_WRITE_BARRIER_SRC_BYREF RBM_ARG_1
1383 #define REG_WRITE_BARRIER_DST_BYREF REG_ARG_0
1384 #define RBM_WRITE_BARRIER_DST_BYREF RBM_ARG_0
1386 // GenericPInvokeCalliHelper VASigCookie Parameter
1387 #define REG_PINVOKE_COOKIE_PARAM REG_R4
1388 #define RBM_PINVOKE_COOKIE_PARAM RBM_R4
1389 #define PREDICT_REG_PINVOKE_COOKIE_PARAM PREDICT_REG_R4
1391 // GenericPInvokeCalliHelper unmanaged target Parameter
1392 #define REG_PINVOKE_TARGET_PARAM REG_R12
1393 #define RBM_PINVOKE_TARGET_PARAM RBM_R12
1394 #define PREDICT_REG_PINVOKE_TARGET_PARAM PREDICT_REG_R12
1396 // IL stub's secret MethodDesc parameter (JitFlags::JIT_FLAG_PUBLISH_SECRET_PARAM)
1397 #define REG_SECRET_STUB_PARAM REG_R12
1398 #define RBM_SECRET_STUB_PARAM RBM_R12
1400 // R2R indirect call. Use the same registers as VSD
1401 #define REG_R2R_INDIRECT_PARAM REG_R4
1402 #define RBM_R2R_INDIRECT_PARAM RBM_R4
1404 // Registers used by PInvoke frame setup
1405 #define REG_PINVOKE_FRAME REG_R4
1406 #define RBM_PINVOKE_FRAME RBM_R4
1407 #define REG_PINVOKE_TCB REG_R5
1408 #define RBM_PINVOKE_TCB RBM_R5
1409 #define REG_PINVOKE_SCRATCH REG_R6
1410 #define RBM_PINVOKE_SCRATCH RBM_R6
1412 #ifdef LEGACY_BACKEND
1413 #define REG_SPILL_CHOICE REG_LR
1414 #define RBM_SPILL_CHOICE RBM_LR
1415 #define REG_SPILL_CHOICE_FLT REG_F14
1416 #define RBM_SPILL_CHOICE_FLT (RBM_F14|RBM_F15)
1417 #endif // LEGACY_BACKEND
1419 // The following defines are useful for iterating a regNumber
1420 #define REG_FIRST REG_R0
1421 #define REG_INT_FIRST REG_R0
1422 #define REG_INT_LAST REG_LR
1423 #define REG_INT_COUNT (REG_INT_LAST - REG_INT_FIRST + 1)
1424 #define REG_NEXT(reg) ((regNumber)((unsigned)(reg) + 1))
1425 #define REG_PREV(reg) ((regNumber)((unsigned)(reg) - 1))
1427 // genCodeForCall() moves the target address of the tailcall into this register, before pushing it on the stack
1428 #define REG_TAILCALL_ADDR REG_R1
1430 // The following registers are used in emitting Enter/Leave/Tailcall profiler callbacks
1431 #define REG_PROFILER_ENTER_ARG REG_R0
1432 #define RBM_PROFILER_ENTER_ARG RBM_R0
1433 #define REG_PROFILER_RET_SCRATCH REG_R2
1434 #define RBM_PROFILER_RET_SCRATCH RBM_R2
1435 #define RBM_PROFILER_RET_USED (RBM_R0 | RBM_R1 | RBM_R2)
1436 #define REG_PROFILER_JMP_ARG REG_R0
1437 #define RBM_PROFILER_JMP_USED RBM_R0
1438 #define RBM_PROFILER_TAIL_USED (RBM_R0 | RBM_R12 | RBM_LR)
1441 // Which register are int and long values returned in ?
1442 #define REG_INTRET REG_R0
1443 #define RBM_INTRET RBM_R0
1444 #define REG_LNGRET REG_PAIR_R0R1
1445 #define RBM_LNGRET (RBM_R1|RBM_R0)
1446 #define REG_LNGRET_LO REG_R0
1447 #define REG_LNGRET_HI REG_R1
1448 #define RBM_LNGRET_LO RBM_R0
1449 #define RBM_LNGRET_HI RBM_R1
1451 #define REG_FLOATRET REG_F0
1452 #define RBM_FLOATRET RBM_F0
1453 #define RBM_DOUBLERET (RBM_F0|RBM_F1)
1455 // The registers trashed by the CORINFO_HELP_STOP_FOR_GC helper (JIT_RareDisableHelper).
1456 // See vm\arm\amshelpers.asm for more details.
1457 #define RBM_STOP_FOR_GC_TRASH (RBM_CALLEE_TRASH & ~(RBM_LNGRET|RBM_R7|RBM_R8|RBM_R11|RBM_DOUBLERET|RBM_F2|RBM_F3|RBM_F4|RBM_F5|RBM_F6|RBM_F7))
1459 // The registers trashed by the CORINFO_HELP_INIT_PINVOKE_FRAME helper.
1460 #define RBM_INIT_PINVOKE_FRAME_TRASH (RBM_CALLEE_TRASH | RBM_PINVOKE_TCB | RBM_PINVOKE_SCRATCH)
1462 #define REG_FPBASE REG_R11
1463 #define RBM_FPBASE RBM_R11
1464 #define STR_FPBASE "r11"
1465 #define REG_SPBASE REG_SP
1466 #define RBM_SPBASE RBM_SP
1467 #define STR_SPBASE "sp"
1469 #define FIRST_ARG_STACK_OFFS (2*REGSIZE_BYTES) // Caller's saved FP and return address
1471 #define MAX_REG_ARG 4
1472 #define MAX_FLOAT_REG_ARG 16
1473 #define MAX_HFA_RET_SLOTS 8
1475 #define REG_ARG_FIRST REG_R0
1476 #define REG_ARG_LAST REG_R3
1477 #define REG_ARG_FP_FIRST REG_F0
1478 #define REG_ARG_FP_LAST REG_F7
1479 #define INIT_ARG_STACK_SLOT 0 // No outgoing reserved stack slots
1481 #define REG_ARG_0 REG_R0
1482 #define REG_ARG_1 REG_R1
1483 #define REG_ARG_2 REG_R2
1484 #define REG_ARG_3 REG_R3
1486 SELECTANY const regNumber intArgRegs [] = {REG_R0, REG_R1, REG_R2, REG_R3};
1487 SELECTANY const regMaskTP intArgMasks[] = {RBM_R0, RBM_R1, RBM_R2, RBM_R3};
1489 #define RBM_ARG_0 RBM_R0
1490 #define RBM_ARG_1 RBM_R1
1491 #define RBM_ARG_2 RBM_R2
1492 #define RBM_ARG_3 RBM_R3
1494 #define RBM_ARG_REGS (RBM_ARG_0|RBM_ARG_1|RBM_ARG_2|RBM_ARG_3)
1495 #define RBM_FLTARG_REGS (RBM_F0|RBM_F1|RBM_F2|RBM_F3|RBM_F4|RBM_F5|RBM_F6|RBM_F7|RBM_F8|RBM_F9|RBM_F10|RBM_F11|RBM_F12|RBM_F13|RBM_F14|RBM_F15)
1496 #define RBM_DBL_REGS RBM_ALLDOUBLE
1498 SELECTANY const regNumber fltArgRegs [] = {REG_F0, REG_F1, REG_F2, REG_F3, REG_F4, REG_F5, REG_F6, REG_F7, REG_F8, REG_F9, REG_F10, REG_F11, REG_F12, REG_F13, REG_F14, REG_F15 };
1499 SELECTANY const regMaskTP fltArgMasks[] = {RBM_F0, RBM_F1, RBM_F2, RBM_F3, RBM_F4, RBM_F5, RBM_F6, RBM_F7, RBM_F8, RBM_F9, RBM_F10, RBM_F11, RBM_F12, RBM_F13, RBM_F14, RBM_F15 };
1501 #define LBL_DIST_SMALL_MAX_NEG (0)
1502 #define LBL_DIST_SMALL_MAX_POS (+1020)
1503 #define LBL_DIST_MED_MAX_NEG (-4095)
1504 #define LBL_DIST_MED_MAX_POS (+4096)
1506 #define JMP_DIST_SMALL_MAX_NEG (-2048)
1507 #define JMP_DIST_SMALL_MAX_POS (+2046)
1509 #define CALL_DIST_MAX_NEG (-16777216)
1510 #define CALL_DIST_MAX_POS (+16777214)
1512 #define JCC_DIST_SMALL_MAX_NEG (-256)
1513 #define JCC_DIST_SMALL_MAX_POS (+254)
1515 #define JCC_DIST_MEDIUM_MAX_NEG (-1048576)
1516 #define JCC_DIST_MEDIUM_MAX_POS (+1048574)
1518 #define LBL_SIZE_SMALL (2)
1520 #define JMP_SIZE_SMALL (2)
1521 #define JMP_SIZE_LARGE (4)
1523 #define JCC_SIZE_SMALL (2)
1524 #define JCC_SIZE_MEDIUM (4)
1525 #define JCC_SIZE_LARGE (6)
1527 #elif defined(_TARGET_ARM64_)
1529 #define CPU_LOAD_STORE_ARCH 1
1530 #define CPU_LONG_USES_REGPAIR 0
1531 #define CPU_HAS_FP_SUPPORT 1
1532 #define ROUND_FLOAT 0 // Do not round intermed float expression results
1533 #define CPU_HAS_BYTE_REGS 0
1534 #define CPU_USES_BLOCK_MOVE 0
1536 #define CPBLK_UNROLL_LIMIT 64 // Upper bound to let the code generator to loop unroll CpBlk.
1537 #define INITBLK_UNROLL_LIMIT 64 // Upper bound to let the code generator to loop unroll InitBlk.
1540 #define ALIGN_SIMD_TYPES 1 // whether SIMD type locals are to be aligned
1541 #define FEATURE_PARTIAL_SIMD_CALLEE_SAVE 1 // Whether SIMD registers are partially saved at calls
1542 #endif // FEATURE_SIMD
1544 #define FEATURE_WRITE_BARRIER 1 // Generate the proper WriteBarrier calls for GC
1545 #define FEATURE_FIXED_OUT_ARGS 1 // Preallocate the outgoing arg area in the prolog
1546 #define FEATURE_STRUCTPROMOTE 1 // JIT Optimization to promote fields of structs into registers
1547 #define FEATURE_MULTIREG_STRUCT_PROMOTE 1 // True when we want to promote fields of a multireg struct into registers
1548 #define FEATURE_FASTTAILCALL 1 // Tail calls made as epilog+jmp
1549 #define FEATURE_TAILCALL_OPT 1 // opportunistic Tail calls (i.e. without ".tail" prefix) made as fast tail calls.
1550 #define FEATURE_SET_FLAGS 0 // Set to true to force the JIT to mark the trees with GTF_SET_FLAGS when the flags need to be set
1551 #define FEATURE_MULTIREG_ARGS_OR_RET 1 // Support for passing and/or returning single values in more than one register
1552 #define FEATURE_MULTIREG_ARGS 1 // Support for passing a single argument in more than one register
1553 #define FEATURE_MULTIREG_RET 1 // Support for returning a single value in more than one register
1554 #define FEATURE_STRUCT_CLASSIFIER 0 // Uses a classifier function to determine is structs are passed/returned in more than one register
1555 #define MAX_PASS_MULTIREG_BYTES 32 // Maximum size of a struct that could be passed in more than one register (max is 4 doubles using an HFA)
1556 #define MAX_RET_MULTIREG_BYTES 32 // Maximum size of a struct that could be returned in more than one register (Max is an HFA of 4 doubles)
1557 #define MAX_ARG_REG_COUNT 4 // Maximum registers used to pass a single argument in multiple registers. (max is 4 floats or doubles using an HFA)
1558 #define MAX_RET_REG_COUNT 4 // Maximum registers used to return a value.
1560 #ifdef FEATURE_USE_ASM_GC_WRITE_BARRIERS
1561 #define NOGC_WRITE_BARRIERS 1 // We have specialized WriteBarrier JIT Helpers that DO-NOT trash the RBM_CALLEE_TRASH registers
1563 #define NOGC_WRITE_BARRIERS 0 // Do not modify this -- modify the definition above. (If we're not using ASM barriers we definitely don't have NOGC barriers).
1565 #define USER_ARGS_COME_LAST 1
1566 #define EMIT_TRACK_STACK_DEPTH 1 // This is something of a workaround. For both ARM and AMD64, the frame size is fixed, so we don't really
1567 // need to track stack depth, but this is currently necessary to get GC information reported at call sites.
1568 #define TARGET_POINTER_SIZE 8 // equal to sizeof(void*) and the managed pointer size in bytes for this target
1569 #define FEATURE_EH 1 // To aid platform bring-up, eliminate exceptional EH clauses (catch, filter, filter-handler, fault) and directly execute 'finally' clauses.
1570 #define FEATURE_EH_FUNCLETS 1
1571 #define FEATURE_EH_CALLFINALLY_THUNKS 1 // Generate call-to-finally code in "thunks" in the enclosing EH region, protected by "cloned finally" clauses.
1572 #define FEATURE_STACK_FP_X87 0
1573 #define ETW_EBP_FRAMED 1 // if 1 we cannot use REG_FP as a scratch register and must setup the frame pointer for most methods
1574 #define FEATURE_FP_REGALLOC 0 // Enabled if RegAlloc is used to enregister Floating Point LclVars
1575 #define CSE_CONSTS 1 // Enable if we want to CSE constants
1577 #define REG_FP_FIRST REG_V0
1578 #define REG_FP_LAST REG_V31
1579 #define FIRST_FP_ARGREG REG_V0
1580 #define LAST_FP_ARGREG REG_V15
1582 #define REGNUM_BITS 6 // number of bits in a REG_*
1583 #define TINY_REGNUM_BITS 5 // number of bits we will use for a tiny instr desc (may not use float)
1584 #define REGMASK_BITS 64 // number of bits in a REGNUM_MASK
1585 #define REGSIZE_BYTES 8 // number of bytes in one general purpose register
1586 #define FP_REGSIZE_BYTES 16 // number of bytes in one FP/SIMD register
1587 #define FPSAVE_REGSIZE_BYTES 8 // number of bytes in one FP/SIMD register that are saved/restored, for callee-saved registers
1589 #define MIN_ARG_AREA_FOR_CALL 0 // Minimum required outgoing argument space for a call.
1591 #define CODE_ALIGN 4 // code alignment requirement
1592 #define STACK_ALIGN 16 // stack alignment requirement
1593 #define STACK_ALIGN_SHIFT 3 // Shift-right amount to convert stack size in bytes to size in DWORD_PTRs
1595 #define RBM_INT_CALLEE_SAVED (RBM_R19|RBM_R20|RBM_R21|RBM_R22|RBM_R23|RBM_R24|RBM_R25|RBM_R26|RBM_R27|RBM_R28)
1596 #define RBM_INT_CALLEE_TRASH (RBM_R0|RBM_R1|RBM_R2|RBM_R3|RBM_R4|RBM_R5|RBM_R6|RBM_R7|RBM_R8|RBM_R9|RBM_R10|RBM_R11|RBM_R12|RBM_R13|RBM_R14|RBM_R15|RBM_IP0|RBM_IP1|RBM_LR)
1597 #define RBM_FLT_CALLEE_SAVED (RBM_V8|RBM_V9|RBM_V10|RBM_V11|RBM_V12|RBM_V13|RBM_V14|RBM_V15)
1598 #define RBM_FLT_CALLEE_TRASH (RBM_V0|RBM_V1|RBM_V2|RBM_V3|RBM_V4|RBM_V5|RBM_V6|RBM_V7|RBM_V16|RBM_V17|RBM_V18|RBM_V19|RBM_V20|RBM_V21|RBM_V22|RBM_V23|RBM_V24|RBM_V25|RBM_V26|RBM_V27|RBM_V28|RBM_V29|RBM_V30|RBM_V31)
1600 #define RBM_CALLEE_SAVED (RBM_INT_CALLEE_SAVED | RBM_FLT_CALLEE_SAVED)
1601 #define RBM_CALLEE_TRASH (RBM_INT_CALLEE_TRASH | RBM_FLT_CALLEE_TRASH)
1603 #define REG_DEFAULT_HELPER_CALL_TARGET REG_R12
1604 #define RBM_DEFAULT_HELPER_CALL_TARGET RBM_R12
1606 // REVIEW: why does arm64 RBM_CALLEE_TRASH_NOGC include IP1? The JIT_ByRefWriteBarrier only trashes r12 and r15.
1607 #define RBM_CALLEE_TRASH_NOGC (RBM_R12|RBM_R15|RBM_IP1|RBM_DEFAULT_HELPER_CALL_TARGET)
1609 #define REG_FASTTAILCALL_TARGET REG_IP0 // Target register for fast tail call
1610 #define RBM_FASTTAILCALL_TARGET RBM_IP0
1612 #define RBM_ALLINT (RBM_INT_CALLEE_SAVED | RBM_INT_CALLEE_TRASH)
1613 #define RBM_ALLFLOAT (RBM_FLT_CALLEE_SAVED | RBM_FLT_CALLEE_TRASH)
1614 #define RBM_ALLDOUBLE RBM_ALLFLOAT
1616 #define REG_VAR_ORDER REG_R9,REG_R10,REG_R11,REG_R12,REG_R13,REG_R14,REG_R15,\
1617 REG_R8,REG_R7,REG_R6,REG_R5,REG_R4,REG_R3,REG_R2,REG_R1,REG_R0,\
1618 REG_R19,REG_R20,REG_R21,REG_R22,REG_R23,REG_R24,REG_R25,REG_R26,REG_R27,REG_R28,\
1620 #define REG_VAR_ORDER_FLT REG_V16, REG_V17, REG_V18, REG_V19, \
1621 REG_V20, REG_V21, REG_V22, REG_V23, \
1622 REG_V24, REG_V25, REG_V26, REG_V27, \
1623 REG_V28, REG_V29, REG_V30, REG_V31, \
1624 REG_V7, REG_V6, REG_V5, REG_V4, \
1625 REG_V8, REG_V9, REG_V10, REG_V11, \
1626 REG_V12, REG_V13, REG_V14, REG_V15, \
1627 REG_V3, REG_V2, REG_V1, REG_V0
1629 #define REG_CALLEE_SAVED_ORDER REG_R19,REG_R20,REG_R21,REG_R22,REG_R23,REG_R24,REG_R25,REG_R26,REG_R27,REG_R28
1630 #define RBM_CALLEE_SAVED_ORDER RBM_R19,RBM_R20,RBM_R21,RBM_R22,RBM_R23,RBM_R24,RBM_R25,RBM_R26,RBM_R27,RBM_R28
1632 #define CNT_CALLEE_SAVED (11)
1633 #define CNT_CALLEE_TRASH (17)
1634 #define CNT_CALLEE_ENREG (CNT_CALLEE_SAVED-1)
1636 #define CNT_CALLEE_SAVED_FLOAT (8)
1637 #define CNT_CALLEE_TRASH_FLOAT (24)
1639 #define CALLEE_SAVED_REG_MAXSZ (CNT_CALLEE_SAVED * REGSIZE_BYTES)
1640 #define CALLEE_SAVED_FLOAT_MAXSZ (CNT_CALLEE_SAVED_FLOAT * FPSAVE_REGSIZE_BYTES)
1642 // TODO-ARM64-Cleanup: Remove this
1643 #define REG_L_STK REG_ZR
1645 // This is the first register in REG_TMP_ORDER
1646 #define REG_TMP_0 REG_R9
1647 #define RBM_TMP_0 RBM_R9
1649 // This is the second register in REG_TMP_ORDER
1650 #define REG_TMP_1 REG_R10
1651 #define RBM_TMP_1 RBM_R10
1653 // Temporary registers used for the GS cookie check.
1654 #define REG_GSCOOKIE_TMP_0 REG_R9
1655 #define REG_GSCOOKIE_TMP_1 REG_R10
1657 // register to hold shift amount; no special register is required on ARM64.
1658 #define REG_SHIFT REG_NA
1659 #define RBM_SHIFT RBM_ALLINT
1660 #define PREDICT_REG_SHIFT PREDICT_REG
1662 // This is a general scratch register that does not conflict with the argument registers
1663 #define REG_SCRATCH REG_R9
1664 #define RBM_SCRATCH RBM_R9
1666 // This is a general register that can be optionally reserved for other purposes during codegen
1667 #define REG_OPT_RSVD REG_IP1
1668 #define RBM_OPT_RSVD RBM_IP1
1670 // Where is the exception object on entry to the handler block?
1671 #define REG_EXCEPTION_OBJECT REG_R0
1672 #define RBM_EXCEPTION_OBJECT RBM_R0
1674 #define REG_JUMP_THUNK_PARAM REG_R12
1675 #define RBM_JUMP_THUNK_PARAM RBM_R12
1677 #if NOGC_WRITE_BARRIERS
1678 #define REG_WRITE_BARRIER_SRC_BYREF REG_R13
1679 #define RBM_WRITE_BARRIER_SRC_BYREF RBM_R13
1681 #define REG_WRITE_BARRIER_DST_BYREF REG_R14
1682 #define RBM_WRITE_BARRIER_DST_BYREF RBM_R14
1684 #define REG_WRITE_BARRIER REG_R15
1685 #define RBM_WRITE_BARRIER RBM_R15
1688 // GenericPInvokeCalliHelper VASigCookie Parameter
1689 #define REG_PINVOKE_COOKIE_PARAM REG_R15
1690 #define RBM_PINVOKE_COOKIE_PARAM RBM_R15
1691 #define PREDICT_REG_PINVOKE_COOKIE_PARAM PREDICT_REG_R15
1693 // GenericPInvokeCalliHelper unmanaged target Parameter
1694 #define REG_PINVOKE_TARGET_PARAM REG_R14
1695 #define RBM_PINVOKE_TARGET_PARAM RBM_R14
1696 #define PREDICT_REG_PINVOKE_TARGET_PARAM PREDICT_REG_R14
1698 // IL stub's secret MethodDesc parameter (JitFlags::JIT_FLAG_PUBLISH_SECRET_PARAM)
1699 #define REG_SECRET_STUB_PARAM REG_R12
1700 #define RBM_SECRET_STUB_PARAM RBM_R12
1702 // R2R indirect call. Use the same registers as VSD
1703 #define REG_R2R_INDIRECT_PARAM REG_R11
1704 #define RBM_R2R_INDIRECT_PARAM RBM_R11
1706 // Registers used by PInvoke frame setup
1707 #define REG_PINVOKE_FRAME REG_R9
1708 #define RBM_PINVOKE_FRAME RBM_R9
1709 #define REG_PINVOKE_TCB REG_R10
1710 #define RBM_PINVOKE_TCB RBM_R10
1711 #define REG_PINVOKE_SCRATCH REG_R10
1712 #define RBM_PINVOKE_SCRATCH RBM_R10
1714 // The following defines are useful for iterating a regNumber
1715 #define REG_FIRST REG_R0
1716 #define REG_INT_FIRST REG_R0
1717 #define REG_INT_LAST REG_ZR
1718 #define REG_INT_COUNT (REG_INT_LAST - REG_INT_FIRST + 1)
1719 #define REG_NEXT(reg) ((regNumber)((unsigned)(reg) + 1))
1720 #define REG_PREV(reg) ((regNumber)((unsigned)(reg) - 1))
1722 // genCodeForCall() moves the target address of the tailcall into this register, before pushing it on the stack
1723 #define REG_TAILCALL_ADDR REG_R9
1725 // The following registers are used in emitting Enter/Leave/Tailcall profiler callbacks
1726 #define REG_PROFILER_ENTER_ARG REG_R0
1727 #define RBM_PROFILER_ENTER_ARG RBM_R0
1728 #define REG_PROFILER_RET_SCRATCH REG_R2
1729 #define RBM_PROFILER_RET_SCRATCH RBM_R2
1730 #define RBM_PROFILER_RET_USED (RBM_R0 | RBM_R1 | RBM_R2)
1731 #define REG_PROFILER_JMP_ARG REG_R0
1732 #define RBM_PROFILER_JMP_USED RBM_R0
1733 #define RBM_PROFILER_TAIL_USED (RBM_R0 | RBM_R12 | RBM_LR)
1736 // Which register are int and long values returned in ?
1737 #define REG_INTRET REG_R0
1738 #define RBM_INTRET RBM_R0
1739 #define REG_LNGRET REG_R0
1740 #define RBM_LNGRET RBM_R0
1741 // second return register for 16-byte structs
1742 #define REG_INTRET_1 REG_R1
1743 #define RBM_INTRET_1 RBM_R1
1745 #define REG_FLOATRET REG_V0
1746 #define RBM_FLOATRET RBM_V0
1747 #define RBM_DOUBLERET RBM_V0
1749 // The registers trashed by the CORINFO_HELP_STOP_FOR_GC helper
1750 #define RBM_STOP_FOR_GC_TRASH RBM_CALLEE_TRASH
1752 // The registers trashed by the CORINFO_HELP_INIT_PINVOKE_FRAME helper.
1753 #define RBM_INIT_PINVOKE_FRAME_TRASH RBM_CALLEE_TRASH
1755 #define REG_FPBASE REG_FP
1756 #define RBM_FPBASE RBM_FP
1757 #define STR_FPBASE "fp"
1758 #define REG_SPBASE REG_SP
1759 #define RBM_SPBASE RBM_ZR // reuse the RBM for REG_ZR
1760 #define STR_SPBASE "sp"
1762 #define FIRST_ARG_STACK_OFFS (2*REGSIZE_BYTES) // Caller's saved FP and return address
1764 // On ARM64 the calling convention defines REG_R8 (x8) as an additional argument register
1765 // It isn't allocated for the normal user arguments, so it isn't counted by MAX_REG_ARG
1766 // whether we use this register to pass the RetBuff is controlled by the function hasFixedRetBuffReg()
1767 // it is consider to be the next integer argnum, which is 8
1769 #define REG_ARG_RET_BUFF REG_R8
1770 #define RBM_ARG_RET_BUFF RBM_R8
1771 #define RET_BUFF_ARGNUM 8
1773 #define MAX_REG_ARG 8
1774 #define MAX_FLOAT_REG_ARG 8
1776 #define REG_ARG_FIRST REG_R0
1777 #define REG_ARG_LAST REG_R7
1778 #define REG_ARG_FP_FIRST REG_V0
1779 #define REG_ARG_FP_LAST REG_V7
1780 #define INIT_ARG_STACK_SLOT 0 // No outgoing reserved stack slots
1782 #define REG_ARG_0 REG_R0
1783 #define REG_ARG_1 REG_R1
1784 #define REG_ARG_2 REG_R2
1785 #define REG_ARG_3 REG_R3
1786 #define REG_ARG_4 REG_R4
1787 #define REG_ARG_5 REG_R5
1788 #define REG_ARG_6 REG_R6
1789 #define REG_ARG_7 REG_R7
1791 SELECTANY const regNumber intArgRegs [] = {REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7};
1792 SELECTANY const regMaskTP intArgMasks[] = {RBM_R0, RBM_R1, RBM_R2, RBM_R3, RBM_R4, RBM_R5, RBM_R6, RBM_R7};
1794 #define RBM_ARG_0 RBM_R0
1795 #define RBM_ARG_1 RBM_R1
1796 #define RBM_ARG_2 RBM_R2
1797 #define RBM_ARG_3 RBM_R3
1798 #define RBM_ARG_4 RBM_R4
1799 #define RBM_ARG_5 RBM_R5
1800 #define RBM_ARG_6 RBM_R6
1801 #define RBM_ARG_7 RBM_R7
1803 #define REG_FLTARG_0 REG_V0
1804 #define REG_FLTARG_1 REG_V1
1805 #define REG_FLTARG_2 REG_V2
1806 #define REG_FLTARG_3 REG_V3
1807 #define REG_FLTARG_4 REG_V4
1808 #define REG_FLTARG_5 REG_V5
1809 #define REG_FLTARG_6 REG_V6
1810 #define REG_FLTARG_7 REG_V7
1812 #define RBM_FLTARG_0 RBM_V0
1813 #define RBM_FLTARG_1 RBM_V1
1814 #define RBM_FLTARG_2 RBM_V2
1815 #define RBM_FLTARG_3 RBM_V3
1816 #define RBM_FLTARG_4 RBM_V4
1817 #define RBM_FLTARG_5 RBM_V5
1818 #define RBM_FLTARG_6 RBM_V6
1819 #define RBM_FLTARG_7 RBM_V7
1821 #define RBM_ARG_REGS (RBM_ARG_0|RBM_ARG_1|RBM_ARG_2|RBM_ARG_3|RBM_ARG_4|RBM_ARG_5|RBM_ARG_6|RBM_ARG_7)
1822 #define RBM_FLTARG_REGS (RBM_FLTARG_0|RBM_FLTARG_1|RBM_FLTARG_2|RBM_FLTARG_3|RBM_FLTARG_4|RBM_FLTARG_5|RBM_FLTARG_6|RBM_FLTARG_7)
1824 SELECTANY const regNumber fltArgRegs [] = {REG_V0, REG_V1, REG_V2, REG_V3, REG_V4, REG_V5, REG_V6, REG_V7 };
1825 SELECTANY const regMaskTP fltArgMasks[] = {RBM_V0, RBM_V1, RBM_V2, RBM_V3, RBM_V4, RBM_V5, RBM_V6, RBM_V7 };
1827 #define LBL_DIST_SMALL_MAX_NEG (-1048576)
1828 #define LBL_DIST_SMALL_MAX_POS (+1048575)
1830 #define LBL_SIZE_SMALL (4)
1831 #define LBL_SIZE_LARGE (8)
1833 #define JCC_DIST_SMALL_MAX_NEG (-1048576)
1834 #define JCC_DIST_SMALL_MAX_POS (+1048575)
1836 #define TB_DIST_SMALL_MAX_NEG (-32768)
1837 #define TB_DIST_SMALL_MAX_POS (+32767)
1839 #define JCC_SIZE_SMALL (4)
1840 #define JCC_SIZE_LARGE (8)
1842 #define LDC_DIST_SMALL_MAX_NEG (-1048576)
1843 #define LDC_DIST_SMALL_MAX_POS (+1048575)
1845 #define LDC_SIZE_SMALL (4)
1846 #define LDC_SIZE_LARGE (8)
1848 #define JMP_SIZE_SMALL (4)
1851 #error Unsupported or unset target architecture
1854 #ifdef _TARGET_XARCH_
1856 #define JMP_DIST_SMALL_MAX_NEG (-128)
1857 #define JMP_DIST_SMALL_MAX_POS (+127)
1859 #define JCC_DIST_SMALL_MAX_NEG (-128)
1860 #define JCC_DIST_SMALL_MAX_POS (+127)
1862 #define JMP_SIZE_SMALL (2)
1863 #define JMP_SIZE_LARGE (5)
1865 #define JCC_SIZE_SMALL (2)
1866 #define JCC_SIZE_LARGE (6)
1868 #define PUSH_INST_SIZE (5)
1869 #define CALL_INST_SIZE (5)
1871 #endif // _TARGET_XARCH_
1873 C_ASSERT(REG_FIRST == 0);
1874 C_ASSERT(REG_INT_FIRST < REG_INT_LAST);
1875 C_ASSERT(REG_FP_FIRST < REG_FP_LAST);
1877 // Opportunistic tail call feature converts non-tail prefixed calls into
1878 // tail calls where possible. It requires fast tail calling mechanism for
1879 // performance. Otherwise, we are better off not converting non-tail prefixed
1880 // calls into tail calls.
1881 C_ASSERT((FEATURE_TAILCALL_OPT == 0) || (FEATURE_FASTTAILCALL == 1));
1883 /*****************************************************************************/
1885 #define BITS_PER_BYTE 8
1886 #define REGNUM_MASK ((1 << REGNUM_BITS) - 1) // a n-bit mask use to encode multiple REGNUMs into a unsigned int
1887 #define RBM_ALL(type) (varTypeIsFloating(type) ? RBM_ALLFLOAT : RBM_ALLINT)
1889 /*****************************************************************************/
1891 #if CPU_HAS_BYTE_REGS
1892 #define RBM_BYTE_REGS (RBM_EAX|RBM_ECX|RBM_EDX|RBM_EBX)
1893 #define RBM_NON_BYTE_REGS (RBM_ESI|RBM_EDI)
1894 // We reuse the ESP register as a flag for byteable registers in lvPrefReg
1895 #define RBM_BYTE_REG_FLAG RBM_ESP
1897 #define RBM_BYTE_REGS RBM_ALLINT
1898 #define RBM_NON_BYTE_REGS RBM_NONE
1899 #define RBM_BYTE_REG_FLAG RBM_NONE
1903 /*****************************************************************************/
1907 static const char* g_tgtCPUName;
1908 static const char* g_tgtPlatformName;
1915 static const enum ArgOrder g_tgtArgOrder;
1917 #if NOGC_WRITE_BARRIERS
1918 static regMaskTP exclude_WriteBarrierReg(regMaskTP mask)
1920 unsigned result = (mask & ~RBM_WRITE_BARRIER);
1924 return RBM_ALLINT & ~RBM_WRITE_BARRIER;
1926 #endif // NOGC_WRITE_BARRIERS
1929 #if defined(DEBUG) || defined(LATE_DISASM)
1930 const char* getRegName(unsigned reg, bool isFloat = false); // this is for gcencode.cpp and disasm.cpp that don't use
1931 // the regNumber type
1932 const char* getRegName(regNumber reg, bool isFloat = false);
1933 #endif // defined(DEBUG) || defined(LATE_DISASM)
1936 const char* getRegNameFloat(regNumber reg, var_types type);
1937 extern void dspRegMask(regMaskTP regMask, size_t minSiz = 0);
1940 #if CPU_HAS_BYTE_REGS
1941 inline BOOL isByteReg(regNumber reg)
1943 return (reg <= REG_EBX);
1946 inline BOOL isByteReg(regNumber reg)
1952 #ifdef LEGACY_BACKEND
1953 extern const regNumber raRegTmpOrder[REG_TMP_ORDER_COUNT];
1954 extern const regNumber rpRegTmpOrder[REG_TMP_ORDER_COUNT];
1955 #if FEATURE_FP_REGALLOC
1956 extern const regNumber raRegFltTmpOrder[REG_FLT_TMP_ORDER_COUNT];
1958 #endif // LEGACY_BACKEND
1960 inline regMaskTP genRegMask(regNumber reg);
1961 inline regMaskTP genRegMaskFloat(regNumber reg, var_types type = TYP_DOUBLE);
1963 /*****************************************************************************
1964 * Return true if the register number is valid
1966 inline bool genIsValidReg(regNumber reg)
1968 /* It's safest to perform an unsigned comparison in case reg is negative */
1969 return ((unsigned)reg < (unsigned)REG_COUNT);
1972 /*****************************************************************************
1973 * Return true if the register is a valid integer register
1975 inline bool genIsValidIntReg(regNumber reg)
1977 return reg >= REG_INT_FIRST && reg <= REG_INT_LAST;
1980 /*****************************************************************************
1981 * Return true if the register is a valid floating point register
1983 inline bool genIsValidFloatReg(regNumber reg)
1985 return reg >= REG_FP_FIRST && reg <= REG_FP_LAST;
1990 /*****************************************************************************
1991 * Return true if the register is a valid floating point double register
1993 inline bool genIsValidDoubleReg(regNumber reg)
1995 return genIsValidFloatReg(reg) && (((reg - REG_FP_FIRST) & 0x1) == 0);
1998 #endif // _TARGET_ARM_
2000 //-------------------------------------------------------------------------------------------
2001 // hasFixedRetBuffReg:
2002 // Returns true if our target architecture uses a fixed return buffer register
2004 inline bool hasFixedRetBuffReg()
2006 #ifdef _TARGET_ARM64_
2013 //-------------------------------------------------------------------------------------------
2014 // theFixedRetBuffReg:
2015 // Returns the regNumber to use for the fixed return buffer
2017 inline regNumber theFixedRetBuffReg()
2019 assert(hasFixedRetBuffReg()); // This predicate should be checked before calling this method
2020 #ifdef _TARGET_ARM64_
2021 return REG_ARG_RET_BUFF;
2027 //-------------------------------------------------------------------------------------------
2028 // theFixedRetBuffMask:
2029 // Returns the regNumber to use for the fixed return buffer
2031 inline regMaskTP theFixedRetBuffMask()
2033 assert(hasFixedRetBuffReg()); // This predicate should be checked before calling this method
2034 #ifdef _TARGET_ARM64_
2035 return RBM_ARG_RET_BUFF;
2041 //-------------------------------------------------------------------------------------------
2042 // theFixedRetBuffArgNum:
2043 // Returns the argNum to use for the fixed return buffer
2045 inline unsigned theFixedRetBuffArgNum()
2047 assert(hasFixedRetBuffReg()); // This predicate should be checked before calling this method
2048 #ifdef _TARGET_ARM64_
2049 return RET_BUFF_ARGNUM;
2055 //-------------------------------------------------------------------------------------------
2056 // fullIntArgRegMask:
2057 // Returns the full mask of all possible integer registers
2058 // Note this includes the fixed return buffer register on Arm64
2060 inline regMaskTP fullIntArgRegMask()
2062 if (hasFixedRetBuffReg())
2064 return RBM_ARG_REGS | theFixedRetBuffMask();
2068 return RBM_ARG_REGS;
2072 //-------------------------------------------------------------------------------------------
2073 // isValidIntArgReg:
2074 // Returns true if the register is a valid integer argument register
2075 // Note this method also returns true on Arm64 when 'reg' is the RetBuff register
2077 inline bool isValidIntArgReg(regNumber reg)
2079 return (genRegMask(reg) & fullIntArgRegMask()) != 0;
2082 //-------------------------------------------------------------------------------------------
2084 // Given a register that is an integer or floating point argument register
2085 // returns the next argument register
2087 regNumber genRegArgNext(regNumber argReg);
2089 //-------------------------------------------------------------------------------------------
2090 // isValidFloatArgReg:
2091 // Returns true if the register is a valid floating-point argument register
2093 inline bool isValidFloatArgReg(regNumber reg)
2101 return (reg >= FIRST_FP_ARGREG) && (reg <= LAST_FP_ARGREG);
2105 /*****************************************************************************
2107 * Can the register hold the argument type?
2111 inline bool floatRegCanHoldType(regNumber reg, var_types type)
2113 assert(genIsValidFloatReg(reg));
2114 if (type == TYP_DOUBLE)
2116 return ((reg - REG_F0) % 2) == 0;
2120 // Can be TYP_STRUCT for HFA. It's not clear that's correct; what about
2121 // HFA of double? We wouldn't be asserting the right alignment, and
2122 // callers like genRegMaskFloat() wouldn't be generating the right mask.
2124 assert((type == TYP_FLOAT) || (type == TYP_STRUCT));
2129 // AMD64: xmm registers can hold any float type
2130 // x86: FP stack can hold any float type
2131 // ARM64: Floating-point/SIMD registers can hold any type.
2132 inline bool floatRegCanHoldType(regNumber reg, var_types type)
2138 /*****************************************************************************
2140 * Map a register number to a register mask.
2143 extern const regMaskSmall regMasks[REG_COUNT];
2145 inline regMaskTP genRegMask(regNumber reg)
2147 assert((unsigned)reg < ArrLen(regMasks));
2148 #ifdef _TARGET_AMD64_
2149 // shift is faster than a L1 hit on modern x86
2150 // (L1 latency on sandy bridge is 4 cycles for [base] and 5 for [base + index*c] )
2151 // the reason this is AMD-only is because the x86 BE will try to get reg masks for REG_STK
2152 // and the result needs to be zero.
2153 regMaskTP result = 1 << reg;
2154 assert(result == regMasks[reg]);
2157 return regMasks[reg];
2161 /*****************************************************************************
2163 * Map a register number to a floating-point register mask.
2166 #if defined(_TARGET_X86_) && defined(LEGACY_BACKEND)
2167 extern const regMaskSmall regFPMasks[REG_FPCOUNT];
2168 #endif // defined(_TARGET_X86_) && defined(LEGACY_BACKEND)
2170 inline regMaskTP genRegMaskFloat(regNumber reg, var_types type /* = TYP_DOUBLE */)
2172 #if defined(_TARGET_X86_) && defined(LEGACY_BACKEND)
2173 assert(reg >= REG_FPV0 && reg < REG_FPCOUNT);
2174 assert((unsigned)reg < ArrLen(regFPMasks));
2175 return regFPMasks[reg];
2176 #elif defined(_TARGET_AMD64_) || defined(_TARGET_ARM64_) || defined(_TARGET_X86_)
2177 assert(genIsValidFloatReg(reg));
2178 assert((unsigned)reg < ArrLen(regMasks));
2179 return regMasks[reg];
2180 #elif defined _TARGET_ARM_
2181 assert(floatRegCanHoldType(reg, type));
2182 assert(reg >= REG_F0 && reg <= REG_F31);
2184 if (type == TYP_DOUBLE)
2186 return regMasks[reg] | regMasks[reg + 1];
2190 return regMasks[reg];
2193 #error Unsupported or unset target architecture
2197 //------------------------------------------------------------------------
2198 // genRegMask: Given a register, and its type, generate the appropriate regMask
2201 // regNum - the register of interest
2202 // type - the type of regNum (i.e. the type it is being used as)
2205 // This will usually return the same value as genRegMask(regNum), but
2206 // on architectures where multiple registers are used for certain types
2207 // (e.g. TYP_DOUBLE on ARM), it will return a regMask that includes
2208 // all the registers.
2209 // Registers that are used in pairs, but separately named (e.g. TYP_LONG
2210 // on ARM) will return just the regMask for the given register.
2213 // For registers that are used in pairs, the caller will be handling
2214 // each member of the pair separately.
2216 inline regMaskTP genRegMask(regNumber regNum, var_types type)
2218 #ifndef _TARGET_ARM_
2219 return genRegMask(regNum);
2221 regMaskTP regMask = RBM_NONE;
2223 if (varTypeIsFloating(type))
2225 regMask = genRegMaskFloat(regNum, type);
2229 regMask = genRegMask(regNum);
2235 /*****************************************************************************
2237 * These arrays list the callee-saved register numbers (and bitmaps, respectively) for
2238 * the current architecture.
2240 extern const regNumber raRegCalleeSaveOrder[CNT_CALLEE_SAVED];
2241 extern const regMaskTP raRbmCalleeSaveOrder[CNT_CALLEE_SAVED];
2243 // This method takes a "compact" bitset of the callee-saved registers, and "expands" it to a full register mask.
2244 regMaskSmall genRegMaskFromCalleeSavedMask(unsigned short);
2246 /*****************************************************************************
2248 * Returns the register that holds the low 32 bits of the long value given
2249 * by the register pair 'regPair'.
2251 inline regNumber genRegPairLo(regPairNo regPair)
2253 assert(regPair >= REG_PAIR_FIRST && regPair <= REG_PAIR_LAST);
2255 return (regNumber)((regPair - REG_PAIR_FIRST) & REG_PAIR_NMASK);
2258 /*****************************************************************************
2260 * Returns the register that holds the high 32 bits of the long value given
2261 * by the register pair 'regPair'.
2263 inline regNumber genRegPairHi(regPairNo regPair)
2265 assert(regPair >= REG_PAIR_FIRST && regPair <= REG_PAIR_LAST);
2267 return (regNumber)(((regPair - REG_PAIR_FIRST) >> REG_PAIR_NBITS) & REG_PAIR_NMASK);
2270 /*****************************************************************************
2272 * Returns whether regPair is a combination of two "real" registers
2273 * or whether it contains a pseudo register.
2275 * In debug it also asserts that reg1 and reg2 are not the same.
2277 bool genIsProperRegPair(regPairNo regPair);
2279 /*****************************************************************************
2281 * Returns the register pair number that corresponds to the given two regs.
2283 inline regPairNo gen2regs2pair(regNumber regLo, regNumber regHi)
2285 assert(regLo != regHi || regLo == REG_STK);
2286 assert(genIsValidReg(regLo) && genIsValidReg(regHi));
2287 assert(regLo != REG_L_STK && regHi != REG_L_STK);
2289 regPairNo regPair = (regPairNo)(regLo + (regHi << REG_PAIR_NBITS) + REG_PAIR_FIRST);
2291 assert(regLo == genRegPairLo(regPair));
2292 assert(regHi == genRegPairHi(regPair));
2297 /*****************************************************************************/
2298 inline regMaskTP genRegPairMask(regPairNo regPair)
2300 assert(regPair >= REG_PAIR_FIRST && regPair <= REG_PAIR_LAST);
2302 return genRegMask(genRegPairLo(regPair)) | genRegMask(genRegPairHi(regPair));
2305 /*****************************************************************************
2307 * Assumes that "reg" is of the given "type". Return the next unused reg number after "reg"
2308 * of this type, else REG_NA if there are no more.
2311 inline regNumber regNextOfType(regNumber reg, var_types type)
2313 regNumber regReturn;
2316 if (type == TYP_DOUBLE)
2318 // Skip odd FP registers for double-precision types
2319 assert(floatRegCanHoldType(reg, type));
2320 regReturn = regNumber(reg + 2);
2324 regReturn = REG_NEXT(reg);
2326 #else // _TARGET_ARM_
2327 regReturn = REG_NEXT(reg);
2330 if (varTypeIsFloating(type))
2332 if (regReturn > REG_FP_LAST)
2339 if (regReturn > REG_INT_LAST)
2348 /*****************************************************************************
2353 inline bool isRegPairType(int /* s/b "var_types" */ type)
2355 #if !CPU_LONG_USES_REGPAIR
2358 #ifdef _TARGET_64BIT_
2360 #elif CPU_HAS_FP_SUPPORT
2361 return type == TYP_LONG;
2363 return type == TYP_LONG || type == TYP_DOUBLE;
2365 #endif // CPU_LONG_USES_REGPAIR
2368 inline bool isFloatRegType(int /* s/b "var_types" */ type)
2370 #if CPU_HAS_FP_SUPPORT
2371 return type == TYP_DOUBLE || type == TYP_FLOAT;
2377 // If the WINDOWS_AMD64_ABI is defined make sure that _TARGET_AMD64_ is also defined.
2378 #if defined(WINDOWS_AMD64_ABI)
2379 #if !defined(_TARGET_AMD64_)
2380 #error When WINDOWS_AMD64_ABI is defined you must define _TARGET_AMD64_ defined as well.
2384 /*****************************************************************************/
2385 // Some sanity checks on some of the register masks
2386 // Stack pointer is never part of RBM_ALLINT
2387 C_ASSERT((RBM_ALLINT & RBM_SPBASE) == RBM_NONE);
2388 C_ASSERT((RBM_INT_CALLEE_SAVED & RBM_SPBASE) == RBM_NONE);
2391 // Frame pointer isn't either if we're supporting ETW frame chaining
2392 C_ASSERT((RBM_ALLINT & RBM_FPBASE) == RBM_NONE);
2393 C_ASSERT((RBM_INT_CALLEE_SAVED & RBM_FPBASE) == RBM_NONE);
2395 /*****************************************************************************/
2397 #ifdef _TARGET_64BIT_
2398 typedef unsigned __int64 target_size_t;
2400 typedef unsigned int target_size_t;
2403 C_ASSERT(sizeof(target_size_t) == TARGET_POINTER_SIZE);
2405 /*****************************************************************************/
2406 #endif // _TARGET_H_
2407 /*****************************************************************************/
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