1 // Licensed to the .NET Foundation under one or more agreements.
2 // The .NET Foundation licenses this file to you under the MIT license.
3 // See the LICENSE file in the project root for more information.
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8 XX Register Requirements for ARM XX
10 XX This encapsulates all the logic for setting register requirements for XX
11 XX the ARM architecture. XX
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23 #ifndef LEGACY_BACKEND // This file is ONLY used for the RyuJIT backend that uses the linear scan register allocator
28 #include "sideeffects.h"
32 //------------------------------------------------------------------------
33 // TreeNodeInfoInitReturn: Set the NodeInfo for a GT_RETURN.
36 // tree - The node of interest
41 void Lowering::TreeNodeInfoInitReturn(GenTree* tree)
43 ContainCheckRet(tree->AsOp());
45 TreeNodeInfo* info = &(tree->gtLsraInfo);
46 LinearScan* l = m_lsra;
47 Compiler* compiler = comp;
48 GenTree* op1 = tree->gtGetOp1();
50 if (tree->TypeGet() == TYP_LONG)
52 assert((op1->OperGet() == GT_LONG) && op1->isContained());
53 GenTree* loVal = op1->gtGetOp1();
54 GenTree* hiVal = op1->gtGetOp2();
56 loVal->gtLsraInfo.setSrcCandidates(l, RBM_LNGRET_LO);
57 hiVal->gtLsraInfo.setSrcCandidates(l, RBM_LNGRET_HI);
62 regMaskTP useCandidates = RBM_NONE;
64 info->srcCount = ((tree->TypeGet() == TYP_VOID) || op1->isContained()) ? 0 : 1;
67 if (varTypeIsStruct(tree))
69 // op1 has to be either an lclvar or a multi-reg returning call
70 if (op1->OperGet() != GT_LCL_VAR)
72 noway_assert(op1->IsMultiRegCall());
74 ReturnTypeDesc* retTypeDesc = op1->AsCall()->GetReturnTypeDesc();
75 info->srcCount = retTypeDesc->GetReturnRegCount();
76 useCandidates = retTypeDesc->GetABIReturnRegs();
81 // Non-struct type return - determine useCandidates
82 switch (tree->TypeGet())
85 useCandidates = RBM_NONE;
88 useCandidates = RBM_FLOATRET;
91 useCandidates = RBM_DOUBLERET;
94 useCandidates = RBM_LNGRET;
97 useCandidates = RBM_INTRET;
102 if (useCandidates != RBM_NONE)
104 tree->gtOp.gtOp1->gtLsraInfo.setSrcCandidates(l, useCandidates);
109 void Lowering::TreeNodeInfoInitLclHeap(GenTree* tree)
111 ContainCheckLclHeap(tree->AsOp());
113 TreeNodeInfo* info = &(tree->gtLsraInfo);
114 LinearScan* l = m_lsra;
115 Compiler* compiler = comp;
119 // Need a variable number of temp regs (see genLclHeap() in codegenarm.cpp):
120 // Here '-' means don't care.
122 // Size? Init Memory? # temp regs
124 // const and <=4 str instr - hasPspSym ? 1 : 0
125 // const and <PageSize No hasPspSym ? 1 : 0
126 // >4 ptr words Yes hasPspSym ? 2 : 1
127 // Non-const Yes hasPspSym ? 2 : 1
128 // Non-const No hasPspSym ? 2 : 1
131 #if FEATURE_EH_FUNCLETS
132 hasPspSym = (compiler->lvaPSPSym != BAD_VAR_NUM);
137 GenTreePtr size = tree->gtOp.gtOp1;
138 if (size->IsCnsIntOrI())
140 assert(size->isContained());
143 size_t sizeVal = size->gtIntCon.gtIconVal;
146 info->internalIntCount = 0;
150 sizeVal = AlignUp(sizeVal, STACK_ALIGN);
151 size_t cntStackAlignedWidthItems = (sizeVal >> STACK_ALIGN_SHIFT);
153 // For small allocations up to 4 store instructions
154 if (cntStackAlignedWidthItems <= 4)
156 info->internalIntCount = 0;
158 else if (!compiler->info.compInitMem)
160 // No need to initialize allocated stack space.
161 if (sizeVal < compiler->eeGetPageSize())
163 info->internalIntCount = 0;
167 info->internalIntCount = 1;
172 info->internalIntCount = 1;
177 info->internalIntCount++;
183 // target (regCnt) + tmp + [psp]
185 info->internalIntCount = hasPspSym ? 2 : 1;
188 // If we are needed in temporary registers we should be sure that
189 // it's different from target (regCnt)
190 if (info->internalIntCount > 0)
192 info->isInternalRegDelayFree = true;
196 //------------------------------------------------------------------------
197 // TreeNodeInfoInit: Set the register requirements for RA.
200 // Takes care of annotating the register requirements
201 // for every TreeNodeInfo struct that maps to each tree node.
204 // LSRA has been initialized and there is a TreeNodeInfo node
205 // already allocated and initialized for every tree in the IR.
208 // Every TreeNodeInfo instance has the right annotations on register
209 // requirements needed by LSRA to build the Interval Table (source,
210 // destination and internal [temp] register counts).
212 void Lowering::TreeNodeInfoInit(GenTree* tree)
214 LinearScan* l = m_lsra;
215 Compiler* compiler = comp;
217 unsigned kind = tree->OperKind();
218 TreeNodeInfo* info = &(tree->gtLsraInfo);
219 RegisterType registerType = TypeGet(tree);
221 JITDUMP("TreeNodeInfoInit for: ");
224 switch (tree->OperGet())
229 case GT_STORE_LCL_FLD:
230 case GT_STORE_LCL_VAR:
231 TreeNodeInfoInitStoreLoc(tree->AsLclVarCommon());
235 // A GT_NOP is either a passthrough (if it is void, or if it has
236 // a child), but must be considered to produce a dummy value if it
237 // has a type but no child
239 if (tree->TypeGet() != TYP_VOID && tree->gtOp.gtOp1 == nullptr)
251 // TODO-ARM: Implement other type of intrinsics (round, sqrt and etc.)
252 // Both operand and its result must be of the same floating point type.
253 op1 = tree->gtOp.gtOp1;
254 assert(varTypeIsFloating(op1));
255 assert(op1->TypeGet() == tree->TypeGet());
257 switch (tree->gtIntrinsic.gtIntrinsicId)
259 case CORINFO_INTRINSIC_Abs:
260 case CORINFO_INTRINSIC_Sqrt:
265 NYI_ARM("Lowering::TreeNodeInfoInit for GT_INTRINSIC");
273 ContainCheckCast(tree->AsCast());
277 // Non-overflow casts to/from float/double are done using SSE2 instructions
278 // and that allow the source operand to be either a reg or memop. Given the
279 // fact that casts from small int to float/double are done as two-level casts,
280 // the source operand is always guaranteed to be of size 4 or 8 bytes.
281 var_types castToType = tree->CastToType();
282 GenTreePtr castOp = tree->gtCast.CastOp();
283 var_types castOpType = castOp->TypeGet();
284 if (tree->gtFlags & GTF_UNSIGNED)
286 castOpType = genUnsignedType(castOpType);
289 if (!tree->gtOverflow() && (varTypeIsFloating(castToType) || varTypeIsFloating(castOpType)))
291 // If converting to float/double, the operand must be 4 or 8 byte in size.
292 if (varTypeIsFloating(castToType))
294 unsigned opSize = genTypeSize(castOpType);
295 assert(opSize == 4 || opSize == 8);
300 if (varTypeIsLong(castOpType))
302 assert((castOp->OperGet() == GT_LONG) && castOp->isContained());
306 // FloatToIntCast needs a temporary register
307 if (varTypeIsFloating(castOpType) && varTypeIsIntOrI(tree))
309 info->setInternalCandidates(m_lsra, RBM_ALLFLOAT);
310 info->internalFloatCount = 1;
311 info->isInternalRegDelayFree = true;
316 // Get information about the cast.
317 getCastDescription(tree, &castInfo);
319 if (castInfo.requiresOverflowCheck)
321 var_types srcType = castOp->TypeGet();
322 emitAttr cmpSize = EA_ATTR(genTypeSize(srcType));
324 // If we cannot store data in an immediate for instructions,
325 // then we will need to reserve a temporary register.
327 if (!castInfo.signCheckOnly) // In case of only sign check, temp regs are not needeed.
329 if (castInfo.unsignedSource || castInfo.unsignedDest)
332 bool canStoreTypeMask = emitter::emitIns_valid_imm_for_alu(castInfo.typeMask);
333 if (!canStoreTypeMask)
335 info->internalIntCount = 1;
340 // For comparing against the max or min value
341 bool canStoreMaxValue =
342 emitter::emitIns_valid_imm_for_cmp(castInfo.typeMax, INS_FLAGS_DONT_CARE);
343 bool canStoreMinValue =
344 emitter::emitIns_valid_imm_for_cmp(castInfo.typeMin, INS_FLAGS_DONT_CARE);
346 if (!canStoreMaxValue || !canStoreMinValue)
348 info->internalIntCount = 1;
359 l->clearDstCount(tree->gtOp.gtOp1);
368 // This should never occur since switch nodes must not be visible at this
371 info->dstCount = 0; // To avoid getting uninit errors.
372 noway_assert(!"Switch must be lowered at this point");
380 case GT_SWITCH_TABLE:
388 noway_assert(!"We should never hit any assignment operator in lowering");
399 if (varTypeIsFloating(tree->TypeGet()))
401 // overflow operations aren't supported on float/double types.
402 assert(!tree->gtOverflow());
404 // No implicit conversions at this stage as the expectation is that
405 // everything is made explicit by adding casts.
406 assert(tree->gtOp.gtOp1->TypeGet() == tree->gtOp.gtOp2->TypeGet());
419 ContainCheckBinary(tree->AsOp());
420 info->srcCount = tree->gtOp.gtOp2->isContained() ? 1 : 2;
425 // this just turns into a compare of its child with an int
426 // + a conditional call
432 if (tree->gtOverflow())
434 // Need a register different from target reg to check for overflow.
435 info->internalIntCount = 1;
436 info->isInternalRegDelayFree = true;
465 if (tree->IsUnusedValue())
467 // An unused GT_LONG node needs to consume its sources.
482 if (tree->TypeGet() == TYP_FLOAT)
484 // An int register for float constant
485 info->internalIntCount = 1;
490 assert(tree->TypeGet() == TYP_DOUBLE);
492 // Two int registers for double constant
493 info->internalIntCount = 2;
498 TreeNodeInfoInitReturn(tree);
502 if (tree->TypeGet() == TYP_VOID)
509 assert(tree->TypeGet() == TYP_INT);
514 info->setSrcCandidates(l, RBM_INTRET);
515 tree->gtOp.gtOp1->gtLsraInfo.setSrcCandidates(l, RBM_INTRET);
519 case GT_ARR_BOUNDS_CHECK:
522 #endif // FEATURE_SIMD
524 // Consumes arrLen & index - has no result
531 // These must have been lowered to GT_ARR_INDEX
532 noway_assert(!"We should never see a GT_ARR_ELEM in lowering");
540 info->internalIntCount = 1;
541 info->isInternalRegDelayFree = true;
543 // For GT_ARR_INDEX, the lifetime of the arrObj must be extended because it is actually used multiple
544 // times while the result is being computed.
545 tree->AsArrIndex()->ArrObj()->gtLsraInfo.isDelayFree = true;
546 info->hasDelayFreeSrc = true;
550 ContainCheckArrOffset(tree->AsArrOffs());
551 // This consumes the offset, if any, the arrObj and the effective index,
552 // and produces the flattened offset for this dimension.
555 if (tree->gtArrOffs.gtOffset->isContained())
561 // Here we simply need an internal register, which must be different
562 // from any of the operand's registers, but may be the same as targetReg.
563 info->internalIntCount = 1;
570 GenTreeAddrMode* lea = tree->AsAddrMode();
571 unsigned offset = lea->gtOffset;
573 // This LEA is instantiating an address, so we set up the srcCount and dstCount here.
585 // An internal register may be needed too; the logic here should be in sync with the
586 // genLeaInstruction()'s requirements for a such register.
587 if (lea->HasBase() && lea->HasIndex())
591 // We need a register when we have all three: base reg, index reg and a non-zero offset.
592 info->internalIntCount = 1;
595 else if (lea->HasBase())
597 if (!emitter::emitIns_valid_imm_for_add(offset, INS_FLAGS_DONT_CARE))
599 // We need a register when we have an offset that is too large to encode in the add instruction.
600 info->internalIntCount = 1;
622 TreeNodeInfoInitShiftRotate(tree);
632 TreeNodeInfoInitCmp(tree);
638 info->internalIntCount = 1;
642 TreeNodeInfoInitCall(tree->AsCall());
647 case GT_STORE_DYN_BLK:
648 LowerBlockStore(tree->AsBlk());
649 TreeNodeInfoInitBlockStore(tree->AsBlk());
653 // Always a passthrough of its child's value.
659 TreeNodeInfoInitLclHeap(tree);
665 GenTree* src = tree->gtOp.gtOp2;
667 if (compiler->codeGen->gcInfo.gcIsWriteBarrierAsgNode(tree))
669 TreeNodeInfoInitGCWriteBarrier(tree);
673 TreeNodeInfoInitIndir(tree->AsIndir());
674 // No contained source on ARM.
675 assert(!src->isContained());
683 info->isLocalDefUse = true;
684 // null check is an indirection on an addr
685 TreeNodeInfoInitIndir(tree->AsIndir());
691 TreeNodeInfoInitIndir(tree->AsIndir());
697 info->setDstCandidates(l, RBM_EXCEPTION_OBJECT);
702 // GT_CLS_VAR, by the time we reach the backend, must always
704 // It will produce a result of the type of the
705 // node, and use an internal register for the address.
708 assert((tree->gtFlags & (GTF_VAR_DEF | GTF_VAR_USEASG)) == 0);
709 info->internalIntCount = 1;
716 // This case currently only occurs for double types that are passed as TYP_LONG;
717 // actual long types would have been decomposed by now.
718 if (tree->TypeGet() == TYP_LONG)
727 // This case currently only occurs for double types that are passed as TYP_LONG;
728 // actual long types would have been decomposed by now.
729 if (tree->TypeGet() == TYP_LONG)
738 info->dstCount = info->srcCount;
744 _snprintf_s(message, _countof(message), _TRUNCATE, "NYI: Unimplemented node type %s",
745 GenTree::OpName(tree->OperGet()));
748 NYI_ARM("TreeNodeInfoInit default case");
751 case GT_LCL_FLD_ADDR:
753 case GT_LCL_VAR_ADDR:
755 case GT_CLS_VAR_ADDR:
760 case GT_PINVOKE_PROLOG:
763 case GT_MEMORYBARRIER:
765 case GT_PUTARG_SPLIT:
766 info->dstCount = tree->IsValue() ? 1 : 0;
767 if (kind & (GTK_CONST | GTK_LEAF))
771 else if (kind & (GTK_SMPOP))
773 if (tree->gtGetOp2IfPresent() != nullptr)
787 } // end switch (tree->OperGet())
789 // We need to be sure that we've set info->srcCount and info->dstCount appropriately
790 assert((info->dstCount < 2) || tree->IsMultiRegNode());
793 #endif // _TARGET_ARM_
795 #endif // !LEGACY_BACKEND