1 // Licensed to the .NET Foundation under one or more agreements.
2 // The .NET Foundation licenses this file to you under the MIT license.
3 // See the LICENSE file in the project root for more information.
4 /*****************************************************************************/
8 /*****************************************************************************/
10 #define BAD_CODE 0x0BADC0DE // better not match a real encoding!
12 /*****************************************************************************/
15 enum instruction : unsigned
17 #if defined(_TARGET_XARCH_)
18 #define INST0(id, nm, fp, um, rf, wf, mr ) INS_##id,
19 #define INST1(id, nm, fp, um, rf, wf, mr ) INS_##id,
20 #define INST2(id, nm, fp, um, rf, wf, mr, mi ) INS_##id,
21 #define INST3(id, nm, fp, um, rf, wf, mr, mi, rm ) INS_##id,
22 #define INST4(id, nm, fp, um, rf, wf, mr, mi, rm, a4 ) INS_##id,
23 #define INST5(id, nm, fp, um, rf, wf, mr, mi, rm, a4, rr) INS_##id,
26 #elif defined(_TARGET_ARM_)
27 #define INST1(id, nm, fp, ldst, fmt, e1 ) INS_##id,
28 #define INST2(id, nm, fp, ldst, fmt, e1, e2 ) INS_##id,
29 #define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) INS_##id,
30 #define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) INS_##id,
31 #define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) INS_##id,
32 #define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) INS_##id,
33 #define INST8(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8 ) INS_##id,
34 #define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) INS_##id,
36 #include "x86_instrs.h"
38 #elif defined(_TARGET_ARM64_)
39 #define INST1(id, nm, fp, ldst, fmt, e1 ) INS_##id,
40 #define INST2(id, nm, fp, ldst, fmt, e1, e2 ) INS_##id,
41 #define INST3(id, nm, fp, ldst, fmt, e1, e2, e3 ) INS_##id,
42 #define INST4(id, nm, fp, ldst, fmt, e1, e2, e3, e4 ) INS_##id,
43 #define INST5(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5 ) INS_##id,
44 #define INST6(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6 ) INS_##id,
45 #define INST9(id, nm, fp, ldst, fmt, e1, e2, e3, e4, e5, e6, e7, e8, e9) INS_##id,
48 INS_lea, // Not a real instruction. It is used for load the address of stack locals
51 #error Unsupported target architecture
58 /*****************************************************************************/
67 /*****************************************************************************/
73 #define JMP_SMALL(en, rev, ins) EJ_##en,
79 /*****************************************************************************/
81 enum GCtype : unsigned
88 // TODO-Cleanup: Move 'insFlags' under _TARGET_ARM_
89 enum insFlags: unsigned
96 #if defined(_TARGET_ARM_)
97 enum insOpts: unsigned
100 INS_OPTS_LDST_PRE_DEC,
101 INS_OPTS_LDST_POST_INC,
109 #elif defined(_TARGET_ARM64_)
110 enum insOpts : unsigned
142 INS_OPTS_MSL, // Vector Immediate (shifting ones variant)
144 INS_OPTS_S_TO_4BYTE, // Single to INT32
145 INS_OPTS_D_TO_4BYTE, // Double to INT32
147 INS_OPTS_S_TO_8BYTE, // Single to INT64
148 INS_OPTS_D_TO_8BYTE, // Double to INT64
150 INS_OPTS_4BYTE_TO_S, // INT32 to Single
151 INS_OPTS_4BYTE_TO_D, // INT32 to Double
153 INS_OPTS_8BYTE_TO_S, // INT64 to Single
154 INS_OPTS_8BYTE_TO_D, // INT64 to Double
156 INS_OPTS_S_TO_D, // Single to Double
157 INS_OPTS_D_TO_S, // Double to Single
159 INS_OPTS_H_TO_S, // Half to Single
160 INS_OPTS_H_TO_D, // Half to Double
162 INS_OPTS_S_TO_H, // Single to Half
163 INS_OPTS_D_TO_H, // Double to Half
166 enum insCond : unsigned
187 enum insCflags : unsigned
210 enum insBarrier : unsigned
212 INS_BARRIER_OSHLD = 1,
213 INS_BARRIER_OSHST = 2,
216 INS_BARRIER_NSHLD = 5,
217 INS_BARRIER_NSHST = 6,
220 INS_BARRIER_ISHLD = 9,
221 INS_BARRIER_ISHST = 10,
222 INS_BARRIER_ISH = 11,
231 enum emitAttr : unsigned
240 EA_SIZE_MASK = 0x03F,
242 #ifdef _TARGET_64BIT_
243 EA_PTRSIZE = EA_8BYTE,
245 EA_PTRSIZE = EA_4BYTE,
248 EA_OFFSET_FLG = 0x040,
249 EA_OFFSET = EA_OFFSET_FLG | EA_PTRSIZE, /* size == 0 */
250 EA_GCREF_FLG = 0x080,
251 EA_GCREF = EA_GCREF_FLG | EA_PTRSIZE, /* size == -1 */
252 EA_BYREF_FLG = 0x100,
253 EA_BYREF = EA_BYREF_FLG | EA_PTRSIZE, /* size == -2 */
254 EA_DSP_RELOC_FLG = 0x200,
255 EA_CNS_RELOC_FLG = 0x400,
258 #define EA_ATTR(x) ((emitAttr)(x))
259 #define EA_SIZE(x) ((emitAttr)(((unsigned)(x)) & EA_SIZE_MASK))
260 #define EA_SIZE_IN_BYTES(x) ((UNATIVE_OFFSET)(EA_SIZE(x)))
261 #define EA_SET_SIZE(x, sz) ((emitAttr)((((unsigned)(x)) & ~EA_SIZE_MASK) | sz))
262 #define EA_SET_FLG(x, flg) ((emitAttr)(((unsigned)(x)) | flg))
263 #define EA_4BYTE_DSP_RELOC (EA_SET_FLG(EA_4BYTE, EA_DSP_RELOC_FLG))
264 #define EA_PTR_DSP_RELOC (EA_SET_FLG(EA_PTRSIZE, EA_DSP_RELOC_FLG))
265 #define EA_HANDLE_CNS_RELOC (EA_SET_FLG(EA_PTRSIZE, EA_CNS_RELOC_FLG))
266 #define EA_IS_OFFSET(x) ((((unsigned)(x)) & ((unsigned)EA_OFFSET_FLG)) != 0)
267 #define EA_IS_GCREF(x) ((((unsigned)(x)) & ((unsigned)EA_GCREF_FLG)) != 0)
268 #define EA_IS_BYREF(x) ((((unsigned)(x)) & ((unsigned)EA_BYREF_FLG)) != 0)
269 #define EA_IS_GCREF_OR_BYREF(x) ((((unsigned)(x)) & ((unsigned)(EA_BYREF_FLG | EA_GCREF_FLG))) != 0)
270 #define EA_IS_DSP_RELOC(x) ((((unsigned)(x)) & ((unsigned)EA_DSP_RELOC_FLG)) != 0)
271 #define EA_IS_CNS_RELOC(x) ((((unsigned)(x)) & ((unsigned)EA_CNS_RELOC_FLG)) != 0)
272 #define EA_IS_RELOC(x) (EA_IS_DSP_RELOC(x) || EA_IS_CNS_RELOC(x))
273 #define EA_TYPE(x) ((emitAttr)(((unsigned)(x)) & ~(EA_OFFSET_FLG | EA_DSP_RELOC_FLG | EA_CNS_RELOC_FLG)))
275 #define EmitSize(x) (EA_ATTR(genTypeSize(TypeGet(x))))
279 InstructionSet_ILLEGAL = 0,
280 #ifdef _TARGET_XARCH_
281 // Start linear order SIMD instruction sets
282 // These ISAs have strictly generation to generation order.
283 InstructionSet_SSE = 1,
284 InstructionSet_SSE2 = 2,
285 InstructionSet_SSE3 = 3,
286 InstructionSet_SSSE3 = 4,
287 InstructionSet_SSE41 = 5,
288 InstructionSet_SSE42 = 6,
289 InstructionSet_AVX = 7,
290 InstructionSet_AVX2 = 8,
291 // Reserve values <32 for future SIMD instruction sets (i.e., AVX512),
292 // End linear order SIMD instruction sets.
294 InstructionSet_AES = 32,
295 InstructionSet_BMI1 = 33,
296 InstructionSet_BMI2 = 34,
297 InstructionSet_FMA = 35,
298 InstructionSet_LZCNT = 36,
299 InstructionSet_PCLMULQDQ = 37,
300 InstructionSet_POPCNT = 38,
301 #elif defined(_TARGET_ARM_)
303 #elif defined(_TARGET_ARM64_)
304 InstructionSet_Base, // Base instructions available on all Arm64 platforms
305 InstructionSet_Aes, // ID_AA64ISAR0_EL1.AES is 1 or better
306 InstructionSet_Atomics, // ID_AA64ISAR0_EL1.Atomic is 2 or better
307 InstructionSet_Crc32, // ID_AA64ISAR0_EL1.CRC32 is 1 or better
308 InstructionSet_Dcpop, // ID_AA64ISAR1_EL1.DPB is 1 or better
309 InstructionSet_Dp, // ID_AA64ISAR0_EL1.DP is 1 or better
310 InstructionSet_Fcma, // ID_AA64ISAR1_EL1.FCMA is 1 or better
311 InstructionSet_Fp, // ID_AA64PFR0_EL1.FP is 0 or better
312 InstructionSet_Fp16, // ID_AA64PFR0_EL1.FP is 1 or better
313 InstructionSet_Jscvt, // ID_AA64ISAR1_EL1.JSCVT is 1 or better
314 InstructionSet_Lrcpc, // ID_AA64ISAR1_EL1.LRCPC is 1 or better
315 InstructionSet_Pmull, // ID_AA64ISAR0_EL1.AES is 2 or better
316 InstructionSet_Sha1, // ID_AA64ISAR0_EL1.SHA1 is 1 or better
317 InstructionSet_Sha256, // ID_AA64ISAR0_EL1.SHA2 is 1 or better
318 InstructionSet_Sha512, // ID_AA64ISAR0_EL1.SHA2 is 2 or better
319 InstructionSet_Sha3, // ID_AA64ISAR0_EL1.SHA3 is 1 or better
320 InstructionSet_Simd, // ID_AA64PFR0_EL1.AdvSIMD is 0 or better
321 InstructionSet_Simd_v81, // ID_AA64ISAR0_EL1.RDM is 1 or better
322 InstructionSet_Simd_fp16, // ID_AA64PFR0_EL1.AdvSIMD is 1 or better
323 InstructionSet_Sm3, // ID_AA64ISAR0_EL1.SM3 is 1 or better
324 InstructionSet_Sm4, // ID_AA64ISAR0_EL1.SM4 is 1 or better
325 InstructionSet_Sve, // ID_AA64PFR0_EL1.SVE is 1 or better
327 InstructionSet_NONE // No instruction set is available indicating an invalid value
331 /*****************************************************************************/
333 /*****************************************************************************/