1 // Licensed to the .NET Foundation under one or more agreements.
2 // The .NET Foundation licenses this file to you under the MIT license.
3 // See the LICENSE file in the project root for more information.
5 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
6 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
8 XX ARM/ARM64 Code Generator Common Code XX
10 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
11 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
18 #ifndef LEGACY_BACKEND // This file is ONLY used for the RyuJIT backend that uses the linear scan register allocator
20 #ifdef _TARGET_ARMARCH_ // This file is ONLY used for ARM and ARM64 architectures
27 //------------------------------------------------------------------------
28 // genCodeForTreeNode Generate code for a single node in the tree.
31 // All operands have been evaluated.
33 void CodeGen::genCodeForTreeNode(GenTreePtr treeNode)
35 regNumber targetReg = treeNode->gtRegNum;
36 var_types targetType = treeNode->TypeGet();
37 emitter* emit = getEmitter();
40 // Validate that all the operands for the current node are consumed in order.
41 // This is important because LSRA ensures that any necessary copies will be
43 lastConsumedNode = nullptr;
44 if (compiler->verbose)
46 unsigned seqNum = treeNode->gtSeqNum; // Useful for setting a conditional break in Visual Studio
47 compiler->gtDispLIRNode(treeNode, "Generating: ");
51 #ifdef _TARGET_ARM64_ // TODO-ARM: is this applicable to ARM32?
52 // Is this a node whose value is already in a register? LSRA denotes this by
53 // setting the GTF_REUSE_REG_VAL flag.
54 if (treeNode->IsReuseRegVal())
56 // For now, this is only used for constant nodes.
57 assert((treeNode->OperGet() == GT_CNS_INT) || (treeNode->OperGet() == GT_CNS_DBL));
58 JITDUMP(" TreeNode is marked ReuseReg\n");
61 #endif // _TARGET_ARM64_
63 // contained nodes are part of their parents for codegen purposes
64 // ex : immediates, most LEAs
65 if (treeNode->isContained())
70 switch (treeNode->gtOper)
75 getEmitter()->emitDisableGC();
79 // We should be seeing this only if profiler hook is needed
80 noway_assert(compiler->compIsProfilerHookNeeded());
82 #ifdef PROFILING_SUPPORTED
83 // Right now this node is used only for tail calls. In future if
84 // we intend to use it for Enter or Leave hooks, add a data member
85 // to this node indicating the kind of profiler hook. For example,
86 // helper number can be used.
87 genProfilingLeaveCallback(CORINFO_HELP_PROF_FCN_TAILCALL);
88 #endif // PROFILING_SUPPORTED
91 #endif // _TARGET_ARM64_
99 genSetRegToConst(targetReg, targetType, treeNode);
100 genProduceReg(treeNode);
105 genCodeForNegNot(treeNode);
112 genCodeForDivMod(treeNode->AsOp());
118 assert(varTypeIsIntegralOrI(treeNode));
122 #if !defined(_TARGET_64BIT_)
127 #endif // !defined(_TARGET_64BIT_)
132 genConsumeOperands(treeNode->AsOp());
133 genCodeForBinary(treeNode);
139 // case GT_ROL: // No ROL instruction on ARM; it has been lowered to ROR.
141 genCodeForShift(treeNode);
144 #if !defined(_TARGET_64BIT_)
148 genCodeForShiftLong(treeNode);
151 #endif // !defined(_TARGET_64BIT_)
154 genCodeForCast(treeNode->AsOp());
157 case GT_LCL_FLD_ADDR:
158 case GT_LCL_VAR_ADDR:
159 genCodeForLclAddr(treeNode);
163 genCodeForLclFld(treeNode->AsLclFld());
167 genCodeForLclVar(treeNode->AsLclVar());
170 case GT_STORE_LCL_FLD:
171 genCodeForStoreLclFld(treeNode->AsLclFld());
174 case GT_STORE_LCL_VAR:
175 genCodeForStoreLclVar(treeNode->AsLclVar());
184 // If we are here, it is the case where there is an LEA that cannot be folded into a parent instruction.
185 genLeaInstruction(treeNode->AsAddrMode());
189 genCodeForIndir(treeNode->AsIndir());
194 genCodeForMulLong(treeNode->AsMultiRegOp());
196 #endif // _TARGET_ARM_
198 #ifdef _TARGET_ARM64_
201 genCodeForMulHi(treeNode->AsOp());
205 genCodeForSwap(treeNode->AsOp());
207 #endif // _TARGET_ARM64_
210 genJmpMethod(treeNode);
214 genCkfinite(treeNode);
218 genIntrinsic(treeNode);
223 genSIMDIntrinsic(treeNode->AsSIMD());
225 #endif // FEATURE_SIMD
234 genCodeForCompare(treeNode->AsOp());
238 genCodeForJumpTrue(treeNode);
244 genCodeForJcc(treeNode->AsCC());
248 genCodeForSetcc(treeNode->AsCC());
251 #endif // _TARGET_ARM_
254 genCodeForReturnTrap(treeNode->AsOp());
258 genCodeForStoreInd(treeNode->AsStoreInd());
262 // This is handled at the time we call genConsumeReg() on the GT_COPY
272 genPutArgStk(treeNode->AsPutArgStk());
276 genPutArgReg(treeNode->AsOp());
280 case GT_PUTARG_SPLIT:
281 genPutArgSplit(treeNode->AsPutArgSplit());
286 genCallInstruction(treeNode->AsCall());
292 genLockedInstructions(treeNode->AsOp());
295 case GT_MEMORYBARRIER:
296 instGen_MemoryBarrier();
304 // do nothing - reload is just a marker.
305 // The parent node will call genConsumeReg on this which will trigger the unspill of this node's child
306 // into the register specified in this node.
316 case GT_ARR_BOUNDS_CHECK:
319 #endif // FEATURE_SIMD
320 genRangeCheck(treeNode);
324 genCodeForPhysReg(treeNode->AsPhysReg());
328 genCodeForNullCheck(treeNode->AsOp());
333 noway_assert(handlerGetsXcptnObj(compiler->compCurBB->bbCatchTyp));
335 /* Catch arguments get passed in a register. genCodeForBBlist()
336 would have marked it as holding a GC object, but not used. */
338 noway_assert(gcInfo.gcRegGCrefSetCur & RBM_EXCEPTION_OBJECT);
339 genConsumeReg(treeNode);
342 case GT_PINVOKE_PROLOG:
343 noway_assert(((gcInfo.gcRegGCrefSetCur | gcInfo.gcRegByrefSetCur) & ~fullIntArgRegMask()) == 0);
345 // the runtime side requires the codegen here to be consistent
346 emit->emitDisableRandomNops();
350 genPendingCallLabel = genCreateTempLabel();
351 treeNode->gtLabel.gtLabBB = genPendingCallLabel;
352 emit->emitIns_R_L(INS_adr, EA_PTRSIZE, genPendingCallLabel, targetReg);
356 case GT_STORE_DYN_BLK:
358 genCodeForStoreBlk(treeNode->AsBlk());
362 genJumpTable(treeNode);
365 case GT_SWITCH_TABLE:
366 genTableBasedSwitch(treeNode);
370 genCodeForArrIndex(treeNode->AsArrIndex());
374 genCodeForArrOffset(treeNode->AsArrOffs());
379 case GT_CLS_VAR_ADDR:
380 emit->emitIns_R_C(INS_lea, EA_PTRSIZE, targetReg, treeNode->gtClsVar.gtClsVarHnd, 0);
381 genProduceReg(treeNode);
385 assert(treeNode->isUsedFromReg());
386 genConsumeRegs(treeNode);
389 #endif // _TARGET_ARM_
392 // Do nothing; these nodes are simply markers for debug info.
399 _snprintf_s(message, _countof(message), _TRUNCATE, "NYI: Unimplemented node type %s",
400 GenTree::OpName(treeNode->OperGet()));
403 NYI("unimplemented node");
410 //------------------------------------------------------------------------
411 // genSetRegToIcon: Generate code that will set the given register to the integer constant.
413 void CodeGen::genSetRegToIcon(regNumber reg, ssize_t val, var_types type, insFlags flags)
415 // Reg cannot be a FP reg
416 assert(!genIsValidFloatReg(reg));
418 // The only TYP_REF constant that can come this path is a managed 'null' since it is not
419 // relocatable. Other ref type constants (e.g. string objects) go through a different
421 noway_assert(type != TYP_REF || val == 0);
423 instGen_Set_Reg_To_Imm(emitActualTypeSize(type), reg, val, flags);
426 //---------------------------------------------------------------------
427 // genIntrinsic - generate code for a given intrinsic
430 // treeNode - the GT_INTRINSIC node
435 void CodeGen::genIntrinsic(GenTreePtr treeNode)
437 assert(treeNode->OperIs(GT_INTRINSIC));
439 // Both operand and its result must be of the same floating point type.
440 GenTreePtr srcNode = treeNode->gtOp.gtOp1;
441 assert(varTypeIsFloating(srcNode));
442 assert(srcNode->TypeGet() == treeNode->TypeGet());
444 // Right now only Abs/Round/Sqrt are treated as math intrinsics.
446 switch (treeNode->gtIntrinsic.gtIntrinsicId)
448 case CORINFO_INTRINSIC_Abs:
449 genConsumeOperands(treeNode->AsOp());
450 getEmitter()->emitInsBinary(INS_ABS, emitTypeSize(treeNode), treeNode, srcNode);
453 case CORINFO_INTRINSIC_Round:
454 NYI_ARM("genIntrinsic for round - not implemented yet");
455 genConsumeOperands(treeNode->AsOp());
456 getEmitter()->emitInsBinary(INS_ROUND, emitTypeSize(treeNode), treeNode, srcNode);
459 case CORINFO_INTRINSIC_Sqrt:
460 genConsumeOperands(treeNode->AsOp());
461 getEmitter()->emitInsBinary(INS_SQRT, emitTypeSize(treeNode), treeNode, srcNode);
465 assert(!"genIntrinsic: Unsupported intrinsic");
469 genProduceReg(treeNode);
472 //---------------------------------------------------------------------
473 // genPutArgStk - generate code for a GT_PUTARG_STK node
476 // treeNode - the GT_PUTARG_STK node
481 void CodeGen::genPutArgStk(GenTreePutArgStk* treeNode)
483 assert(treeNode->OperIs(GT_PUTARG_STK));
484 var_types targetType = treeNode->TypeGet();
485 GenTreePtr source = treeNode->gtOp1;
486 emitter* emit = getEmitter();
488 // This is the varNum for our store operations,
489 // typically this is the varNum for the Outgoing arg space
490 // When we are generating a tail call it will be the varNum for arg0
491 unsigned varNumOut = (unsigned)-1;
492 unsigned argOffsetMax = (unsigned)-1; // Records the maximum size of this area for assert checks
494 // Get argument offset to use with 'varNumOut'
495 // Here we cross check that argument offset hasn't changed from lowering to codegen since
496 // we are storing arg slot number in GT_PUTARG_STK node in lowering phase.
497 unsigned argOffsetOut = treeNode->gtSlotNum * TARGET_POINTER_SIZE;
500 fgArgTabEntryPtr curArgTabEntry = compiler->gtArgEntryByNode(treeNode->gtCall, treeNode);
501 assert(curArgTabEntry);
502 assert(argOffsetOut == (curArgTabEntry->slotNum * TARGET_POINTER_SIZE));
505 // Whether to setup stk arg in incoming or out-going arg area?
506 // Fast tail calls implemented as epilog+jmp = stk arg is setup in incoming arg area.
507 // All other calls - stk arg is setup in out-going arg area.
508 if (treeNode->putInIncomingArgArea())
510 NYI_ARM("genPutArgStk: fast tail call");
512 #ifdef _TARGET_ARM64_
513 varNumOut = getFirstArgWithStackSlot();
514 argOffsetMax = compiler->compArgSize;
515 #if FEATURE_FASTTAILCALL
516 // This must be a fast tail call.
517 assert(treeNode->gtCall->IsFastTailCall());
519 // Since it is a fast tail call, the existence of first incoming arg is guaranteed
520 // because fast tail call requires that in-coming arg area of caller is >= out-going
521 // arg area required for tail call.
522 LclVarDsc* varDsc = &(compiler->lvaTable[varNumOut]);
523 assert(varDsc != nullptr);
524 #endif // FEATURE_FASTTAILCALL
525 #endif // _TARGET_ARM64_
529 varNumOut = compiler->lvaOutgoingArgSpaceVar;
530 argOffsetMax = compiler->lvaOutgoingArgSpaceSize;
533 bool isStruct = (targetType == TYP_STRUCT) || (source->OperGet() == GT_FIELD_LIST);
535 if (!isStruct) // a normal non-Struct argument
537 instruction storeIns = ins_Store(targetType);
538 emitAttr storeAttr = emitTypeSize(targetType);
540 // If it is contained then source must be the integer constant zero
541 if (source->isContained())
543 assert(source->OperGet() == GT_CNS_INT);
544 assert(source->AsIntConCommon()->IconValue() == 0);
545 NYI_ARM("genPutArgStk: contained zero source");
547 #ifdef _TARGET_ARM64_
548 emit->emitIns_S_R(storeIns, storeAttr, REG_ZR, varNumOut, argOffsetOut);
549 #endif // _TARGET_ARM64_
553 genConsumeReg(source);
554 emit->emitIns_S_R(storeIns, storeAttr, source->gtRegNum, varNumOut, argOffsetOut);
555 if (compiler->opts.compUseSoftFP && targetType == TYP_LONG)
557 // This case currently only occurs for double types that are passed as TYP_LONG;
558 // actual long types would have been decomposed by now.
559 assert(source->IsCopyOrReload());
560 regNumber otherReg = (regNumber)source->AsCopyOrReload()->GetRegNumByIdx(1);
561 assert(otherReg != REG_NA);
562 argOffsetOut += EA_4BYTE;
563 emit->emitIns_S_R(storeIns, storeAttr, otherReg, varNumOut, argOffsetOut);
566 argOffsetOut += EA_SIZE_IN_BYTES(storeAttr);
567 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
569 else // We have some kind of a struct argument
571 assert(source->isContained()); // We expect that this node was marked as contained in Lower
573 if (source->OperGet() == GT_FIELD_LIST)
575 // Deal with the multi register passed struct args.
576 GenTreeFieldList* fieldListPtr = source->AsFieldList();
578 // Evaluate each of the GT_FIELD_LIST items into their register
579 // and store their register into the outgoing argument area
580 for (; fieldListPtr != nullptr; fieldListPtr = fieldListPtr->Rest())
582 GenTreePtr nextArgNode = fieldListPtr->gtOp.gtOp1;
583 genConsumeReg(nextArgNode);
585 regNumber reg = nextArgNode->gtRegNum;
586 var_types type = nextArgNode->TypeGet();
587 emitAttr attr = emitTypeSize(type);
589 // Emit store instructions to store the registers produced by the GT_FIELD_LIST into the outgoing
591 emit->emitIns_S_R(ins_Store(type), attr, reg, varNumOut, argOffsetOut);
592 argOffsetOut += EA_SIZE_IN_BYTES(attr);
593 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
596 else // We must have a GT_OBJ or a GT_LCL_VAR
598 noway_assert((source->OperGet() == GT_LCL_VAR) || (source->OperGet() == GT_OBJ));
600 var_types targetType = source->TypeGet();
601 noway_assert(varTypeIsStruct(targetType));
603 // We will copy this struct to the stack, possibly using a ldp/ldr instruction
605 // Setup loReg (and hiReg) from the internal registers that we reserved in lower.
607 regNumber loReg = treeNode->ExtractTempReg();
608 #ifdef _TARGET_ARM64_
609 regNumber hiReg = treeNode->GetSingleTempReg();
610 #endif // _TARGET_ARM64_
611 regNumber addrReg = REG_NA;
613 GenTreeLclVarCommon* varNode = nullptr;
614 GenTreePtr addrNode = nullptr;
616 if (source->OperGet() == GT_LCL_VAR)
618 varNode = source->AsLclVarCommon();
620 else // we must have a GT_OBJ
622 assert(source->OperGet() == GT_OBJ);
624 addrNode = source->gtOp.gtOp1;
626 // addrNode can either be a GT_LCL_VAR_ADDR or an address expression
628 if (addrNode->OperGet() == GT_LCL_VAR_ADDR)
630 // We have a GT_OBJ(GT_LCL_VAR_ADDR)
632 // We will treat this case the same as above
633 // (i.e if we just had this GT_LCL_VAR directly as the source)
634 // so update 'source' to point this GT_LCL_VAR_ADDR node
635 // and continue to the codegen for the LCL_VAR node below
637 varNode = addrNode->AsLclVarCommon();
642 // Either varNode or addrNOde must have been setup above,
643 // the xor ensures that only one of the two is setup, not both
644 assert((varNode != nullptr) ^ (addrNode != nullptr));
646 BYTE gcPtrArray[MAX_ARG_REG_COUNT] = {}; // TYPE_GC_NONE = 0
647 BYTE* gcPtrs = gcPtrArray;
649 unsigned gcPtrCount; // The count of GC pointers in the struct
653 // This is the varNum for our load operations,
654 // only used when we have a multireg struct with a LclVar source
655 unsigned varNumInp = BAD_VAR_NUM;
658 // On ARM32, size of reference map can be larger than MAX_ARG_REG_COUNT
659 gcPtrs = treeNode->gtGcPtrs;
660 gcPtrCount = treeNode->gtNumberReferenceSlots;
662 // Setup the structSize, isHFa, and gcPtrCount
663 if (varNode != nullptr)
665 varNumInp = varNode->gtLclNum;
666 assert(varNumInp < compiler->lvaCount);
667 LclVarDsc* varDsc = &compiler->lvaTable[varNumInp];
669 assert(varDsc->lvType == TYP_STRUCT);
671 if (varDsc->lvPromoted)
673 NYI_ARM("CodeGen::genPutArgStk - promoted struct");
676 #endif // _TARGET_ARM_
677 // This struct also must live in the stack frame
678 // And it can't live in a register (SIMD)
679 assert(varDsc->lvOnFrame && !varDsc->lvRegister);
681 structSize = varDsc->lvSize(); // This yields the roundUp size, but that is fine
682 // as that is how much stack is allocated for this LclVar
683 isHfa = varDsc->lvIsHfa();
684 #ifdef _TARGET_ARM64_
685 gcPtrCount = varDsc->lvStructGcCount;
686 for (unsigned i = 0; i < gcPtrCount; ++i)
687 gcPtrs[i] = varDsc->lvGcLayout[i];
688 #endif // _TARGET_ARM_
690 else // addrNode is used
692 assert(addrNode != nullptr);
694 // Generate code to load the address that we need into a register
695 genConsumeAddress(addrNode);
696 addrReg = addrNode->gtRegNum;
698 #ifdef _TARGET_ARM64_
699 // If addrReg equal to loReg, swap(loReg, hiReg)
700 // This reduces code complexity by only supporting one addrReg overwrite case
701 if (loReg == addrReg)
706 #endif // _TARGET_ARM64_
708 CORINFO_CLASS_HANDLE objClass = source->gtObj.gtClass;
710 structSize = compiler->info.compCompHnd->getClassSize(objClass);
711 isHfa = compiler->IsHfa(objClass);
712 #ifdef _TARGET_ARM64_
713 gcPtrCount = compiler->info.compCompHnd->getClassGClayout(objClass, &gcPtrs[0]);
717 // If we have an HFA we can't have any GC pointers,
718 // if not then the max size for the the struct is 16 bytes
721 noway_assert(gcPtrCount == 0);
723 #ifdef _TARGET_ARM64_
726 noway_assert(structSize <= 2 * TARGET_POINTER_SIZE);
729 noway_assert(structSize <= MAX_PASS_MULTIREG_BYTES);
730 #endif // _TARGET_ARM64_
732 int remainingSize = structSize;
733 unsigned structOffset = 0;
734 unsigned nextIndex = 0;
736 #ifdef _TARGET_ARM64_
737 // For a >= 16-byte structSize we will generate a ldp and stp instruction each loop
739 // stp x2, x3, [sp, #16]
741 while (remainingSize >= 2 * TARGET_POINTER_SIZE)
743 var_types type0 = compiler->getJitGCType(gcPtrs[nextIndex + 0]);
744 var_types type1 = compiler->getJitGCType(gcPtrs[nextIndex + 1]);
746 if (varNode != nullptr)
748 // Load from our varNumImp source
749 emit->emitIns_R_R_S_S(INS_ldp, emitTypeSize(type0), emitTypeSize(type1), loReg, hiReg, varNumInp,
754 // check for case of destroying the addrRegister while we still need it
755 assert(loReg != addrReg);
756 noway_assert((remainingSize == 2 * TARGET_POINTER_SIZE) || (hiReg != addrReg));
758 // Load from our address expression source
759 emit->emitIns_R_R_R_I(INS_ldp, emitTypeSize(type0), loReg, hiReg, addrReg, structOffset,
760 INS_OPTS_NONE, emitTypeSize(type0));
763 // Emit stp instruction to store the two registers into the outgoing argument area
764 emit->emitIns_S_S_R_R(INS_stp, emitTypeSize(type0), emitTypeSize(type1), loReg, hiReg, varNumOut,
766 argOffsetOut += (2 * TARGET_POINTER_SIZE); // We stored 16-bytes of the struct
767 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
769 remainingSize -= (2 * TARGET_POINTER_SIZE); // We loaded 16-bytes of the struct
770 structOffset += (2 * TARGET_POINTER_SIZE);
773 #else // _TARGET_ARM_
774 // For a >= 4 byte structSize we will generate a ldr and str instruction each loop
777 while (remainingSize >= TARGET_POINTER_SIZE)
779 var_types type = compiler->getJitGCType(gcPtrs[nextIndex]);
781 if (varNode != nullptr)
783 // Load from our varNumImp source
784 emit->emitIns_R_S(INS_ldr, emitTypeSize(type), loReg, varNumInp, structOffset);
788 // check for case of destroying the addrRegister while we still need it
789 assert(loReg != addrReg || remainingSize == TARGET_POINTER_SIZE);
791 // Load from our address expression source
792 emit->emitIns_R_R_I(INS_ldr, emitTypeSize(type), loReg, addrReg, structOffset);
795 // Emit str instruction to store the register into the outgoing argument area
796 emit->emitIns_S_R(INS_str, emitTypeSize(type), loReg, varNumOut, argOffsetOut);
797 argOffsetOut += TARGET_POINTER_SIZE; // We stored 4-bytes of the struct
798 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
800 remainingSize -= TARGET_POINTER_SIZE; // We loaded 4-bytes of the struct
801 structOffset += TARGET_POINTER_SIZE;
804 #endif // _TARGET_ARM_
806 // For a 12-byte structSize we will we will generate two load instructions
812 while (remainingSize > 0)
814 if (remainingSize >= TARGET_POINTER_SIZE)
816 var_types nextType = compiler->getJitGCType(gcPtrs[nextIndex]);
817 emitAttr nextAttr = emitTypeSize(nextType);
818 remainingSize -= TARGET_POINTER_SIZE;
820 if (varNode != nullptr)
822 // Load from our varNumImp source
823 emit->emitIns_R_S(ins_Load(nextType), nextAttr, loReg, varNumInp, structOffset);
827 assert(loReg != addrReg);
829 // Load from our address expression source
830 emit->emitIns_R_R_I(ins_Load(nextType), nextAttr, loReg, addrReg, structOffset);
832 // Emit a store instruction to store the register into the outgoing argument area
833 emit->emitIns_S_R(ins_Store(nextType), nextAttr, loReg, varNumOut, argOffsetOut);
834 argOffsetOut += EA_SIZE_IN_BYTES(nextAttr);
835 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
837 structOffset += TARGET_POINTER_SIZE;
840 else // (remainingSize < TARGET_POINTER_SIZE)
842 int loadSize = remainingSize;
845 // We should never have to do a non-pointer sized load when we have a LclVar source
846 assert(varNode == nullptr);
848 // the left over size is smaller than a pointer and thus can never be a GC type
849 assert(varTypeIsGC(compiler->getJitGCType(gcPtrs[nextIndex])) == false);
851 var_types loadType = TYP_UINT;
854 loadType = TYP_UBYTE;
856 else if (loadSize == 2)
858 loadType = TYP_USHORT;
862 // Need to handle additional loadSize cases here
863 noway_assert(loadSize == 4);
866 instruction loadIns = ins_Load(loadType);
867 emitAttr loadAttr = emitAttr(loadSize);
869 assert(loReg != addrReg);
871 emit->emitIns_R_R_I(loadIns, loadAttr, loReg, addrReg, structOffset);
873 // Emit a store instruction to store the register into the outgoing argument area
874 emit->emitIns_S_R(ins_Store(loadType), loadAttr, loReg, varNumOut, argOffsetOut);
875 argOffsetOut += EA_SIZE_IN_BYTES(loadAttr);
876 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
883 //---------------------------------------------------------------------
884 // genPutArgReg - generate code for a GT_PUTARG_REG node
887 // tree - the GT_PUTARG_REG node
892 void CodeGen::genPutArgReg(GenTreeOp* tree)
894 assert(tree->OperIs(GT_PUTARG_REG));
896 var_types targetType = tree->TypeGet();
897 regNumber targetReg = tree->gtRegNum;
899 assert(targetType != TYP_STRUCT);
901 GenTree* op1 = tree->gtOp1;
904 // If child node is not already in the register we need, move it
905 if (targetReg != op1->gtRegNum)
907 inst_RV_RV(ins_Copy(targetType), targetReg, op1->gtRegNum, targetType);
914 //---------------------------------------------------------------------
915 // genPutArgSplit - generate code for a GT_PUTARG_SPLIT node
918 // tree - the GT_PUTARG_SPLIT node
923 void CodeGen::genPutArgSplit(GenTreePutArgSplit* treeNode)
925 assert(treeNode->OperIs(GT_PUTARG_SPLIT));
927 GenTreePtr source = treeNode->gtOp1;
928 emitter* emit = getEmitter();
929 unsigned varNumOut = compiler->lvaOutgoingArgSpaceVar;
930 unsigned argOffsetMax = compiler->lvaOutgoingArgSpaceSize;
931 unsigned argOffsetOut = treeNode->gtSlotNum * TARGET_POINTER_SIZE;
933 if (source->OperGet() == GT_FIELD_LIST)
935 GenTreeFieldList* fieldListPtr = source->AsFieldList();
937 // Evaluate each of the GT_FIELD_LIST items into their register
938 // and store their register into the outgoing argument area
939 for (unsigned idx = 0; fieldListPtr != nullptr; fieldListPtr = fieldListPtr->Rest(), idx++)
941 GenTreePtr nextArgNode = fieldListPtr->gtGetOp1();
942 regNumber fieldReg = nextArgNode->gtRegNum;
943 genConsumeReg(nextArgNode);
945 if (idx >= treeNode->gtNumRegs)
947 var_types type = nextArgNode->TypeGet();
948 emitAttr attr = emitTypeSize(type);
950 // Emit store instructions to store the registers produced by the GT_FIELD_LIST into the outgoing
952 emit->emitIns_S_R(ins_Store(type), attr, fieldReg, varNumOut, argOffsetOut);
953 argOffsetOut += EA_SIZE_IN_BYTES(attr);
954 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
958 var_types type = treeNode->GetRegType(idx);
959 regNumber argReg = treeNode->GetRegNumByIdx(idx);
961 // If child node is not already in the register we need, move it
962 if (argReg != fieldReg)
964 inst_RV_RV(ins_Copy(type), argReg, fieldReg, type);
971 var_types targetType = source->TypeGet();
972 assert(source->OperGet() == GT_OBJ);
973 assert(varTypeIsStruct(targetType));
975 regNumber baseReg = treeNode->ExtractTempReg();
976 regNumber addrReg = REG_NA;
978 GenTreeLclVarCommon* varNode = nullptr;
979 GenTreePtr addrNode = nullptr;
981 addrNode = source->gtOp.gtOp1;
983 // addrNode can either be a GT_LCL_VAR_ADDR or an address expression
985 if (addrNode->OperGet() == GT_LCL_VAR_ADDR)
987 // We have a GT_OBJ(GT_LCL_VAR_ADDR)
989 // We will treat this case the same as above
990 // (i.e if we just had this GT_LCL_VAR directly as the source)
991 // so update 'source' to point this GT_LCL_VAR_ADDR node
992 // and continue to the codegen for the LCL_VAR node below
994 varNode = addrNode->AsLclVarCommon();
998 // Either varNode or addrNOde must have been setup above,
999 // the xor ensures that only one of the two is setup, not both
1000 assert((varNode != nullptr) ^ (addrNode != nullptr));
1002 // Setup the structSize, isHFa, and gcPtrCount
1003 BYTE* gcPtrs = treeNode->gtGcPtrs;
1004 unsigned gcPtrCount = treeNode->gtNumberReferenceSlots; // The count of GC pointers in the struct
1005 int structSize = treeNode->getArgSize();
1007 // This is the varNum for our load operations,
1008 // only used when we have a struct with a LclVar source
1009 unsigned srcVarNum = BAD_VAR_NUM;
1011 if (varNode != nullptr)
1013 srcVarNum = varNode->gtLclNum;
1014 assert(srcVarNum < compiler->lvaCount);
1016 // handle promote situation
1017 LclVarDsc* varDsc = compiler->lvaTable + srcVarNum;
1018 if (varDsc->lvPromoted)
1020 NYI_ARM("CodeGen::genPutArgSplit - promoted struct");
1023 // We don't split HFA struct
1024 assert(!varDsc->lvIsHfa());
1026 else // addrNode is used
1028 assert(addrNode != nullptr);
1030 // Generate code to load the address that we need into a register
1031 genConsumeAddress(addrNode);
1032 addrReg = addrNode->gtRegNum;
1034 // If addrReg equal to baseReg, we use the last target register as alternative baseReg.
1035 // Because the candidate mask for the internal baseReg does not include any of the target register,
1036 // we can ensure that baseReg, addrReg, and the last target register are not all same.
1037 assert(baseReg != addrReg);
1039 // We don't split HFA struct
1040 assert(!compiler->IsHfa(source->gtObj.gtClass));
1043 // Put on stack first
1044 unsigned nextIndex = treeNode->gtNumRegs;
1045 unsigned structOffset = nextIndex * TARGET_POINTER_SIZE;
1046 int remainingSize = structSize - structOffset;
1048 // remainingSize is always multiple of TARGET_POINTER_SIZE
1049 assert(remainingSize % TARGET_POINTER_SIZE == 0);
1050 while (remainingSize > 0)
1052 var_types type = compiler->getJitGCType(gcPtrs[nextIndex]);
1054 if (varNode != nullptr)
1056 // Load from our varNumImp source
1057 emit->emitIns_R_S(INS_ldr, emitTypeSize(type), baseReg, srcVarNum, structOffset);
1061 // check for case of destroying the addrRegister while we still need it
1062 assert(baseReg != addrReg);
1064 // Load from our address expression source
1065 emit->emitIns_R_R_I(INS_ldr, emitTypeSize(type), baseReg, addrReg, structOffset);
1068 // Emit str instruction to store the register into the outgoing argument area
1069 emit->emitIns_S_R(INS_str, emitTypeSize(type), baseReg, varNumOut, argOffsetOut);
1070 argOffsetOut += TARGET_POINTER_SIZE; // We stored 4-bytes of the struct
1071 assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area
1072 remainingSize -= TARGET_POINTER_SIZE; // We loaded 4-bytes of the struct
1073 structOffset += TARGET_POINTER_SIZE;
1077 // We set up the registers in order, so that we assign the last target register `baseReg` is no longer in use,
1078 // in case we had to reuse the last target register for it.
1080 for (unsigned idx = 0; idx < treeNode->gtNumRegs; idx++)
1082 regNumber targetReg = treeNode->GetRegNumByIdx(idx);
1083 var_types type = treeNode->GetRegType(idx);
1085 if (varNode != nullptr)
1087 // Load from our varNumImp source
1088 emit->emitIns_R_S(INS_ldr, emitTypeSize(type), targetReg, srcVarNum, structOffset);
1092 // check for case of destroying the addrRegister while we still need it
1093 if (targetReg == addrReg && idx != treeNode->gtNumRegs - 1)
1095 assert(targetReg != baseReg);
1096 emit->emitIns_R_R(INS_mov, emitTypeSize(type), baseReg, addrReg);
1100 // Load from our address expression source
1101 emit->emitIns_R_R_I(INS_ldr, emitTypeSize(type), targetReg, addrReg, structOffset);
1103 structOffset += TARGET_POINTER_SIZE;
1106 genProduceReg(treeNode);
1108 #endif // _TARGET_ARM_
1110 //----------------------------------------------------------------------------------
1111 // genMultiRegCallStoreToLocal: store multi-reg return value of a call node to a local
1114 // treeNode - Gentree of GT_STORE_LCL_VAR
1120 // The child of store is a multi-reg call node.
1121 // genProduceReg() on treeNode is made by caller of this routine.
1123 void CodeGen::genMultiRegCallStoreToLocal(GenTreePtr treeNode)
1125 assert(treeNode->OperGet() == GT_STORE_LCL_VAR);
1127 #if defined(_TARGET_ARM_)
1128 // Longs are returned in two return registers on Arm32.
1129 // Structs are returned in four registers on ARM32 and HFAs.
1130 assert(varTypeIsLong(treeNode) || varTypeIsStruct(treeNode));
1131 #elif defined(_TARGET_ARM64_)
1132 // Structs of size >=9 and <=16 are returned in two return registers on ARM64 and HFAs.
1133 assert(varTypeIsStruct(treeNode));
1136 // Assumption: current implementation requires that a multi-reg
1137 // var in 'var = call' is flagged as lvIsMultiRegRet to prevent it from
1139 unsigned lclNum = treeNode->AsLclVarCommon()->gtLclNum;
1140 LclVarDsc* varDsc = &(compiler->lvaTable[lclNum]);
1141 noway_assert(varDsc->lvIsMultiRegRet);
1143 GenTree* op1 = treeNode->gtGetOp1();
1144 GenTree* actualOp1 = op1->gtSkipReloadOrCopy();
1145 GenTreeCall* call = actualOp1->AsCall();
1146 assert(call->HasMultiRegRetVal());
1148 genConsumeRegs(op1);
1150 ReturnTypeDesc* pRetTypeDesc = call->GetReturnTypeDesc();
1151 unsigned regCount = pRetTypeDesc->GetReturnRegCount();
1153 if (treeNode->gtRegNum != REG_NA)
1155 // Right now the only enregistrable multi-reg return types supported are SIMD types.
1156 assert(varTypeIsSIMD(treeNode));
1157 NYI("GT_STORE_LCL_VAR of a SIMD enregisterable struct");
1163 for (unsigned i = 0; i < regCount; ++i)
1165 var_types type = pRetTypeDesc->GetReturnRegType(i);
1166 regNumber reg = call->GetRegNumByIdx(i);
1167 if (op1->IsCopyOrReload())
1169 // GT_COPY/GT_RELOAD will have valid reg for those positions
1170 // that need to be copied or reloaded.
1171 regNumber reloadReg = op1->AsCopyOrReload()->GetRegNumByIdx(i);
1172 if (reloadReg != REG_NA)
1178 assert(reg != REG_NA);
1179 getEmitter()->emitIns_S_R(ins_Store(type), emitTypeSize(type), reg, lclNum, offset);
1180 offset += genTypeSize(type);
1183 varDsc->lvRegNum = REG_STK;
1187 //------------------------------------------------------------------------
1188 // genRangeCheck: generate code for GT_ARR_BOUNDS_CHECK node.
1190 void CodeGen::genRangeCheck(GenTreePtr oper)
1193 noway_assert(oper->OperGet() == GT_ARR_BOUNDS_CHECK || oper->OperGet() == GT_SIMD_CHK);
1194 #else // !FEATURE_SIMD
1195 noway_assert(oper->OperGet() == GT_ARR_BOUNDS_CHECK);
1196 #endif // !FEATURE_SIMD
1198 GenTreeBoundsChk* bndsChk = oper->AsBoundsChk();
1200 GenTreePtr arrLen = bndsChk->gtArrLen;
1201 GenTreePtr arrIndex = bndsChk->gtIndex;
1202 GenTreePtr arrRef = NULL;
1207 emitJumpKind jmpKind;
1209 genConsumeRegs(arrIndex);
1210 genConsumeRegs(arrLen);
1212 if (arrIndex->isContainedIntOrIImmed())
1214 // To encode using a cmp immediate, we place the
1215 // constant operand in the second position
1218 jmpKind = genJumpKindForOper(GT_LE, CK_UNSIGNED);
1224 jmpKind = genJumpKindForOper(GT_GE, CK_UNSIGNED);
1227 getEmitter()->emitInsBinary(INS_cmp, EA_4BYTE, src1, src2);
1228 genJumpToThrowHlpBlk(jmpKind, SCK_RNGCHK_FAIL, bndsChk->gtIndRngFailBB);
1231 //---------------------------------------------------------------------
1232 // genCodeForPhysReg - generate code for a GT_PHYSREG node
1235 // tree - the GT_PHYSREG node
1240 void CodeGen::genCodeForPhysReg(GenTreePhysReg* tree)
1242 assert(tree->OperIs(GT_PHYSREG));
1244 var_types targetType = tree->TypeGet();
1245 regNumber targetReg = tree->gtRegNum;
1247 if (targetReg != tree->gtSrcReg)
1249 inst_RV_RV(ins_Copy(targetType), targetReg, tree->gtSrcReg, targetType);
1250 genTransferRegGCState(targetReg, tree->gtSrcReg);
1253 genProduceReg(tree);
1256 //---------------------------------------------------------------------
1257 // genCodeForNullCheck - generate code for a GT_NULLCHECK node
1260 // tree - the GT_NULLCHECK node
1265 void CodeGen::genCodeForNullCheck(GenTreeOp* tree)
1267 assert(tree->OperIs(GT_NULLCHECK));
1268 assert(!tree->gtOp1->isContained());
1269 regNumber addrReg = genConsumeReg(tree->gtOp1);
1271 #ifdef _TARGET_ARM64_
1272 regNumber targetReg = REG_ZR;
1274 regNumber targetReg = tree->gtRegNum;
1277 getEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, targetReg, addrReg, 0);
1280 //------------------------------------------------------------------------
1281 // genOffsetOfMDArrayLowerBound: Returns the offset from the Array object to the
1282 // lower bound for the given dimension.
1285 // elemType - the element type of the array
1286 // rank - the rank of the array
1287 // dimension - the dimension for which the lower bound offset will be returned.
1291 // TODO-Cleanup: move to CodeGenCommon.cpp
1294 unsigned CodeGen::genOffsetOfMDArrayLowerBound(var_types elemType, unsigned rank, unsigned dimension)
1296 // Note that the lower bound and length fields of the Array object are always TYP_INT
1297 return compiler->eeGetArrayDataOffset(elemType) + genTypeSize(TYP_INT) * (dimension + rank);
1300 //------------------------------------------------------------------------
1301 // genOffsetOfMDArrayLength: Returns the offset from the Array object to the
1302 // size for the given dimension.
1305 // elemType - the element type of the array
1306 // rank - the rank of the array
1307 // dimension - the dimension for which the lower bound offset will be returned.
1311 // TODO-Cleanup: move to CodeGenCommon.cpp
1314 unsigned CodeGen::genOffsetOfMDArrayDimensionSize(var_types elemType, unsigned rank, unsigned dimension)
1316 // Note that the lower bound and length fields of the Array object are always TYP_INT
1317 return compiler->eeGetArrayDataOffset(elemType) + genTypeSize(TYP_INT) * dimension;
1320 //------------------------------------------------------------------------
1321 // genCodeForArrIndex: Generates code to bounds check the index for one dimension of an array reference,
1322 // producing the effective index by subtracting the lower bound.
1325 // arrIndex - the node for which we're generating code
1330 void CodeGen::genCodeForArrIndex(GenTreeArrIndex* arrIndex)
1332 emitter* emit = getEmitter();
1333 GenTreePtr arrObj = arrIndex->ArrObj();
1334 GenTreePtr indexNode = arrIndex->IndexExpr();
1335 regNumber arrReg = genConsumeReg(arrObj);
1336 regNumber indexReg = genConsumeReg(indexNode);
1337 regNumber tgtReg = arrIndex->gtRegNum;
1338 noway_assert(tgtReg != REG_NA);
1340 // We will use a temp register to load the lower bound and dimension size values.
1342 regNumber tmpReg = arrIndex->GetSingleTempReg();
1343 assert(tgtReg != tmpReg);
1345 unsigned dim = arrIndex->gtCurrDim;
1346 unsigned rank = arrIndex->gtArrRank;
1347 var_types elemType = arrIndex->gtArrElemType;
1350 offset = genOffsetOfMDArrayLowerBound(elemType, rank, dim);
1351 emit->emitIns_R_R_I(ins_Load(TYP_INT), EA_PTRSIZE, tmpReg, arrReg, offset); // a 4 BYTE sign extending load
1352 emit->emitIns_R_R_R(INS_sub, EA_4BYTE, tgtReg, indexReg, tmpReg);
1354 offset = genOffsetOfMDArrayDimensionSize(elemType, rank, dim);
1355 emit->emitIns_R_R_I(ins_Load(TYP_INT), EA_PTRSIZE, tmpReg, arrReg, offset); // a 4 BYTE sign extending load
1356 emit->emitIns_R_R(INS_cmp, EA_4BYTE, tgtReg, tmpReg);
1358 emitJumpKind jmpGEU = genJumpKindForOper(GT_GE, CK_UNSIGNED);
1359 genJumpToThrowHlpBlk(jmpGEU, SCK_RNGCHK_FAIL);
1361 genProduceReg(arrIndex);
1364 //------------------------------------------------------------------------
1365 // genCodeForArrOffset: Generates code to compute the flattened array offset for
1366 // one dimension of an array reference:
1367 // result = (prevDimOffset * dimSize) + effectiveIndex
1368 // where dimSize is obtained from the arrObj operand
1371 // arrOffset - the node for which we're generating code
1377 // dimSize and effectiveIndex are always non-negative, the former by design,
1378 // and the latter because it has been normalized to be zero-based.
1380 void CodeGen::genCodeForArrOffset(GenTreeArrOffs* arrOffset)
1382 GenTreePtr offsetNode = arrOffset->gtOffset;
1383 GenTreePtr indexNode = arrOffset->gtIndex;
1384 regNumber tgtReg = arrOffset->gtRegNum;
1386 noway_assert(tgtReg != REG_NA);
1388 if (!offsetNode->IsIntegralConst(0))
1390 emitter* emit = getEmitter();
1391 regNumber offsetReg = genConsumeReg(offsetNode);
1392 regNumber indexReg = genConsumeReg(indexNode);
1393 regNumber arrReg = genConsumeReg(arrOffset->gtArrObj);
1394 noway_assert(offsetReg != REG_NA);
1395 noway_assert(indexReg != REG_NA);
1396 noway_assert(arrReg != REG_NA);
1398 regNumber tmpReg = arrOffset->GetSingleTempReg();
1400 unsigned dim = arrOffset->gtCurrDim;
1401 unsigned rank = arrOffset->gtArrRank;
1402 var_types elemType = arrOffset->gtArrElemType;
1403 unsigned offset = genOffsetOfMDArrayDimensionSize(elemType, rank, dim);
1405 // Load tmpReg with the dimension size and evaluate
1406 // tgtReg = offsetReg*tmpReg + indexReg.
1407 emit->emitIns_R_R_I(ins_Load(TYP_INT), EA_PTRSIZE, tmpReg, arrReg, offset);
1408 emit->emitIns_R_R_R_R(INS_MULADD, EA_PTRSIZE, tgtReg, tmpReg, offsetReg, indexReg);
1412 regNumber indexReg = genConsumeReg(indexNode);
1413 if (indexReg != tgtReg)
1415 inst_RV_RV(INS_mov, tgtReg, indexReg, TYP_INT);
1418 genProduceReg(arrOffset);
1421 //------------------------------------------------------------------------
1422 // indirForm: Make a temporary indir we can feed to pattern matching routines
1423 // in cases where we don't want to instantiate all the indirs that happen.
1425 GenTreeIndir CodeGen::indirForm(var_types type, GenTree* base)
1427 GenTreeIndir i(GT_IND, type, base, nullptr);
1428 i.gtRegNum = REG_NA;
1430 // has to be nonnull (because contained nodes can't be the last in block)
1431 // but don't want it to be a valid pointer
1432 i.gtNext = (GenTree*)(-1);
1436 //------------------------------------------------------------------------
1437 // intForm: Make a temporary int we can feed to pattern matching routines
1438 // in cases where we don't want to instantiate.
1440 GenTreeIntCon CodeGen::intForm(var_types type, ssize_t value)
1442 GenTreeIntCon i(type, value);
1443 i.gtRegNum = REG_NA;
1444 // has to be nonnull (because contained nodes can't be the last in block)
1445 // but don't want it to be a valid pointer
1446 i.gtNext = (GenTree*)(-1);
1450 //------------------------------------------------------------------------
1451 // genCodeForShift: Generates the code sequence for a GenTree node that
1452 // represents a bit shift or rotate operation (<<, >>, >>>, rol, ror).
1455 // tree - the bit shift node (that specifies the type of bit shift to perform).
1458 // a) All GenTrees are register allocated.
1460 void CodeGen::genCodeForShift(GenTreePtr tree)
1462 var_types targetType = tree->TypeGet();
1463 genTreeOps oper = tree->OperGet();
1464 instruction ins = genGetInsForOper(oper, targetType);
1465 emitAttr size = emitTypeSize(tree);
1467 assert(tree->gtRegNum != REG_NA);
1469 genConsumeOperands(tree->AsOp());
1471 GenTreePtr operand = tree->gtGetOp1();
1472 GenTreePtr shiftBy = tree->gtGetOp2();
1473 if (!shiftBy->IsCnsIntOrI())
1475 getEmitter()->emitIns_R_R_R(ins, size, tree->gtRegNum, operand->gtRegNum, shiftBy->gtRegNum);
1479 unsigned immWidth = emitter::getBitWidth(size); // For ARM64, immWidth will be set to 32 or 64
1480 ssize_t shiftByImm = shiftBy->gtIntCon.gtIconVal & (immWidth - 1);
1482 getEmitter()->emitIns_R_R_I(ins, size, tree->gtRegNum, operand->gtRegNum, shiftByImm);
1485 genProduceReg(tree);
1488 //------------------------------------------------------------------------
1489 // genCodeForLclAddr: Generates the code for GT_LCL_FLD_ADDR/GT_LCL_VAR_ADDR.
1494 void CodeGen::genCodeForLclAddr(GenTree* tree)
1496 assert(tree->OperIs(GT_LCL_FLD_ADDR, GT_LCL_VAR_ADDR));
1498 var_types targetType = tree->TypeGet();
1499 regNumber targetReg = tree->gtRegNum;
1501 // Address of a local var.
1502 noway_assert(targetType == TYP_BYREF);
1504 inst_RV_TT(INS_lea, targetReg, tree, 0, EA_BYREF);
1505 genProduceReg(tree);
1508 //------------------------------------------------------------------------
1509 // genCodeForLclFld: Produce code for a GT_LCL_FLD node.
1512 // tree - the GT_LCL_FLD node
1514 void CodeGen::genCodeForLclFld(GenTreeLclFld* tree)
1516 assert(tree->OperIs(GT_LCL_FLD));
1518 var_types targetType = tree->TypeGet();
1519 regNumber targetReg = tree->gtRegNum;
1520 emitter* emit = getEmitter();
1522 NYI_IF(targetType == TYP_STRUCT, "GT_LCL_FLD: struct load local field not supported");
1523 assert(targetReg != REG_NA);
1525 emitAttr size = emitTypeSize(targetType);
1526 unsigned offs = tree->gtLclOffs;
1527 unsigned varNum = tree->gtLclNum;
1528 assert(varNum < compiler->lvaCount);
1530 if (varTypeIsFloating(targetType))
1532 emit->emitIns_R_S(ins_Load(targetType), size, targetReg, varNum, offs);
1536 #ifdef _TARGET_ARM64_
1537 size = EA_SET_SIZE(size, EA_8BYTE);
1538 #endif // _TARGET_ARM64_
1539 emit->emitIns_R_S(ins_Move_Extend(targetType, false), size, targetReg, varNum, offs);
1542 genProduceReg(tree);
1545 //------------------------------------------------------------------------
1546 // genCodeForIndir: Produce code for a GT_IND node.
1549 // tree - the GT_IND node
1551 void CodeGen::genCodeForIndir(GenTreeIndir* tree)
1553 assert(tree->OperIs(GT_IND));
1555 var_types targetType = tree->TypeGet();
1556 regNumber targetReg = tree->gtRegNum;
1557 emitter* emit = getEmitter();
1558 emitAttr attr = emitTypeSize(tree);
1559 instruction ins = ins_Load(targetType);
1561 assert((attr != EA_1BYTE) || !(tree->gtFlags & GTF_IND_UNALIGNED));
1563 genConsumeAddress(tree->Addr());
1564 if (tree->gtFlags & GTF_IND_VOLATILE)
1566 #ifdef _TARGET_ARM64_
1567 GenTree* addr = tree->Addr();
1568 bool useLoadAcquire = genIsValidIntReg(targetReg) && !addr->isContained() &&
1569 (varTypeIsUnsigned(targetType) || varTypeIsI(targetType)) &&
1570 !(tree->gtFlags & GTF_IND_UNALIGNED);
1574 switch (EA_SIZE(attr))
1577 assert(ins == INS_ldrb);
1581 assert(ins == INS_ldrh);
1586 assert(ins == INS_ldr);
1590 assert(false); // We should not get here
1594 emit->emitInsLoadStoreOp(ins, attr, targetReg, tree);
1596 if (!useLoadAcquire) // issue a INS_BARRIER_OSHLD after a volatile LdInd operation
1597 instGen_MemoryBarrier(INS_BARRIER_OSHLD);
1599 emit->emitInsLoadStoreOp(ins, attr, targetReg, tree);
1601 // issue a full memory barrier after a volatile LdInd operation
1602 instGen_MemoryBarrier();
1603 #endif // _TARGET_ARM64_
1607 emit->emitInsLoadStoreOp(ins, attr, targetReg, tree);
1610 genProduceReg(tree);
1613 // Generate code for a CpBlk node by the means of the VM memcpy helper call
1615 // a) The size argument of the CpBlk is not an integer constant
1616 // b) The size argument is a constant but is larger than CPBLK_MOVS_LIMIT bytes.
1617 void CodeGen::genCodeForCpBlk(GenTreeBlk* cpBlkNode)
1619 // Make sure we got the arguments of the cpblk operation in the right registers
1620 unsigned blockSize = cpBlkNode->Size();
1621 GenTreePtr dstAddr = cpBlkNode->Addr();
1622 assert(!dstAddr->isContained());
1624 genConsumeBlockOp(cpBlkNode, REG_ARG_0, REG_ARG_1, REG_ARG_2);
1626 #ifdef _TARGET_ARM64_
1629 assert(blockSize > CPBLK_UNROLL_LIMIT);
1631 #endif // _TARGET_ARM64_
1633 if (cpBlkNode->gtFlags & GTF_BLK_VOLATILE)
1635 // issue a full memory barrier before a volatile CpBlk operation
1636 instGen_MemoryBarrier();
1639 genEmitHelperCall(CORINFO_HELP_MEMCPY, 0, EA_UNKNOWN);
1641 if (cpBlkNode->gtFlags & GTF_BLK_VOLATILE)
1643 #ifdef _TARGET_ARM64_
1644 // issue a INS_BARRIER_ISHLD after a volatile CpBlk operation
1645 instGen_MemoryBarrier(INS_BARRIER_ISHLD);
1647 // issue a full memory barrier after a volatile CpBlk operation
1648 instGen_MemoryBarrier();
1649 #endif // _TARGET_ARM64_
1653 // Generates code for InitBlk by calling the VM memset helper function.
1655 // a) The size argument of the InitBlk is not an integer constant.
1656 // b) The size argument of the InitBlk is >= INITBLK_STOS_LIMIT bytes.
1657 void CodeGen::genCodeForInitBlk(GenTreeBlk* initBlkNode)
1659 // Make sure we got the arguments of the initblk operation in the right registers
1660 unsigned size = initBlkNode->Size();
1661 GenTreePtr dstAddr = initBlkNode->Addr();
1662 GenTreePtr initVal = initBlkNode->Data();
1663 if (initVal->OperIsInitVal())
1665 initVal = initVal->gtGetOp1();
1668 assert(!dstAddr->isContained());
1669 assert(!initVal->isContained());
1670 if (initBlkNode->gtOper == GT_STORE_DYN_BLK)
1672 assert(initBlkNode->AsDynBlk()->gtDynamicSize->gtRegNum == REG_ARG_2);
1676 assert(initBlkNode->gtRsvdRegs == RBM_ARG_2);
1679 #ifdef _TARGET_ARM64_
1682 assert(size > INITBLK_UNROLL_LIMIT);
1684 #endif // _TARGET_ARM64_
1686 genConsumeBlockOp(initBlkNode, REG_ARG_0, REG_ARG_1, REG_ARG_2);
1688 if (initBlkNode->gtFlags & GTF_BLK_VOLATILE)
1690 // issue a full memory barrier before a volatile initBlock Operation
1691 instGen_MemoryBarrier();
1694 genEmitHelperCall(CORINFO_HELP_MEMSET, 0, EA_UNKNOWN);
1697 //------------------------------------------------------------------------
1698 // genRegCopy: Generate a register copy.
1700 void CodeGen::genRegCopy(GenTree* treeNode)
1702 assert(treeNode->OperGet() == GT_COPY);
1704 var_types targetType = treeNode->TypeGet();
1705 regNumber targetReg = treeNode->gtRegNum;
1706 assert(targetReg != REG_NA);
1708 GenTree* op1 = treeNode->gtOp.gtOp1;
1710 // Check whether this node and the node from which we're copying the value have the same
1712 // This can happen if (currently iff) we have a SIMD vector type that fits in an integer
1713 // register, in which case it is passed as an argument, or returned from a call,
1714 // in an integer register and must be copied if it's in an xmm register.
1716 if (varTypeIsFloating(treeNode) != varTypeIsFloating(op1))
1718 #ifdef _TARGET_ARM64_
1719 inst_RV_RV(INS_fmov, targetReg, genConsumeReg(op1), targetType);
1720 #else // !_TARGET_ARM64_
1721 if (varTypeIsFloating(treeNode))
1723 NYI_ARM("genRegCopy from 'int' to 'float'");
1727 assert(varTypeIsFloating(op1));
1729 if (op1->TypeGet() == TYP_FLOAT)
1731 inst_RV_RV(INS_vmov_f2i, targetReg, genConsumeReg(op1), targetType);
1735 regNumber otherReg = (regNumber)treeNode->AsCopyOrReload()->gtOtherRegs[0];
1736 assert(otherReg != REG_NA);
1737 inst_RV_RV_RV(INS_vmov_d2i, targetReg, otherReg, genConsumeReg(op1), EA_8BYTE);
1740 #endif // !_TARGET_ARM64_
1744 inst_RV_RV(ins_Copy(targetType), targetReg, genConsumeReg(op1), targetType);
1749 // The lclVar will never be a def.
1750 // If it is a last use, the lclVar will be killed by genConsumeReg(), as usual, and genProduceReg will
1751 // appropriately set the gcInfo for the copied value.
1752 // If not, there are two cases we need to handle:
1753 // - If this is a TEMPORARY copy (indicated by the GTF_VAR_DEATH flag) the variable
1754 // will remain live in its original register.
1755 // genProduceReg() will appropriately set the gcInfo for the copied value,
1756 // and genConsumeReg will reset it.
1757 // - Otherwise, we need to update register info for the lclVar.
1759 GenTreeLclVarCommon* lcl = op1->AsLclVarCommon();
1760 assert((lcl->gtFlags & GTF_VAR_DEF) == 0);
1762 if ((lcl->gtFlags & GTF_VAR_DEATH) == 0 && (treeNode->gtFlags & GTF_VAR_DEATH) == 0)
1764 LclVarDsc* varDsc = &compiler->lvaTable[lcl->gtLclNum];
1766 // If we didn't just spill it (in genConsumeReg, above), then update the register info
1767 if (varDsc->lvRegNum != REG_STK)
1769 // The old location is dying
1770 genUpdateRegLife(varDsc, /*isBorn*/ false, /*isDying*/ true DEBUGARG(op1));
1772 gcInfo.gcMarkRegSetNpt(genRegMask(op1->gtRegNum));
1774 genUpdateVarReg(varDsc, treeNode);
1776 // The new location is going live
1777 genUpdateRegLife(varDsc, /*isBorn*/ true, /*isDying*/ false DEBUGARG(treeNode));
1782 genProduceReg(treeNode);
1785 //------------------------------------------------------------------------
1786 // genCallInstruction: Produce code for a GT_CALL node
1788 void CodeGen::genCallInstruction(GenTreeCall* call)
1790 gtCallTypes callType = (gtCallTypes)call->gtCallType;
1792 IL_OFFSETX ilOffset = BAD_IL_OFFSET;
1794 // all virtuals should have been expanded into a control expression
1795 assert(!call->IsVirtual() || call->gtControlExpr || call->gtCallAddr);
1797 // Consume all the arg regs
1798 for (GenTreePtr list = call->gtCallLateArgs; list; list = list->MoveNext())
1800 assert(list->OperIsList());
1802 GenTreePtr argNode = list->Current();
1804 fgArgTabEntryPtr curArgTabEntry = compiler->gtArgEntryByNode(call, argNode->gtSkipReloadOrCopy());
1805 assert(curArgTabEntry);
1807 if (curArgTabEntry->regNum == REG_STK)
1810 // Deal with multi register passed struct args.
1811 if (argNode->OperGet() == GT_FIELD_LIST)
1813 GenTreeArgList* argListPtr = argNode->AsArgList();
1814 unsigned iterationNum = 0;
1815 regNumber argReg = curArgTabEntry->regNum;
1816 for (; argListPtr != nullptr; argListPtr = argListPtr->Rest(), iterationNum++)
1818 GenTreePtr putArgRegNode = argListPtr->gtOp.gtOp1;
1819 assert(putArgRegNode->gtOper == GT_PUTARG_REG);
1821 genConsumeReg(putArgRegNode);
1823 if (putArgRegNode->gtRegNum != argReg)
1825 inst_RV_RV(ins_Move_Extend(putArgRegNode->TypeGet(), true), argReg, putArgRegNode->gtRegNum);
1828 argReg = genRegArgNext(argReg);
1830 #if defined(_TARGET_ARM_)
1831 // A double register is modelled as an even-numbered single one
1832 if (putArgRegNode->TypeGet() == TYP_DOUBLE)
1834 argReg = genRegArgNext(argReg);
1836 #endif // _TARGET_ARM_
1840 else if (curArgTabEntry->isSplit)
1842 assert(curArgTabEntry->numRegs >= 1);
1843 genConsumeArgSplitStruct(argNode->AsPutArgSplit());
1844 for (unsigned idx = 0; idx < curArgTabEntry->numRegs; idx++)
1846 regNumber argReg = (regNumber)((unsigned)curArgTabEntry->regNum + idx);
1847 regNumber allocReg = argNode->AsPutArgSplit()->GetRegNumByIdx(idx);
1848 if (argReg != allocReg)
1850 inst_RV_RV(ins_Move_Extend(argNode->TypeGet(), true), argReg, allocReg);
1857 regNumber argReg = curArgTabEntry->regNum;
1858 genConsumeReg(argNode);
1859 if (argNode->gtRegNum != argReg)
1861 inst_RV_RV(ins_Move_Extend(argNode->TypeGet(), true), argReg, argNode->gtRegNum);
1865 // In the case of a varargs call,
1866 // the ABI dictates that if we have floating point args,
1867 // we must pass the enregistered arguments in both the
1868 // integer and floating point registers so, let's do that.
1869 if (call->IsVarargs() && varTypeIsFloating(argNode))
1871 NYI_ARM("CodeGen - IsVarargs");
1872 NYI_ARM64("CodeGen - IsVarargs");
1876 // Insert a null check on "this" pointer if asked.
1877 if (call->NeedsNullCheck())
1879 const regNumber regThis = genGetThisArgReg(call);
1881 #if defined(_TARGET_ARM_)
1882 const regNumber tmpReg = call->ExtractTempReg();
1883 getEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, tmpReg, regThis, 0);
1884 #elif defined(_TARGET_ARM64_)
1885 getEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, REG_ZR, regThis, 0);
1889 // Either gtControlExpr != null or gtCallAddr != null or it is a direct non-virtual call to a user or helper method.
1890 CORINFO_METHOD_HANDLE methHnd;
1891 GenTree* target = call->gtControlExpr;
1892 if (callType == CT_INDIRECT)
1894 assert(target == nullptr);
1895 target = call->gtCallAddr;
1900 methHnd = call->gtCallMethHnd;
1903 CORINFO_SIG_INFO* sigInfo = nullptr;
1905 // Pass the call signature information down into the emitter so the emitter can associate
1906 // native call sites with the signatures they were generated from.
1907 if (callType != CT_HELPER)
1909 sigInfo = call->callSig;
1913 // If fast tail call, then we are done. In this case we setup the args (both reg args
1914 // and stack args in incoming arg area) and call target. Epilog sequence would
1915 // generate "br <reg>".
1916 if (call->IsFastTailCall())
1918 // Don't support fast tail calling JIT helpers
1919 assert(callType != CT_HELPER);
1921 // Fast tail calls materialize call target either in gtControlExpr or in gtCallAddr.
1922 assert(target != nullptr);
1924 genConsumeReg(target);
1926 NYI_ARM("fast tail call");
1928 #ifdef _TARGET_ARM64_
1929 // Use IP0 as the call target register.
1930 if (target->gtRegNum != REG_IP0)
1932 inst_RV_RV(INS_mov, REG_IP0, target->gtRegNum);
1934 #endif // _TARGET_ARM64_
1939 // For a pinvoke to unmanaged code we emit a label to clear
1940 // the GC pointer state before the callsite.
1941 // We can't utilize the typical lazy killing of GC pointers
1942 // at (or inside) the callsite.
1943 if (call->IsUnmanaged())
1945 genDefineTempLabel(genCreateTempLabel());
1948 // Determine return value size(s).
1949 ReturnTypeDesc* pRetTypeDesc = call->GetReturnTypeDesc();
1950 emitAttr retSize = EA_PTRSIZE;
1951 emitAttr secondRetSize = EA_UNKNOWN;
1953 if (call->HasMultiRegRetVal())
1955 retSize = emitTypeSize(pRetTypeDesc->GetReturnRegType(0));
1956 secondRetSize = emitTypeSize(pRetTypeDesc->GetReturnRegType(1));
1960 assert(!varTypeIsStruct(call));
1962 if (call->gtType == TYP_REF || call->gtType == TYP_ARRAY)
1966 else if (call->gtType == TYP_BYREF)
1972 // We need to propagate the IL offset information to the call instruction, so we can emit
1973 // an IL to native mapping record for the call, to support managed return value debugging.
1974 // We don't want tail call helper calls that were converted from normal calls to get a record,
1975 // so we skip this hash table lookup logic in that case.
1976 if (compiler->opts.compDbgInfo && compiler->genCallSite2ILOffsetMap != nullptr && !call->IsTailCall())
1978 (void)compiler->genCallSite2ILOffsetMap->Lookup(call, &ilOffset);
1981 if (target != nullptr)
1983 // A call target can not be a contained indirection
1984 assert(!target->isContainedIndir());
1986 genConsumeReg(target);
1988 // We have already generated code for gtControlExpr evaluating it into a register.
1989 // We just need to emit "call reg" in this case.
1991 assert(genIsValidIntReg(target->gtRegNum));
1993 genEmitCall(emitter::EC_INDIR_R, methHnd,
1994 INDEBUG_LDISASM_COMMA(sigInfo) nullptr, // addr
1995 retSize MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(secondRetSize), ilOffset, target->gtRegNum);
1999 // Generate a direct call to a non-virtual user defined or helper method
2000 assert(callType == CT_HELPER || callType == CT_USER_FUNC);
2002 void* addr = nullptr;
2003 if (callType == CT_HELPER)
2005 // Direct call to a helper method.
2006 CorInfoHelpFunc helperNum = compiler->eeGetHelperNum(methHnd);
2007 noway_assert(helperNum != CORINFO_HELP_UNDEF);
2009 void* pAddr = nullptr;
2010 addr = compiler->compGetHelperFtn(helperNum, (void**)&pAddr);
2012 if (addr == nullptr)
2019 // Direct call to a non-virtual user function.
2020 CORINFO_ACCESS_FLAGS aflags = CORINFO_ACCESS_ANY;
2021 if (call->IsSameThis())
2023 aflags = (CORINFO_ACCESS_FLAGS)(aflags | CORINFO_ACCESS_THIS);
2026 if ((call->NeedsNullCheck()) == 0)
2028 aflags = (CORINFO_ACCESS_FLAGS)(aflags | CORINFO_ACCESS_NONNULL);
2031 CORINFO_CONST_LOOKUP addrInfo;
2032 compiler->info.compCompHnd->getFunctionEntryPoint(methHnd, &addrInfo, aflags);
2034 addr = addrInfo.addr;
2037 assert(addr != nullptr);
2039 // Non-virtual direct call to known addresses
2041 if (!arm_Valid_Imm_For_BL((ssize_t)addr))
2043 regNumber tmpReg = call->GetSingleTempReg();
2044 instGen_Set_Reg_To_Imm(EA_HANDLE_CNS_RELOC, tmpReg, (ssize_t)addr);
2045 genEmitCall(emitter::EC_INDIR_R, methHnd, INDEBUG_LDISASM_COMMA(sigInfo) NULL, retSize, ilOffset, tmpReg);
2048 #endif // _TARGET_ARM_
2050 genEmitCall(emitter::EC_FUNC_TOKEN, methHnd, INDEBUG_LDISASM_COMMA(sigInfo) addr,
2051 retSize MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(secondRetSize), ilOffset);
2054 #if 0 && defined(_TARGET_ARM64_)
2055 // Use this path if you want to load an absolute call target using
2056 // a sequence of movs followed by an indirect call (blr instruction)
2058 // Load the call target address in x16
2059 instGen_Set_Reg_To_Imm(EA_8BYTE, REG_IP0, (ssize_t) addr);
2061 // indirect call to constant address in IP0
2062 genEmitCall(emitter::EC_INDIR_R,
2064 INDEBUG_LDISASM_COMMA(sigInfo)
2073 // if it was a pinvoke we may have needed to get the address of a label
2074 if (genPendingCallLabel)
2076 assert(call->IsUnmanaged());
2077 genDefineTempLabel(genPendingCallLabel);
2078 genPendingCallLabel = nullptr;
2082 // All Callee arg registers are trashed and no longer contain any GC pointers.
2083 // TODO-Bug?: As a matter of fact shouldn't we be killing all of callee trashed regs here?
2084 // For now we will assert that other than arg regs gc ref/byref set doesn't contain any other
2085 // registers from RBM_CALLEE_TRASH
2086 assert((gcInfo.gcRegGCrefSetCur & (RBM_CALLEE_TRASH & ~RBM_ARG_REGS)) == 0);
2087 assert((gcInfo.gcRegByrefSetCur & (RBM_CALLEE_TRASH & ~RBM_ARG_REGS)) == 0);
2088 gcInfo.gcRegGCrefSetCur &= ~RBM_ARG_REGS;
2089 gcInfo.gcRegByrefSetCur &= ~RBM_ARG_REGS;
2091 var_types returnType = call->TypeGet();
2092 if (returnType != TYP_VOID)
2094 regNumber returnReg;
2096 if (call->HasMultiRegRetVal())
2098 assert(pRetTypeDesc != nullptr);
2099 unsigned regCount = pRetTypeDesc->GetReturnRegCount();
2101 // If regs allocated to call node are different from ABI return
2102 // regs in which the call has returned its result, move the result
2103 // to regs allocated to call node.
2104 for (unsigned i = 0; i < regCount; ++i)
2106 var_types regType = pRetTypeDesc->GetReturnRegType(i);
2107 returnReg = pRetTypeDesc->GetABIReturnReg(i);
2108 regNumber allocatedReg = call->GetRegNumByIdx(i);
2109 if (returnReg != allocatedReg)
2111 inst_RV_RV(ins_Copy(regType), allocatedReg, returnReg, regType);
2118 if (call->IsHelperCall(compiler, CORINFO_HELP_INIT_PINVOKE_FRAME))
2120 // The CORINFO_HELP_INIT_PINVOKE_FRAME helper uses a custom calling convention that returns with
2121 // TCB in REG_PINVOKE_TCB. fgMorphCall() sets the correct argument registers.
2122 returnReg = REG_PINVOKE_TCB;
2125 #endif // _TARGET_ARM_
2126 if (varTypeIsFloating(returnType) && !compiler->opts.compUseSoftFP)
2128 returnReg = REG_FLOATRET;
2132 returnReg = REG_INTRET;
2135 if (call->gtRegNum != returnReg)
2138 if (compiler->opts.compUseSoftFP && returnType == TYP_DOUBLE)
2140 inst_RV_RV_RV(INS_vmov_i2d, call->gtRegNum, returnReg, genRegArgNext(returnReg), EA_8BYTE);
2142 else if (compiler->opts.compUseSoftFP && returnType == TYP_FLOAT)
2144 inst_RV_RV(INS_vmov_i2f, call->gtRegNum, returnReg, returnType);
2149 inst_RV_RV(ins_Copy(returnType), call->gtRegNum, returnReg, returnType);
2154 genProduceReg(call);
2157 // If there is nothing next, that means the result is thrown away, so this value is not live.
2158 // However, for minopts or debuggable code, we keep it live to support managed return value debugging.
2159 if ((call->gtNext == nullptr) && !compiler->opts.MinOpts() && !compiler->opts.compDbgCode)
2161 gcInfo.gcMarkRegSetNpt(RBM_INTRET);
2165 // Produce code for a GT_JMP node.
2166 // The arguments of the caller needs to be transferred to the callee before exiting caller.
2167 // The actual jump to callee is generated as part of caller epilog sequence.
2168 // Therefore the codegen of GT_JMP is to ensure that the callee arguments are correctly setup.
2169 void CodeGen::genJmpMethod(GenTreePtr jmp)
2171 assert(jmp->OperGet() == GT_JMP);
2172 assert(compiler->compJmpOpUsed);
2174 // If no arguments, nothing to do
2175 if (compiler->info.compArgsCount == 0)
2180 // Make sure register arguments are in their initial registers
2181 // and stack arguments are put back as well.
2185 // First move any en-registered stack arguments back to the stack.
2186 // At the same time any reg arg not in correct reg is moved back to its stack location.
2188 // We are not strictly required to spill reg args that are not in the desired reg for a jmp call
2189 // But that would require us to deal with circularity while moving values around. Spilling
2190 // to stack makes the implementation simple, which is not a bad trade off given Jmp calls
2191 // are not frequent.
2192 for (varNum = 0; (varNum < compiler->info.compArgsCount); varNum++)
2194 varDsc = compiler->lvaTable + varNum;
2196 if (varDsc->lvPromoted)
2198 noway_assert(varDsc->lvFieldCnt == 1); // We only handle one field here
2200 unsigned fieldVarNum = varDsc->lvFieldLclStart;
2201 varDsc = compiler->lvaTable + fieldVarNum;
2203 noway_assert(varDsc->lvIsParam);
2205 if (varDsc->lvIsRegArg && (varDsc->lvRegNum != REG_STK))
2207 // Skip reg args which are already in its right register for jmp call.
2208 // If not, we will spill such args to their stack locations.
2210 // If we need to generate a tail call profiler hook, then spill all
2211 // arg regs to free them up for the callback.
2212 if (!compiler->compIsProfilerHookNeeded() && (varDsc->lvRegNum == varDsc->lvArgReg))
2215 else if (varDsc->lvRegNum == REG_STK)
2217 // Skip args which are currently living in stack.
2221 // If we came here it means either a reg argument not in the right register or
2222 // a stack argument currently living in a register. In either case the following
2223 // assert should hold.
2224 assert(varDsc->lvRegNum != REG_STK);
2225 assert(varDsc->TypeGet() != TYP_STRUCT);
2226 var_types storeType = genActualType(varDsc->TypeGet());
2227 emitAttr storeSize = emitActualTypeSize(storeType);
2229 getEmitter()->emitIns_S_R(ins_Store(storeType), storeSize, varDsc->lvRegNum, varNum, 0);
2230 // Update lvRegNum life and GC info to indicate lvRegNum is dead and varDsc stack slot is going live.
2231 // Note that we cannot modify varDsc->lvRegNum here because another basic block may not be expecting it.
2232 // Therefore manually update life of varDsc->lvRegNum.
2233 regMaskTP tempMask = genRegMask(varDsc->lvRegNum);
2234 regSet.RemoveMaskVars(tempMask);
2235 gcInfo.gcMarkRegSetNpt(tempMask);
2236 if (compiler->lvaIsGCTracked(varDsc))
2238 VarSetOps::AddElemD(compiler, gcInfo.gcVarPtrSetCur, varNum);
2242 #ifdef PROFILING_SUPPORTED
2243 // At this point all arg regs are free.
2244 // Emit tail call profiler callback.
2245 genProfilingLeaveCallback(CORINFO_HELP_PROF_FCN_TAILCALL);
2248 // Next move any un-enregistered register arguments back to their register.
2249 regMaskTP fixedIntArgMask = RBM_NONE; // tracks the int arg regs occupying fixed args in case of a vararg method.
2250 unsigned firstArgVarNum = BAD_VAR_NUM; // varNum of the first argument in case of a vararg method.
2251 for (varNum = 0; (varNum < compiler->info.compArgsCount); varNum++)
2253 varDsc = compiler->lvaTable + varNum;
2254 if (varDsc->lvPromoted)
2256 noway_assert(varDsc->lvFieldCnt == 1); // We only handle one field here
2258 unsigned fieldVarNum = varDsc->lvFieldLclStart;
2259 varDsc = compiler->lvaTable + fieldVarNum;
2261 noway_assert(varDsc->lvIsParam);
2263 // Skip if arg not passed in a register.
2264 if (!varDsc->lvIsRegArg)
2267 // Register argument
2268 noway_assert(isRegParamType(genActualType(varDsc->TypeGet())));
2270 // Is register argument already in the right register?
2271 // If not load it from its stack location.
2272 regNumber argReg = varDsc->lvArgReg; // incoming arg register
2273 regNumber argRegNext = REG_NA;
2275 if (varDsc->lvRegNum != argReg)
2277 var_types loadType = TYP_UNDEF;
2278 if (varTypeIsStruct(varDsc))
2280 // Must be <= 16 bytes or else it wouldn't be passed in registers
2281 noway_assert(EA_SIZE_IN_BYTES(varDsc->lvSize()) <= MAX_PASS_MULTIREG_BYTES);
2282 loadType = compiler->getJitGCType(varDsc->lvGcLayout[0]);
2286 loadType = compiler->mangleVarArgsType(genActualType(varDsc->TypeGet()));
2288 emitAttr loadSize = emitActualTypeSize(loadType);
2289 getEmitter()->emitIns_R_S(ins_Load(loadType), loadSize, argReg, varNum, 0);
2291 // Update argReg life and GC Info to indicate varDsc stack slot is dead and argReg is going live.
2292 // Note that we cannot modify varDsc->lvRegNum here because another basic block may not be expecting it.
2293 // Therefore manually update life of argReg. Note that GT_JMP marks the end of the basic block
2294 // and after which reg life and gc info will be recomputed for the new block in genCodeForBBList().
2295 regSet.AddMaskVars(genRegMask(argReg));
2296 gcInfo.gcMarkRegPtrVal(argReg, loadType);
2298 if (compiler->lvaIsMultiregStruct(varDsc))
2300 if (varDsc->lvIsHfa())
2302 NYI_ARM("CodeGen::genJmpMethod with multireg HFA arg");
2303 NYI_ARM64("CodeGen::genJmpMethod with multireg HFA arg");
2306 // Restore the second register.
2307 argRegNext = genRegArgNext(argReg);
2309 loadType = compiler->getJitGCType(varDsc->lvGcLayout[1]);
2310 loadSize = emitActualTypeSize(loadType);
2311 getEmitter()->emitIns_R_S(ins_Load(loadType), loadSize, argRegNext, varNum, TARGET_POINTER_SIZE);
2313 regSet.AddMaskVars(genRegMask(argRegNext));
2314 gcInfo.gcMarkRegPtrVal(argRegNext, loadType);
2317 if (compiler->lvaIsGCTracked(varDsc))
2319 VarSetOps::RemoveElemD(compiler, gcInfo.gcVarPtrSetCur, varNum);
2323 // In case of a jmp call to a vararg method ensure only integer registers are passed.
2324 if (compiler->info.compIsVarArgs)
2326 assert((genRegMask(argReg) & RBM_ARG_REGS) != RBM_NONE);
2328 fixedIntArgMask |= genRegMask(argReg);
2330 if (compiler->lvaIsMultiregStruct(varDsc))
2332 assert(argRegNext != REG_NA);
2333 fixedIntArgMask |= genRegMask(argRegNext);
2336 if (argReg == REG_ARG_0)
2338 assert(firstArgVarNum == BAD_VAR_NUM);
2339 firstArgVarNum = varNum;
2344 // Jmp call to a vararg method - if the method has fewer than fixed arguments that can be max size of reg,
2345 // load the remaining integer arg registers from the corresponding
2346 // shadow stack slots. This is for the reason that we don't know the number and type
2347 // of non-fixed params passed by the caller, therefore we have to assume the worst case
2348 // of caller passing all integer arg regs that can be max size of reg.
2350 // The caller could have passed gc-ref/byref type var args. Since these are var args
2351 // the callee no way of knowing their gc-ness. Therefore, mark the region that loads
2352 // remaining arg registers from shadow stack slots as non-gc interruptible.
2353 if (fixedIntArgMask != RBM_NONE)
2355 assert(compiler->info.compIsVarArgs);
2356 assert(firstArgVarNum != BAD_VAR_NUM);
2358 regMaskTP remainingIntArgMask = RBM_ARG_REGS & ~fixedIntArgMask;
2359 if (remainingIntArgMask != RBM_NONE)
2361 getEmitter()->emitDisableGC();
2362 for (int argNum = 0, argOffset = 0; argNum < MAX_REG_ARG; ++argNum)
2364 regNumber argReg = intArgRegs[argNum];
2365 regMaskTP argRegMask = genRegMask(argReg);
2367 if ((remainingIntArgMask & argRegMask) != 0)
2369 remainingIntArgMask &= ~argRegMask;
2370 getEmitter()->emitIns_R_S(INS_ldr, EA_PTRSIZE, argReg, firstArgVarNum, argOffset);
2373 argOffset += REGSIZE_BYTES;
2375 getEmitter()->emitEnableGC();
2380 //------------------------------------------------------------------------
2381 // genIntToIntCast: Generate code for an integer cast
2384 // treeNode - The GT_CAST node
2390 // The treeNode must have an assigned register.
2391 // For a signed convert from byte, the source must be in a byte-addressable register.
2392 // Neither the source nor target type can be a floating point type.
2394 // TODO-ARM64-CQ: Allow castOp to be a contained node without an assigned register.
2396 void CodeGen::genIntToIntCast(GenTreePtr treeNode)
2398 assert(treeNode->OperGet() == GT_CAST);
2400 GenTreePtr castOp = treeNode->gtCast.CastOp();
2401 emitter* emit = getEmitter();
2403 var_types dstType = treeNode->CastToType();
2404 var_types srcType = genActualType(castOp->TypeGet());
2405 emitAttr movSize = emitActualTypeSize(dstType);
2406 bool movRequired = false;
2409 if (varTypeIsLong(srcType))
2411 genLongToIntCast(treeNode);
2414 #endif // _TARGET_ARM_
2416 regNumber targetReg = treeNode->gtRegNum;
2417 regNumber sourceReg = castOp->gtRegNum;
2419 // For Long to Int conversion we will have a reserved integer register to hold the immediate mask
2420 regNumber tmpReg = (treeNode->AvailableTempRegCount() == 0) ? REG_NA : treeNode->GetSingleTempReg();
2422 assert(genIsValidIntReg(targetReg));
2423 assert(genIsValidIntReg(sourceReg));
2425 instruction ins = INS_invalid;
2427 genConsumeReg(castOp);
2428 Lowering::CastInfo castInfo;
2430 // Get information about the cast.
2431 Lowering::getCastDescription(treeNode, &castInfo);
2433 if (castInfo.requiresOverflowCheck)
2435 emitAttr cmpSize = EA_ATTR(genTypeSize(srcType));
2437 if (castInfo.signCheckOnly)
2439 // We only need to check for a negative value in sourceReg
2440 emit->emitIns_R_I(INS_cmp, cmpSize, sourceReg, 0);
2441 emitJumpKind jmpLT = genJumpKindForOper(GT_LT, CK_SIGNED);
2442 genJumpToThrowHlpBlk(jmpLT, SCK_OVERFLOW);
2443 noway_assert(genTypeSize(srcType) == 4 || genTypeSize(srcType) == 8);
2444 // This is only interesting case to ensure zero-upper bits.
2445 if ((srcType == TYP_INT) && (dstType == TYP_ULONG))
2447 // cast to TYP_ULONG:
2448 // We use a mov with size=EA_4BYTE
2449 // which will zero out the upper bits
2454 else if (castInfo.unsignedSource || castInfo.unsignedDest)
2456 // When we are converting from/to unsigned,
2457 // we only have to check for any bits set in 'typeMask'
2459 noway_assert(castInfo.typeMask != 0);
2460 #if defined(_TARGET_ARM_)
2461 if (arm_Valid_Imm_For_Instr(INS_tst, castInfo.typeMask, INS_FLAGS_DONT_CARE))
2463 emit->emitIns_R_I(INS_tst, cmpSize, sourceReg, castInfo.typeMask);
2467 noway_assert(tmpReg != REG_NA);
2468 instGen_Set_Reg_To_Imm(cmpSize, tmpReg, castInfo.typeMask);
2469 emit->emitIns_R_R(INS_tst, cmpSize, sourceReg, tmpReg);
2471 #elif defined(_TARGET_ARM64_)
2472 emit->emitIns_R_I(INS_tst, cmpSize, sourceReg, castInfo.typeMask);
2473 #endif // _TARGET_ARM*
2474 emitJumpKind jmpNotEqual = genJumpKindForOper(GT_NE, CK_SIGNED);
2475 genJumpToThrowHlpBlk(jmpNotEqual, SCK_OVERFLOW);
2479 // For a narrowing signed cast
2481 // We must check the value is in a signed range.
2483 // Compare with the MAX
2485 noway_assert((castInfo.typeMin != 0) && (castInfo.typeMax != 0));
2487 #if defined(_TARGET_ARM_)
2488 if (emitter::emitIns_valid_imm_for_cmp(castInfo.typeMax, INS_FLAGS_DONT_CARE))
2489 #elif defined(_TARGET_ARM64_)
2490 if (emitter::emitIns_valid_imm_for_cmp(castInfo.typeMax, cmpSize))
2493 emit->emitIns_R_I(INS_cmp, cmpSize, sourceReg, castInfo.typeMax);
2497 noway_assert(tmpReg != REG_NA);
2498 instGen_Set_Reg_To_Imm(cmpSize, tmpReg, castInfo.typeMax);
2499 emit->emitIns_R_R(INS_cmp, cmpSize, sourceReg, tmpReg);
2502 emitJumpKind jmpGT = genJumpKindForOper(GT_GT, CK_SIGNED);
2503 genJumpToThrowHlpBlk(jmpGT, SCK_OVERFLOW);
2505 // Compare with the MIN
2507 #if defined(_TARGET_ARM_)
2508 if (emitter::emitIns_valid_imm_for_cmp(castInfo.typeMin, INS_FLAGS_DONT_CARE))
2509 #elif defined(_TARGET_ARM64_)
2510 if (emitter::emitIns_valid_imm_for_cmp(castInfo.typeMin, cmpSize))
2513 emit->emitIns_R_I(INS_cmp, cmpSize, sourceReg, castInfo.typeMin);
2517 noway_assert(tmpReg != REG_NA);
2518 instGen_Set_Reg_To_Imm(cmpSize, tmpReg, castInfo.typeMin);
2519 emit->emitIns_R_R(INS_cmp, cmpSize, sourceReg, tmpReg);
2522 emitJumpKind jmpLT = genJumpKindForOper(GT_LT, CK_SIGNED);
2523 genJumpToThrowHlpBlk(jmpLT, SCK_OVERFLOW);
2527 else // Non-overflow checking cast.
2529 if (genTypeSize(srcType) == genTypeSize(dstType))
2535 var_types extendType = TYP_UNKNOWN;
2537 if (genTypeSize(srcType) < genTypeSize(dstType))
2539 // If we need to treat a signed type as unsigned
2540 if ((treeNode->gtFlags & GTF_UNSIGNED) != 0)
2542 extendType = genUnsignedType(srcType);
2545 extendType = srcType;
2547 movSize = emitTypeSize(extendType);
2548 #endif // _TARGET_ARM_
2549 if (extendType == TYP_UINT)
2551 #ifdef _TARGET_ARM64_
2552 // If we are casting from a smaller type to
2553 // a larger type, then we need to make sure the
2554 // higher 4 bytes are zero to gaurentee the correct value.
2555 // Therefore using a mov with EA_4BYTE in place of EA_8BYTE
2556 // will zero the upper bits
2558 #endif // _TARGET_ARM64_
2562 else // (genTypeSize(srcType) > genTypeSize(dstType))
2564 // If we need to treat a signed type as unsigned
2565 if ((treeNode->gtFlags & GTF_UNSIGNED) != 0)
2567 extendType = genUnsignedType(dstType);
2570 extendType = dstType;
2571 #if defined(_TARGET_ARM_)
2572 movSize = emitTypeSize(extendType);
2573 #elif defined(_TARGET_ARM64_)
2574 if (extendType == TYP_INT)
2576 movSize = EA_8BYTE; // a sxtw instruction requires EA_8BYTE
2581 ins = ins_Move_Extend(extendType, true);
2585 // We should never be generating a load from memory instruction here!
2586 assert(!emit->emitInsIsLoad(ins));
2588 if ((ins != INS_mov) || movRequired || (targetReg != sourceReg))
2590 emit->emitIns_R_R(ins, movSize, targetReg, sourceReg);
2593 genProduceReg(treeNode);
2596 //------------------------------------------------------------------------
2597 // genFloatToFloatCast: Generate code for a cast between float and double
2600 // treeNode - The GT_CAST node
2606 // Cast is a non-overflow conversion.
2607 // The treeNode must have an assigned register.
2608 // The cast is between float and double.
2610 void CodeGen::genFloatToFloatCast(GenTreePtr treeNode)
2612 // float <--> double conversions are always non-overflow ones
2613 assert(treeNode->OperGet() == GT_CAST);
2614 assert(!treeNode->gtOverflow());
2616 regNumber targetReg = treeNode->gtRegNum;
2617 assert(genIsValidFloatReg(targetReg));
2619 GenTreePtr op1 = treeNode->gtOp.gtOp1;
2620 assert(!op1->isContained()); // Cannot be contained
2621 assert(genIsValidFloatReg(op1->gtRegNum)); // Must be a valid float reg.
2623 var_types dstType = treeNode->CastToType();
2624 var_types srcType = op1->TypeGet();
2625 assert(varTypeIsFloating(srcType) && varTypeIsFloating(dstType));
2627 genConsumeOperands(treeNode->AsOp());
2629 // treeNode must be a reg
2630 assert(!treeNode->isContained());
2632 #if defined(_TARGET_ARM_)
2634 if (srcType != dstType)
2636 instruction insVcvt = (srcType == TYP_FLOAT) ? INS_vcvt_f2d // convert Float to Double
2637 : INS_vcvt_d2f; // convert Double to Float
2639 getEmitter()->emitIns_R_R(insVcvt, emitTypeSize(treeNode), treeNode->gtRegNum, op1->gtRegNum);
2641 else if (treeNode->gtRegNum != op1->gtRegNum)
2643 getEmitter()->emitIns_R_R(INS_vmov, emitTypeSize(treeNode), treeNode->gtRegNum, op1->gtRegNum);
2646 #elif defined(_TARGET_ARM64_)
2648 if (srcType != dstType)
2650 insOpts cvtOption = (srcType == TYP_FLOAT) ? INS_OPTS_S_TO_D // convert Single to Double
2651 : INS_OPTS_D_TO_S; // convert Double to Single
2653 getEmitter()->emitIns_R_R(INS_fcvt, emitTypeSize(treeNode), treeNode->gtRegNum, op1->gtRegNum, cvtOption);
2655 else if (treeNode->gtRegNum != op1->gtRegNum)
2657 // If double to double cast or float to float cast. Emit a move instruction.
2658 getEmitter()->emitIns_R_R(INS_mov, emitTypeSize(treeNode), treeNode->gtRegNum, op1->gtRegNum);
2663 genProduceReg(treeNode);
2666 //------------------------------------------------------------------------
2667 // genCreateAndStoreGCInfo: Create and record GC Info for the function.
2669 void CodeGen::genCreateAndStoreGCInfo(unsigned codeSize,
2670 unsigned prologSize,
2671 unsigned epilogSize DEBUGARG(void* codePtr))
2673 IAllocator* allowZeroAlloc = new (compiler, CMK_GC) AllowZeroAllocator(compiler->getAllocatorGC());
2674 GcInfoEncoder* gcInfoEncoder = new (compiler, CMK_GC)
2675 GcInfoEncoder(compiler->info.compCompHnd, compiler->info.compMethodInfo, allowZeroAlloc, NOMEM);
2676 assert(gcInfoEncoder != nullptr);
2678 // Follow the code pattern of the x86 gc info encoder (genCreateAndStoreGCInfoJIT32).
2679 gcInfo.gcInfoBlockHdrSave(gcInfoEncoder, codeSize, prologSize);
2681 // We keep the call count for the second call to gcMakeRegPtrTable() below.
2682 unsigned callCnt = 0;
2684 // First we figure out the encoder ID's for the stack slots and registers.
2685 gcInfo.gcMakeRegPtrTable(gcInfoEncoder, codeSize, prologSize, GCInfo::MAKE_REG_PTR_MODE_ASSIGN_SLOTS, &callCnt);
2687 // Now we've requested all the slots we'll need; "finalize" these (make more compact data structures for them).
2688 gcInfoEncoder->FinalizeSlotIds();
2690 // Now we can actually use those slot ID's to declare live ranges.
2691 gcInfo.gcMakeRegPtrTable(gcInfoEncoder, codeSize, prologSize, GCInfo::MAKE_REG_PTR_MODE_DO_WORK, &callCnt);
2693 #ifdef _TARGET_ARM64_
2695 if (compiler->opts.compDbgEnC)
2697 // what we have to preserve is called the "frame header" (see comments in VM\eetwain.cpp)
2701 // -saved 'this' pointer and bool for synchronized methods
2703 // 4 slots for RBP + return address + RSI + RDI
2704 int preservedAreaSize = 4 * REGSIZE_BYTES;
2706 if (compiler->info.compFlags & CORINFO_FLG_SYNCH)
2708 if (!(compiler->info.compFlags & CORINFO_FLG_STATIC))
2709 preservedAreaSize += REGSIZE_BYTES;
2711 preservedAreaSize += 1; // bool for synchronized methods
2714 // Used to signal both that the method is compiled for EnC, and also the size of the block at the top of the
2716 gcInfoEncoder->SetSizeOfEditAndContinuePreservedArea(preservedAreaSize);
2719 #endif // _TARGET_ARM64_
2721 gcInfoEncoder->Build();
2723 // GC Encoder automatically puts the GC info in the right spot using ICorJitInfo::allocGCInfo(size_t)
2724 // let's save the values anyway for debugging purposes
2725 compiler->compInfoBlkAddr = gcInfoEncoder->Emit();
2726 compiler->compInfoBlkSize = 0; // not exposed by the GCEncoder interface
2729 //-------------------------------------------------------------------------------------------
2730 // genJumpKindsForTree: Determine the number and kinds of conditional branches
2731 // necessary to implement the given GT_CMP node
2734 // cmpTree - (input) The GenTree node that is used to set the Condition codes
2735 // - The GenTree Relop node that was used to set the Condition codes
2736 // jmpKind[2] - (output) One or two conditional branch instructions
2737 // jmpToTrueLabel[2] - (output) On Arm64 both branches will always branch to the true label
2740 // Sets the proper values into the array elements of jmpKind[] and jmpToTrueLabel[]
2743 // At least one conditional branch instruction will be returned.
2744 // Typically only one conditional branch is needed
2745 // and the second jmpKind[] value is set to EJ_NONE
2747 void CodeGen::genJumpKindsForTree(GenTreePtr cmpTree, emitJumpKind jmpKind[2], bool jmpToTrueLabel[2])
2749 // On ARM both branches will always branch to the true label
2750 jmpToTrueLabel[0] = true;
2751 jmpToTrueLabel[1] = true;
2753 // For integer comparisons just use genJumpKindForOper
2754 if (!varTypeIsFloating(cmpTree->gtOp.gtOp1))
2756 CompareKind compareKind = ((cmpTree->gtFlags & GTF_UNSIGNED) != 0) ? CK_UNSIGNED : CK_SIGNED;
2757 jmpKind[0] = genJumpKindForOper(cmpTree->gtOper, compareKind);
2758 jmpKind[1] = EJ_NONE;
2760 else // We have a Floating Point Compare operation
2762 assert(cmpTree->OperIsCompare());
2764 // For details on this mapping, see the ARM Condition Code table
2765 // at section A8.3 in the ARMv7 architecture manual or
2766 // at section C1.2.3 in the ARMV8 architecture manual.
2768 // We must check the GTF_RELOP_NAN_UN to find out
2769 // if we need to branch when we have a NaN operand.
2771 if ((cmpTree->gtFlags & GTF_RELOP_NAN_UN) != 0)
2773 // Must branch if we have an NaN, unordered
2774 switch (cmpTree->gtOper)
2777 jmpKind[0] = EJ_eq; // branch or set when equal (and no NaN's)
2778 jmpKind[1] = EJ_vs; // branch or set when we have a NaN
2782 jmpKind[0] = EJ_ne; // branch or set when not equal (or have NaN's)
2783 jmpKind[1] = EJ_NONE;
2787 jmpKind[0] = EJ_lt; // branch or set when less than (or have NaN's)
2788 jmpKind[1] = EJ_NONE;
2792 jmpKind[0] = EJ_le; // branch or set when less than or equal (or have NaN's)
2793 jmpKind[1] = EJ_NONE;
2797 jmpKind[0] = EJ_hi; // branch or set when greater than (or have NaN's)
2798 jmpKind[1] = EJ_NONE;
2802 jmpKind[0] = EJ_hs; // branch or set when greater than or equal (or have NaN's)
2803 jmpKind[1] = EJ_NONE;
2810 else // ((cmpTree->gtFlags & GTF_RELOP_NAN_UN) == 0)
2812 // Do not branch if we have an NaN, unordered
2813 switch (cmpTree->gtOper)
2816 jmpKind[0] = EJ_eq; // branch or set when equal (and no NaN's)
2817 jmpKind[1] = EJ_NONE;
2821 jmpKind[0] = EJ_gt; // branch or set when greater than (and no NaN's)
2822 jmpKind[1] = EJ_lo; // branch or set when less than (and no NaN's)
2826 jmpKind[0] = EJ_lo; // branch or set when less than (and no NaN's)
2827 jmpKind[1] = EJ_NONE;
2831 jmpKind[0] = EJ_ls; // branch or set when less than or equal (and no NaN's)
2832 jmpKind[1] = EJ_NONE;
2836 jmpKind[0] = EJ_gt; // branch or set when greater than (and no NaN's)
2837 jmpKind[1] = EJ_NONE;
2841 jmpKind[0] = EJ_ge; // branch or set when greater than or equal (and no NaN's)
2842 jmpKind[1] = EJ_NONE;
2852 //------------------------------------------------------------------------
2853 // genCodeForJumpTrue: Generates code for jmpTrue statement.
2856 // tree - The GT_JTRUE tree node.
2861 void CodeGen::genCodeForJumpTrue(GenTreePtr tree)
2863 GenTree* cmp = tree->gtOp.gtOp1;
2864 assert(cmp->OperIsCompare());
2865 assert(compiler->compCurBB->bbJumpKind == BBJ_COND);
2867 // Get the "kind" and type of the comparison. Note that whether it is an unsigned cmp
2868 // is governed by a flag NOT by the inherent type of the node
2869 emitJumpKind jumpKind[2];
2870 bool branchToTrueLabel[2];
2871 genJumpKindsForTree(cmp, jumpKind, branchToTrueLabel);
2872 assert(jumpKind[0] != EJ_NONE);
2874 // On ARM the branches will always branch to the true label
2875 assert(branchToTrueLabel[0]);
2876 inst_JMP(jumpKind[0], compiler->compCurBB->bbJumpDest);
2878 if (jumpKind[1] != EJ_NONE)
2880 // the second conditional branch always has to be to the true label
2881 assert(branchToTrueLabel[1]);
2882 inst_JMP(jumpKind[1], compiler->compCurBB->bbJumpDest);
2886 #if defined(_TARGET_ARM_)
2888 //------------------------------------------------------------------------
2889 // genCodeForJcc: Produce code for a GT_JCC node.
2894 void CodeGen::genCodeForJcc(GenTreeCC* tree)
2896 assert(compiler->compCurBB->bbJumpKind == BBJ_COND);
2898 CompareKind compareKind = ((tree->gtFlags & GTF_UNSIGNED) != 0) ? CK_UNSIGNED : CK_SIGNED;
2899 emitJumpKind jumpKind = genJumpKindForOper(tree->gtCondition, compareKind);
2901 inst_JMP(jumpKind, compiler->compCurBB->bbJumpDest);
2904 //------------------------------------------------------------------------
2905 // genCodeForSetcc: Generates code for a GT_SETCC node.
2908 // setcc - the GT_SETCC node
2911 // The condition represents an integer comparison. This code doesn't
2912 // have the necessary logic to deal with floating point comparisons,
2913 // in fact it doesn't even know if the comparison is integer or floating
2914 // point because SETCC nodes do not have any operands.
2917 void CodeGen::genCodeForSetcc(GenTreeCC* setcc)
2919 regNumber dstReg = setcc->gtRegNum;
2920 CompareKind compareKind = setcc->IsUnsigned() ? CK_UNSIGNED : CK_SIGNED;
2921 emitJumpKind jumpKind = genJumpKindForOper(setcc->gtCondition, compareKind);
2923 assert(genIsValidIntReg(dstReg));
2924 // Make sure nobody is setting GTF_RELOP_NAN_UN on this node as it is ignored.
2925 assert((setcc->gtFlags & GTF_RELOP_NAN_UN) == 0);
2927 // Emit code like that:
2937 BasicBlock* labelTrue = genCreateTempLabel();
2938 getEmitter()->emitIns_J(emitter::emitJumpKindToIns(jumpKind), labelTrue);
2940 getEmitter()->emitIns_R_I(INS_mov, emitActualTypeSize(setcc->TypeGet()), dstReg, 0);
2942 BasicBlock* labelNext = genCreateTempLabel();
2943 getEmitter()->emitIns_J(INS_b, labelNext);
2945 genDefineTempLabel(labelTrue);
2946 getEmitter()->emitIns_R_I(INS_mov, emitActualTypeSize(setcc->TypeGet()), dstReg, 1);
2947 genDefineTempLabel(labelNext);
2949 genProduceReg(setcc);
2952 #endif // defined(_TARGET_ARM_)
2954 //------------------------------------------------------------------------
2955 // genCodeForStoreBlk: Produce code for a GT_STORE_OBJ/GT_STORE_DYN_BLK/GT_STORE_BLK node.
2960 void CodeGen::genCodeForStoreBlk(GenTreeBlk* blkOp)
2962 assert(blkOp->OperIs(GT_STORE_OBJ, GT_STORE_DYN_BLK, GT_STORE_BLK));
2964 if (blkOp->OperIs(GT_STORE_OBJ) && blkOp->OperIsCopyBlkOp())
2966 assert(blkOp->AsObj()->gtGcPtrCount != 0);
2967 genCodeForCpObj(blkOp->AsObj());
2971 if (blkOp->gtBlkOpGcUnsafe)
2973 getEmitter()->emitDisableGC();
2975 bool isCopyBlk = blkOp->OperIsCopyBlkOp();
2977 switch (blkOp->gtBlkOpKind)
2979 case GenTreeBlk::BlkOpKindHelper:
2982 genCodeForCpBlk(blkOp);
2986 genCodeForInitBlk(blkOp);
2990 case GenTreeBlk::BlkOpKindUnroll:
2993 genCodeForCpBlkUnroll(blkOp);
2997 genCodeForInitBlkUnroll(blkOp);
3005 if (blkOp->gtBlkOpGcUnsafe)
3007 getEmitter()->emitEnableGC();
3011 //------------------------------------------------------------------------
3012 // genScaledAdd: A helper for genLeaInstruction.
3014 void CodeGen::genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale)
3016 emitter* emit = getEmitter();
3017 #if defined(_TARGET_ARM_)
3018 emit->emitIns_R_R_R_I(INS_add, attr, targetReg, baseReg, indexReg, scale, INS_FLAGS_DONT_CARE, INS_OPTS_LSL);
3019 #elif defined(_TARGET_ARM64_)
3020 emit->emitIns_R_R_R_I(INS_add, attr, targetReg, baseReg, indexReg, scale, INS_OPTS_LSL);
3024 //------------------------------------------------------------------------
3025 // genLeaInstruction: Produce code for a GT_LEA node.
3030 void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
3032 genConsumeOperands(lea);
3033 emitter* emit = getEmitter();
3034 emitAttr size = emitTypeSize(lea);
3035 unsigned offset = lea->gtOffset;
3037 // In ARM we can only load addresses of the form:
3039 // [Base + index*scale]
3041 // [Literal] (PC-Relative)
3043 // So for the case of a LEA node of the form [Base + Index*Scale + Offset] we will generate:
3044 // destReg = baseReg + indexReg * scale;
3045 // destReg = destReg + offset;
3047 // TODO-ARM64-CQ: The purpose of the GT_LEA node is to directly reflect a single target architecture
3048 // addressing mode instruction. Currently we're 'cheating' by producing one or more
3049 // instructions to generate the addressing mode so we need to modify lowering to
3050 // produce LEAs that are a 1:1 relationship to the ARM64 architecture.
3051 if (lea->Base() && lea->Index())
3053 GenTree* memBase = lea->Base();
3054 GenTree* index = lea->Index();
3055 unsigned offset = lea->gtOffset;
3059 assert(isPow2(lea->gtScale));
3060 BitScanForward(&lsl, lea->gtScale);
3066 regNumber tmpReg = lea->GetSingleTempReg();
3068 if (emitter::emitIns_valid_imm_for_add(offset))
3072 // Generate code to set tmpReg = base + index*scale
3073 genScaledAdd(size, tmpReg, memBase->gtRegNum, index->gtRegNum, lsl);
3077 // Generate code to set tmpReg = base + index
3078 emit->emitIns_R_R_R(INS_add, size, tmpReg, memBase->gtRegNum, index->gtRegNum);
3081 // Then compute target reg from [tmpReg + offset]
3082 emit->emitIns_R_R_I(INS_add, size, lea->gtRegNum, tmpReg, offset);
3084 else // large offset
3086 // First load/store tmpReg with the large offset constant
3087 instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, offset);
3088 // Then add the base register
3090 emit->emitIns_R_R_R(INS_add, size, tmpReg, tmpReg, memBase->gtRegNum);
3092 noway_assert(tmpReg != index->gtRegNum);
3094 // Then compute target reg from [tmpReg + index*scale]
3095 genScaledAdd(size, lea->gtRegNum, tmpReg, index->gtRegNum, lsl);
3102 // Then compute target reg from [base + index*scale]
3103 genScaledAdd(size, lea->gtRegNum, memBase->gtRegNum, index->gtRegNum, lsl);
3107 // Then compute target reg from [base + index]
3108 emit->emitIns_R_R_R(INS_add, size, lea->gtRegNum, memBase->gtRegNum, index->gtRegNum);
3112 else if (lea->Base())
3114 GenTree* memBase = lea->Base();
3116 if (emitter::emitIns_valid_imm_for_add(offset))
3120 // Then compute target reg from [memBase + offset]
3121 emit->emitIns_R_R_I(INS_add, size, lea->gtRegNum, memBase->gtRegNum, offset);
3123 else // offset is zero
3125 emit->emitIns_R_R(INS_mov, size, lea->gtRegNum, memBase->gtRegNum);
3130 // We require a tmpReg to hold the offset
3131 regNumber tmpReg = lea->GetSingleTempReg();
3133 // First load tmpReg with the large offset constant
3134 instGen_Set_Reg_To_Imm(EA_PTRSIZE, tmpReg, offset);
3136 // Then compute target reg from [memBase + tmpReg]
3137 emit->emitIns_R_R_R(INS_add, size, lea->gtRegNum, memBase->gtRegNum, tmpReg);
3140 else if (lea->Index())
3142 // If we encounter a GT_LEA node without a base it means it came out
3143 // when attempting to optimize an arbitrary arithmetic expression during lower.
3144 // This is currently disabled in ARM64 since we need to adjust lower to account
3145 // for the simpler instructions ARM64 supports.
3146 // TODO-ARM64-CQ: Fix this and let LEA optimize arithmetic trees too.
3147 assert(!"We shouldn't see a baseless address computation during CodeGen for ARM64");
3153 //------------------------------------------------------------------------
3154 // isStructReturn: Returns whether the 'treeNode' is returning a struct.
3157 // treeNode - The tree node to evaluate whether is a struct return.
3160 // Returns true if the 'treeNode" is a GT_RETURN node of type struct.
3161 // Otherwise returns false.
3163 bool CodeGen::isStructReturn(GenTreePtr treeNode)
3165 // This method could be called for 'treeNode' of GT_RET_FILT or GT_RETURN.
3166 // For the GT_RET_FILT, the return is always
3167 // a bool or a void, for the end of a finally block.
3168 noway_assert(treeNode->OperGet() == GT_RETURN || treeNode->OperGet() == GT_RETFILT);
3170 return varTypeIsStruct(treeNode);
3173 //------------------------------------------------------------------------
3174 // genStructReturn: Generates code for returning a struct.
3177 // treeNode - The GT_RETURN tree node.
3183 // op1 of GT_RETURN node is either GT_LCL_VAR or multi-reg GT_CALL
3184 void CodeGen::genStructReturn(GenTreePtr treeNode)
3186 assert(treeNode->OperGet() == GT_RETURN);
3187 assert(isStructReturn(treeNode));
3188 GenTreePtr op1 = treeNode->gtGetOp1();
3190 if (op1->OperGet() == GT_LCL_VAR)
3192 GenTreeLclVarCommon* lclVar = op1->AsLclVarCommon();
3193 LclVarDsc* varDsc = &(compiler->lvaTable[lclVar->gtLclNum]);
3194 var_types lclType = genActualType(varDsc->TypeGet());
3196 // Currently only multireg TYP_STRUCT types such as HFA's(ARM32, ARM64) and 16-byte structs(ARM64) are supported
3197 // In the future we could have FEATURE_SIMD types like TYP_SIMD16
3198 assert(lclType == TYP_STRUCT);
3199 assert(varDsc->lvIsMultiRegRet);
3201 ReturnTypeDesc retTypeDesc;
3204 retTypeDesc.InitializeStructReturnType(compiler, varDsc->lvVerTypeInfo.GetClassHandle());
3205 regCount = retTypeDesc.GetReturnRegCount();
3207 assert(regCount >= 2);
3208 assert(op1->isContained());
3210 // Copy var on stack into ABI return registers
3211 // TODO: It could be optimized by reducing two float loading to one double
3213 for (unsigned i = 0; i < regCount; ++i)
3215 var_types type = retTypeDesc.GetReturnRegType(i);
3216 regNumber reg = retTypeDesc.GetABIReturnReg(i);
3217 getEmitter()->emitIns_R_S(ins_Load(type), emitTypeSize(type), reg, lclVar->gtLclNum, offset);
3218 offset += genTypeSize(type);
3221 else // op1 must be multi-reg GT_CALL
3224 NYI_ARM("struct return from multi-reg GT_CALL");
3226 assert(op1->IsMultiRegCall() || op1->IsCopyOrReloadOfMultiRegCall());
3228 genConsumeRegs(op1);
3230 GenTree* actualOp1 = op1->gtSkipReloadOrCopy();
3231 GenTreeCall* call = actualOp1->AsCall();
3233 ReturnTypeDesc* pRetTypeDesc;
3235 unsigned matchingCount = 0;
3237 pRetTypeDesc = call->GetReturnTypeDesc();
3238 regCount = pRetTypeDesc->GetReturnRegCount();
3240 var_types regType[MAX_RET_REG_COUNT];
3241 regNumber returnReg[MAX_RET_REG_COUNT];
3242 regNumber allocatedReg[MAX_RET_REG_COUNT];
3243 regMaskTP srcRegsMask = 0;
3244 regMaskTP dstRegsMask = 0;
3245 bool needToShuffleRegs = false; // Set to true if we have to move any registers
3247 for (unsigned i = 0; i < regCount; ++i)
3249 regType[i] = pRetTypeDesc->GetReturnRegType(i);
3250 returnReg[i] = pRetTypeDesc->GetABIReturnReg(i);
3252 regNumber reloadReg = REG_NA;
3253 if (op1->IsCopyOrReload())
3255 // GT_COPY/GT_RELOAD will have valid reg for those positions
3256 // that need to be copied or reloaded.
3257 reloadReg = op1->AsCopyOrReload()->GetRegNumByIdx(i);
3260 if (reloadReg != REG_NA)
3262 allocatedReg[i] = reloadReg;
3266 allocatedReg[i] = call->GetRegNumByIdx(i);
3269 if (returnReg[i] == allocatedReg[i])
3273 else // We need to move this value
3275 // We want to move the value from allocatedReg[i] into returnReg[i]
3276 // so record these two registers in the src and dst masks
3278 srcRegsMask |= genRegMask(allocatedReg[i]);
3279 dstRegsMask |= genRegMask(returnReg[i]);
3281 needToShuffleRegs = true;
3285 if (needToShuffleRegs)
3287 assert(matchingCount < regCount);
3289 unsigned remainingRegCount = regCount - matchingCount;
3290 regMaskTP extraRegMask = treeNode->gtRsvdRegs;
3292 while (remainingRegCount > 0)
3294 // set 'available' to the 'dst' registers that are not currently holding 'src' registers
3296 regMaskTP availableMask = dstRegsMask & ~srcRegsMask;
3301 var_types curType = TYP_UNKNOWN;
3302 regNumber freeUpReg = REG_NA;
3304 if (availableMask == 0)
3306 // Circular register dependencies
3307 // So just free up the lowest register in dstRegsMask by moving it to the 'extra' register
3309 assert(dstRegsMask == srcRegsMask); // this has to be true for us to reach here
3310 assert(extraRegMask != 0); // we require an 'extra' register
3311 assert((extraRegMask & ~dstRegsMask) != 0); // it can't be part of dstRegsMask
3313 availableMask = extraRegMask & ~dstRegsMask;
3315 regMaskTP srcMask = genFindLowestBit(srcRegsMask);
3316 freeUpReg = genRegNumFromMask(srcMask);
3319 dstMask = genFindLowestBit(availableMask);
3320 dstReg = genRegNumFromMask(dstMask);
3323 if (freeUpReg != REG_NA)
3325 // We will free up the srcReg by moving it to dstReg which is an extra register
3329 // Find the 'srcReg' and set 'curType', change allocatedReg[] to dstReg
3330 // and add the new register mask bit to srcRegsMask
3332 for (unsigned i = 0; i < regCount; ++i)
3334 if (allocatedReg[i] == srcReg)
3336 curType = regType[i];
3337 allocatedReg[i] = dstReg;
3338 srcRegsMask |= genRegMask(dstReg);
3342 else // The normal case
3344 // Find the 'srcReg' and set 'curType'
3346 for (unsigned i = 0; i < regCount; ++i)
3348 if (returnReg[i] == dstReg)
3350 srcReg = allocatedReg[i];
3351 curType = regType[i];
3354 // After we perform this move we will have one less registers to setup
3355 remainingRegCount--;
3357 assert(curType != TYP_UNKNOWN);
3359 inst_RV_RV(ins_Copy(curType), dstReg, srcReg, curType);
3361 // Clear the appropriate bits in srcRegsMask and dstRegsMask
3362 srcRegsMask &= ~genRegMask(srcReg);
3363 dstRegsMask &= ~genRegMask(dstReg);
3365 } // while (remainingRegCount > 0)
3367 } // (needToShuffleRegs)
3369 } // op1 must be multi-reg GT_CALL
3371 #endif // _TARGET_ARMARCH_
3373 #endif // !LEGACY_BACKEND