src/intel_module.c

   1 /*
   2  * Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  * Copyright © 2010 Intel Corporation
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "xf86.h"
  32 #include "xf86_OSproc.h"
  33 #include "xf86cmap.h"
  34
  35 #include "common.h"
  36 #include "intel.h"
  37 #include "intel_driver.h"
  38 #include "legacy/legacy.h"
  39
  40 #include <xf86drmMode.h>
  41
  42 static const struct intel_device_info intel_i81x_info = {
  43         .gen = 10,
  44 };
  45
  46 static const struct intel_device_info intel_i8xx_info = {
  47         .gen = 20,
  48 };
  49
  50 static const struct intel_device_info intel_i915_info = {
  51         .gen = 30,
  52 };
  53
  54 static const struct intel_device_info intel_g33_info = {
  55         .gen = 33,
  56 };
  57
  58 static const struct intel_device_info intel_i965_info = {
  59         .gen = 40,
  60 };
  61
  62 static const struct intel_device_info intel_g4x_info = {
  63         .gen = 45,
  64 };
  65
  66 static const struct intel_device_info intel_ironlake_info = {
  67         .gen = 50,
  68 };
  69
  70 static const struct intel_device_info intel_sandybridge_info = {
  71         .gen = 60,
  72 };
  73
  74 static const SymTabRec _intel_chipsets[] = {
  75     {PCI_CHIP_I810,             "i810"},
  76     {PCI_CHIP_I810_DC100,       "i810-dc100"},
  77     {PCI_CHIP_I810_E,           "i810e"},
  78     {PCI_CHIP_I815,             "i815"},
  79     {PCI_CHIP_I830_M,           "i830M"},
  80     {PCI_CHIP_845_G,            "845G"},
  81     {PCI_CHIP_I854,             "854"},
  82     {PCI_CHIP_I855_GM,          "852GM/855GM"},
  83     {PCI_CHIP_I865_G,           "865G"},
  84     {PCI_CHIP_I915_G,           "915G"},
  85     {PCI_CHIP_E7221_G,          "E7221 (i915)"},
  86     {PCI_CHIP_I915_GM,          "915GM"},
  87     {PCI_CHIP_I945_G,           "945G"},
  88     {PCI_CHIP_I945_GM,          "945GM"},
  89     {PCI_CHIP_I945_GME,         "945GME"},
  90     {PCI_CHIP_PINEVIEW_M,       "Pineview GM"},
  91     {PCI_CHIP_PINEVIEW_G,       "Pineview G"},
  92     {PCI_CHIP_I965_G,           "965G"},
  93     {PCI_CHIP_G35_G,            "G35"},
  94     {PCI_CHIP_I965_Q,           "965Q"},
  95     {PCI_CHIP_I946_GZ,          "946GZ"},
  96     {PCI_CHIP_I965_GM,          "965GM"},
  97     {PCI_CHIP_I965_GME,         "965GME/GLE"},
  98     {PCI_CHIP_G33_G,            "G33"},
  99     {PCI_CHIP_Q35_G,            "Q35"},
 100     {PCI_CHIP_Q33_G,            "Q33"},
 101     {PCI_CHIP_GM45_GM,          "GM45"},
 102     {PCI_CHIP_G45_E_G,          "4 Series"},
 103     {PCI_CHIP_G45_G,            "G45/G43"},
 104     {PCI_CHIP_Q45_G,            "Q45/Q43"},
 105     {PCI_CHIP_G41_G,            "G41"},
 106     {PCI_CHIP_B43_G,            "B43"},
 107     {PCI_CHIP_B43_G1,           "B43"},
 108     {PCI_CHIP_IRONLAKE_D_G,             "Clarkdale"},
 109     {PCI_CHIP_IRONLAKE_M_G,             "Arrandale"},
 110     {PCI_CHIP_SANDYBRIDGE_GT1,  "Sandybridge" },
 111     {PCI_CHIP_SANDYBRIDGE_GT2,  "Sandybridge" },
 112     {PCI_CHIP_SANDYBRIDGE_GT2_PLUS,     "Sandybridge" },
 113     {PCI_CHIP_SANDYBRIDGE_M_GT1,        "Sandybridge" },
 114     {PCI_CHIP_SANDYBRIDGE_M_GT2,        "Sandybridge" },
 115     {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,   "Sandybridge" },
 116     {PCI_CHIP_SANDYBRIDGE_S_GT, "Sandybridge" },
 117     {-1,                                NULL}
 118 };
 119 SymTabRec *intel_chipsets = (SymTabRec *) _intel_chipsets;
 120
 121 #define INTEL_DEVICE_MATCH(d,i) \
 122 { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
 123
 124 static const struct pci_id_match intel_device_match[] = {
 125     INTEL_DEVICE_MATCH (PCI_CHIP_I810, 0 ),
 126     INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, 0 ),
 127     INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, 0 ),
 128     INTEL_DEVICE_MATCH (PCI_CHIP_I815, 0 ),
 129     INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, 0 ),
 130     INTEL_DEVICE_MATCH (PCI_CHIP_845_G, 0 ),
 131     INTEL_DEVICE_MATCH (PCI_CHIP_I854, 0 ),
 132     INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, 0 ),
 133     INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, 0 ),
 134     INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, 0 ),
 135     INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, 0 ),
 136     INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, 0 ),
 137     INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
 138     INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
 139     INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
 140     INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, 0 ),
 141     INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, 0 ),
 142     INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
 143     INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
 144     INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
 145     INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, 0 ),
 146     INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, 0 ),
 147     INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, 0 ),
 148     INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, 0 ),
 149     INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
 150     INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
 151     INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
 152     INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, 0 ),
 153     INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
 154     INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
 155     INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
 156     INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
 157     INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, 0 ),
 158     INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, 0 ),
 159     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, 0 ),
 160     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, 0 ),
 161     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, 0 ),
 162     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, 0 ),
 163     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, 0 ),
 164     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, 0 ),
 165     INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, 0 ),
 166     { 0, 0, 0 },
 167 };
 168
 169 static PciChipsets intel_pci_chipsets[] = {
 170     {PCI_CHIP_I810,             PCI_CHIP_I810,          NULL},
 171     {PCI_CHIP_I810_DC100,       PCI_CHIP_I810_DC100,    NULL},
 172     {PCI_CHIP_I810_E,           PCI_CHIP_I810_E,        NULL},
 173     {PCI_CHIP_I815,             PCI_CHIP_I815,          NULL},
 174     {PCI_CHIP_I830_M,           PCI_CHIP_I830_M,        NULL},
 175     {PCI_CHIP_845_G,            PCI_CHIP_845_G,         NULL},
 176     {PCI_CHIP_I854,             PCI_CHIP_I854,          NULL},
 177     {PCI_CHIP_I855_GM,          PCI_CHIP_I855_GM,       NULL},
 178     {PCI_CHIP_I865_G,           PCI_CHIP_I865_G,        NULL},
 179     {PCI_CHIP_I915_G,           PCI_CHIP_I915_G,        NULL},
 180     {PCI_CHIP_E7221_G,          PCI_CHIP_E7221_G,       NULL},
 181     {PCI_CHIP_I915_GM,          PCI_CHIP_I915_GM,       NULL},
 182     {PCI_CHIP_I945_G,           PCI_CHIP_I945_G,        NULL},
 183     {PCI_CHIP_I945_GM,          PCI_CHIP_I945_GM,       NULL},
 184     {PCI_CHIP_I945_GME,         PCI_CHIP_I945_GME,      NULL},
 185     {PCI_CHIP_PINEVIEW_M,       PCI_CHIP_PINEVIEW_M,    NULL},
 186     {PCI_CHIP_PINEVIEW_G,       PCI_CHIP_PINEVIEW_G,            NULL},
 187     {PCI_CHIP_I965_G,           PCI_CHIP_I965_G,        NULL},
 188     {PCI_CHIP_G35_G,            PCI_CHIP_G35_G,         NULL},
 189     {PCI_CHIP_I965_Q,           PCI_CHIP_I965_Q,        NULL},
 190     {PCI_CHIP_I946_GZ,          PCI_CHIP_I946_GZ,       NULL},
 191     {PCI_CHIP_I965_GM,          PCI_CHIP_I965_GM,       NULL},
 192     {PCI_CHIP_I965_GME,         PCI_CHIP_I965_GME,      NULL},
 193     {PCI_CHIP_G33_G,            PCI_CHIP_G33_G,         NULL},
 194     {PCI_CHIP_Q35_G,            PCI_CHIP_Q35_G,         NULL},
 195     {PCI_CHIP_Q33_G,            PCI_CHIP_Q33_G,         NULL},
 196     {PCI_CHIP_GM45_GM,          PCI_CHIP_GM45_GM,       NULL},
 197     {PCI_CHIP_G45_E_G,          PCI_CHIP_G45_E_G,       NULL},
 198     {PCI_CHIP_G45_G,            PCI_CHIP_G45_G,         NULL},
 199     {PCI_CHIP_Q45_G,            PCI_CHIP_Q45_G,         NULL},
 200     {PCI_CHIP_G41_G,            PCI_CHIP_G41_G,         NULL},
 201     {PCI_CHIP_B43_G,            PCI_CHIP_B43_G,         NULL},
 202     {PCI_CHIP_IRONLAKE_D_G,     PCI_CHIP_IRONLAKE_D_G,  NULL},
 203     {PCI_CHIP_IRONLAKE_M_G,     PCI_CHIP_IRONLAKE_M_G,  NULL},
 204     {PCI_CHIP_SANDYBRIDGE_GT1,  PCI_CHIP_SANDYBRIDGE_GT1,       NULL},
 205     {PCI_CHIP_SANDYBRIDGE_GT2,  PCI_CHIP_SANDYBRIDGE_GT2,       NULL},
 206     {PCI_CHIP_SANDYBRIDGE_GT2_PLUS,     PCI_CHIP_SANDYBRIDGE_GT2_PLUS,  NULL},
 207     {PCI_CHIP_SANDYBRIDGE_M_GT1,        PCI_CHIP_SANDYBRIDGE_M_GT1,     NULL},
 208     {PCI_CHIP_SANDYBRIDGE_M_GT2,        PCI_CHIP_SANDYBRIDGE_M_GT2,     NULL},
 209     {PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS,   PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, NULL},
 210     {PCI_CHIP_SANDYBRIDGE_S_GT,         PCI_CHIP_SANDYBRIDGE_S_GT,      NULL},
 211     {-1,                                -1, NULL }
 212 };
 213
 214 void intel_detect_chipset(ScrnInfoPtr scrn,
 215                           struct pci_device *pci,
 216                           struct intel_chipset *chipset)
 217 {
 218     uint32_t capid;
 219
 220     switch (DEVICE_ID(pci)) {
 221     case PCI_CHIP_I810:
 222         chipset->name = "i810";
 223         chipset->info = &intel_i81x_info;
 224         break;
 225     case PCI_CHIP_I810_DC100:
 226         chipset->name = "i810-dc100";
 227         chipset->info = &intel_i81x_info;
 228         break;
 229     case PCI_CHIP_I810_E:
 230         chipset->name = "i810e";
 231         chipset->info = &intel_i81x_info;
 232         break;
 233     case PCI_CHIP_I815:
 234         chipset->name = "i815";
 235         chipset->info = &intel_i81x_info;
 236         break;
 237     case PCI_CHIP_I830_M:
 238         chipset->name = "830M";
 239         chipset->info = &intel_i8xx_info;
 240         break;
 241     case PCI_CHIP_845_G:
 242         chipset->name = "845G";
 243         chipset->info = &intel_i8xx_info;
 244         break;
 245     case PCI_CHIP_I854:
 246         chipset->name = "854";
 247         chipset->info = &intel_i8xx_info;
 248         break;
 249     case PCI_CHIP_I855_GM:
 250         /* Check capid register to find the chipset variant */
 251         pci_device_cfg_read_u32(pci, &capid, I85X_CAPID);
 252         chipset->variant =
 253             (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
 254         switch (chipset->variant) {
 255         case I855_GM:
 256             chipset->name = "855GM";
 257             break;
 258         case I855_GME:
 259             chipset->name = "855GME";
 260             break;
 261         case I852_GM:
 262             chipset->name = "852GM";
 263             break;
 264         case I852_GME:
 265             chipset->name = "852GME";
 266             break;
 267         default:
 268             xf86DrvMsg(scrn->scrnIndex, X_INFO,
 269                        "Unknown 852GM/855GM variant: 0x%x)\n",
 270                        chipset->variant);
 271             chipset->name = "852GM/855GM (unknown variant)";
 272             break;
 273         }
 274         chipset->info = &intel_i8xx_info;
 275         break;
 276     case PCI_CHIP_I865_G:
 277         chipset->name = "865G";
 278         chipset->info = &intel_i8xx_info;
 279         break;
 280     case PCI_CHIP_I915_G:
 281         chipset->name = "915G";
 282         chipset->info = &intel_i915_info;
 283         break;
 284     case PCI_CHIP_E7221_G:
 285         chipset->name = "E7221 (i915)";
 286         chipset->info = &intel_i915_info;
 287         break;
 288     case PCI_CHIP_I915_GM:
 289         chipset->name = "915GM";
 290         chipset->info = &intel_i915_info;
 291         break;
 292     case PCI_CHIP_I945_G:
 293         chipset->name = "945G";
 294         chipset->info = &intel_i915_info;
 295         break;
 296     case PCI_CHIP_I945_GM:
 297         chipset->name = "945GM";
 298         chipset->info = &intel_i915_info;
 299         break;
 300     case PCI_CHIP_I945_GME:
 301         chipset->name = "945GME";
 302         chipset->info = &intel_i915_info;
 303         break;
 304     case PCI_CHIP_PINEVIEW_M:
 305         chipset->name = "Pineview GM";
 306         chipset->info = &intel_g33_info;
 307         break;
 308     case PCI_CHIP_PINEVIEW_G:
 309         chipset->name = "Pineview G";
 310         chipset->info = &intel_g33_info;
 311         break;
 312     case PCI_CHIP_I965_G:
 313         chipset->name = "965G";
 314         chipset->info = &intel_i965_info;
 315         break;
 316     case PCI_CHIP_G35_G:
 317         chipset->name = "G35";
 318         chipset->info = &intel_i965_info;
 319         break;
 320     case PCI_CHIP_I965_Q:
 321         chipset->name = "965Q";
 322         chipset->info = &intel_i965_info;
 323         break;
 324     case PCI_CHIP_I946_GZ:
 325         chipset->name = "946GZ";
 326         chipset->info = &intel_i965_info;
 327         break;
 328     case PCI_CHIP_I965_GM:
 329         chipset->name = "965GM";
 330         chipset->info = &intel_i965_info;
 331         break;
 332     case PCI_CHIP_I965_GME:
 333         chipset->name = "965GME/GLE";
 334         chipset->info = &intel_i965_info;
 335         break;
 336     case PCI_CHIP_G33_G:
 337         chipset->name = "G33";
 338         chipset->info = &intel_g33_info;
 339         break;
 340     case PCI_CHIP_Q35_G:
 341         chipset->name = "Q35";
 342         chipset->info = &intel_g33_info;
 343         break;
 344     case PCI_CHIP_Q33_G:
 345         chipset->name = "Q33";
 346         chipset->info = &intel_g33_info;
 347         break;
 348     case PCI_CHIP_GM45_GM:
 349         chipset->name = "GM45";
 350         chipset->info = &intel_g4x_info;
 351         break;
 352     case PCI_CHIP_G45_E_G:
 353         chipset->name = "4 Series";
 354         chipset->info = &intel_g4x_info;
 355         break;
 356     case PCI_CHIP_G45_G:
 357         chipset->name = "G45/G43";
 358         chipset->info = &intel_g4x_info;
 359         break;
 360     case PCI_CHIP_Q45_G:
 361         chipset->name = "Q45/Q43";
 362         chipset->info = &intel_g4x_info;
 363         break;
 364     case PCI_CHIP_G41_G:
 365         chipset->name = "G41";
 366         chipset->info = &intel_g4x_info;
 367         break;
 368     case PCI_CHIP_B43_G:
 369         chipset->name = "B43";
 370         chipset->info = &intel_g4x_info;
 371         break;
 372     case PCI_CHIP_IRONLAKE_D_G:
 373         chipset->name = "Clarkdale";
 374         chipset->info = &intel_ironlake_info;
 375         break;
 376     case PCI_CHIP_IRONLAKE_M_G:
 377         chipset->name = "Arrandale";
 378         chipset->info = &intel_ironlake_info;
 379         break;
 380     case PCI_CHIP_SANDYBRIDGE_GT1:
 381     case PCI_CHIP_SANDYBRIDGE_GT2:
 382     case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
 383     case PCI_CHIP_SANDYBRIDGE_M_GT1:
 384     case PCI_CHIP_SANDYBRIDGE_M_GT2:
 385     case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
 386     case PCI_CHIP_SANDYBRIDGE_S_GT:
 387         chipset->name = "Sandybridge";
 388         chipset->info = &intel_sandybridge_info;
 389         break;
 390     default:
 391         chipset->name = "unknown chipset";
 392         break;
 393     }
 394
 395     xf86DrvMsg(scrn->scrnIndex, X_INFO,
 396                "Integrated Graphics Chipset: Intel(R) %s\n", chipset->name);
 397 }
 398
 399 /*
 400  * intel_identify --
 401  *
 402  * Returns the string name for the driver based on the chipset.
 403  *
 404  */
 405 static void intel_identify(int flags)
 406 {
 407     xf86PrintChipsets(INTEL_NAME,
 408                       "Driver for Intel Integrated Graphics Chipsets",
 409                       intel_chipsets);
 410 }
 411
 412 static Bool intel_driver_func(ScrnInfoPtr pScrn,
 413                               xorgDriverFuncOp op,
 414                               pointer ptr)
 415 {
 416     xorgHWFlags *flag;
 417
 418     switch (op) {
 419     case GET_REQUIRED_HW_INTERFACES:
 420         flag = (CARD32*)ptr;
 421 #ifdef KMS_ONLY
 422         (*flag) = 0;
 423 #else
 424         (*flag) = HW_IO | HW_MMIO;
 425 #endif
 426         return TRUE;
 427     default:
 428         /* Unknown or deprecated function */
 429         return FALSE;
 430     }
 431 }
 432
 433 static Bool has_kernel_mode_setting(struct pci_device *dev)
 434 {
 435         char id[20];
 436         int ret;
 437
 438         snprintf(id, sizeof(id),
 439                  "pci:%04x:%02x:%02x.%d",
 440                  dev->domain, dev->bus, dev->dev, dev->func);
 441
 442         ret = drmCheckModesettingSupported(id);
 443         if (ret) {
 444                 if (xf86LoadKernelModule("i915"))
 445                         ret = drmCheckModesettingSupported(id);
 446         }
 447         /* Be nice to the user and load fbcon too */
 448         if (!ret)
 449                 (void)xf86LoadKernelModule("fbcon");
 450
 451         return ret == 0;
 452 }
 453
 454 /*
 455  * intel_pci_probe --
 456  *
 457  * Look through the PCI bus to find cards that are intel boards.
 458  * Setup the dispatch table for the rest of the driver functions.
 459  *
 460  */
 461 static Bool intel_pci_probe (DriverPtr          driver,
 462                              int                entity_num,
 463                              struct pci_device  *device,
 464                              intptr_t           match_data)
 465 {
 466     ScrnInfoPtr scrn;
 467
 468     if (!has_kernel_mode_setting(device)) {
 469 #if KMS_ONLY
 470             return FALSE;
 471 #else
 472             switch (DEVICE_ID(device)) {
 473             case PCI_CHIP_I810:
 474             case PCI_CHIP_I810_DC100:
 475             case PCI_CHIP_I810_E:
 476             case PCI_CHIP_I815:
 477                     break;
 478             default:
 479                     return FALSE;
 480             }
 481 #endif
 482     }
 483
 484     scrn = xf86ConfigPciEntity(NULL, 0, entity_num, intel_pci_chipsets,
 485                                NULL, NULL, NULL, NULL, NULL);
 486     if (scrn != NULL) {
 487         scrn->driverVersion = INTEL_VERSION;
 488         scrn->driverName = INTEL_DRIVER_NAME;
 489         scrn->name = INTEL_NAME;
 490         scrn->Probe = NULL;
 491
 492 #if KMS_ONLY
 493         intel_init_scrn(scrn);
 494 #else
 495         switch (DEVICE_ID(device)) {
 496         case PCI_CHIP_I810:
 497         case PCI_CHIP_I810_DC100:
 498         case PCI_CHIP_I810_E:
 499         case PCI_CHIP_I815:
 500             lg_i810_init(scrn);
 501             break;
 502
 503         default:
 504             intel_init_scrn(scrn);
 505             break;
 506         }
 507 #endif
 508     }
 509     return scrn != NULL;
 510 }
 511
 512 #ifdef XFree86LOADER
 513
 514 static MODULESETUPPROTO(intel_setup);
 515
 516 static XF86ModuleVersionInfo intel_version = {
 517     "intel",
 518     MODULEVENDORSTRING,
 519     MODINFOSTRING1,
 520     MODINFOSTRING2,
 521     XORG_VERSION_CURRENT,
 522     INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH,
 523     ABI_CLASS_VIDEODRV,
 524     ABI_VIDEODRV_VERSION,
 525     MOD_CLASS_VIDEODRV,
 526     {0, 0, 0, 0}
 527 };
 528
 529 static const OptionInfoRec *
 530 intel_available_options(int chipid, int busid)
 531 {
 532 #if KMS_ONLY
 533         return intel_uxa_available_options(chipid, busid);
 534 #else
 535         switch (chipid) {
 536         case PCI_CHIP_I810:
 537         case PCI_CHIP_I810_DC100:
 538         case PCI_CHIP_I810_E:
 539         case PCI_CHIP_I815:
 540                 return lg_i810_available_options(chipid, busid);
 541
 542         default:
 543                 return intel_uxa_available_options(chipid, busid);
 544         }
 545 #endif
 546 }
 547
 548 static DriverRec intel = {
 549     INTEL_VERSION,
 550     INTEL_DRIVER_NAME,
 551     intel_identify,
 552     NULL,
 553     intel_available_options,
 554     NULL,
 555     0,
 556     intel_driver_func,
 557     intel_device_match,
 558     intel_pci_probe
 559 };
 560
 561 static pointer intel_setup(pointer module,
 562                            pointer opts,
 563                            int *errmaj,
 564                            int *errmin)
 565 {
 566     static Bool setupDone = 0;
 567
 568     /* This module should be loaded only once, but check to be sure.
 569     */
 570     if (!setupDone) {
 571         setupDone = 1;
 572         xf86AddDriver(&intel, module, HaveDriverFuncs);
 573
 574         /*
 575          * The return value must be non-NULL on success even though there
 576          * is no TearDownProc.
 577          */
 578         return (pointer) 1;
 579     } else {
 580         if (errmaj)
 581             *errmaj = LDR_ONCEONLY;
 582         return NULL;
 583     }
 584 }
 585
 586 _X_EXPORT XF86ModuleData intelModuleData = { &intel_version, intel_setup, NULL };
 587 #endif