2 * Author: Brendan Le Foll <brendan.le.foll@intel.com>
3 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
4 * Copyright (c) 2014 Intel Corporation.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice shall be
15 * included in all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
31 #include "intel_galileo_rev_g.h"
34 #define SYSFS_CLASS_GPIO "/sys/class/gpio"
36 #define UIO_PATH "/dev/uio0"
38 static uint8_t *mmap_reg = NULL;
39 static int mmap_fd = 0;
40 static int mmap_size = 0x1000;
41 static unsigned int mmap_count = 0;
43 static unsigned int pullup_map[] = {33,29,35,17,37,19,21,39,41,23,27,25,43,31,49,51,53,55,57,59};
46 mraa_intel_galileo_gen2_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
48 if (dev->phy_pin >= 0) {
49 int pin = dev->phy_pin;
50 if (plat->pins[pin].gpio.complex_cap.complex_pin != 1)
53 if (plat->pins[pin].gpio.complex_cap.output_en == 1) {
54 mraa_gpio_context output_e;
55 output_e = mraa_gpio_init_raw(plat->pins[pin].gpio.output_enable);
56 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
57 return MRAA_ERROR_INVALID_RESOURCE;
59 if (dir == MRAA_GPIO_OUT)
61 if (mraa_gpio_write(output_e, output_val) != MRAA_SUCCESS)
62 return MRAA_ERROR_INVALID_RESOURCE;
69 mraa_intel_galileo_gen2_i2c_init_pre(unsigned int bus)
71 mraa_gpio_context io18;
73 io18 = mraa_gpio_init_raw(57);
74 status = status + mraa_gpio_dir(io18, MRAA_GPIO_IN);
75 status = status + mraa_gpio_mode(io18, MRAA_GPIO_HIZ);
77 mraa_gpio_context io19;
78 io19 = mraa_gpio_init_raw(59);
79 status = status + mraa_gpio_dir(io19, MRAA_GPIO_IN);
80 status = status + mraa_gpio_mode(io19, MRAA_GPIO_HIZ);
83 return MRAA_ERROR_UNSPECIFIED;
88 mraa_intel_galileo_gen2_pwm_period_replace(mraa_pwm_context dev, int period)
91 snprintf(bu,MAX_SIZE ,"/sys/class/pwm/pwmchip%d/device/pwm_period", dev->chipid);
93 int period_f = open(bu, O_RDWR);
95 syslog(LOG_ERR, "galileo2: Failed to open period for writing!");
96 return MRAA_ERROR_INVALID_RESOURCE;
99 int length = snprintf(out, MAX_SIZE, "%d", period);
100 if (write(period_f, out, length*sizeof(char)) == -1) {
102 return MRAA_ERROR_INVALID_RESOURCE;
110 mraa_intel_galileo_gen2_gpio_mode_replace(mraa_gpio_context dev, gpio_mode_t mode)
112 if (dev->value_fp != -1) {
113 close(dev->value_fp);
117 mraa_gpio_context pullup_e;
118 pullup_e = mraa_gpio_init_raw(pullup_map[dev->phy_pin]);
119 mraa_result_t sta = mraa_gpio_dir(pullup_e, MRAA_GPIO_IN);
120 if (sta != MRAA_SUCCESS) {
121 syslog(LOG_ERR, "galileo2: Failed to set gpio pullup");
122 return MRAA_ERROR_INVALID_RESOURCE;
125 char filepath[MAX_SIZE];
126 snprintf(filepath, MAX_SIZE, SYSFS_CLASS_GPIO "/gpio%d/drive", pullup_map[dev->phy_pin]);
128 int drive = open(filepath, O_WRONLY);
130 syslog(LOG_ERR, "galileo2: Failed to open drive for writing");
131 return MRAA_ERROR_INVALID_RESOURCE;
138 case MRAA_GPIO_STRONG:
139 length = snprintf(bu, sizeof(bu), "hiz");
141 case MRAA_GPIO_PULLUP:
142 length = snprintf(bu, sizeof(bu), "strong");
145 case MRAA_GPIO_PULLDOWN:
146 length = snprintf(bu, sizeof(bu), "pulldown");
155 return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
157 if (write(drive, bu, length*sizeof(char)) == -1) {
158 syslog(LOG_ERR, "galileo2: Failed to write to drive mode");
160 return MRAA_ERROR_INVALID_RESOURCE;
163 sta = mraa_gpio_dir(pullup_e, MRAA_GPIO_OUT);
164 sta += mraa_gpio_write(pullup_e, value);
165 if (sta != MRAA_SUCCESS) {
166 syslog(LOG_ERR, "galileo2: Error Setting pullup");
177 mraa_intel_galileo_gen2_uart_init_pre(int index)
179 mraa_gpio_context io0_output = mraa_gpio_init_raw(32);
180 mraa_gpio_context io1_output = mraa_gpio_init_raw(28);
181 mraa_gpio_dir(io0_output, MRAA_GPIO_OUT);
182 mraa_gpio_dir(io1_output, MRAA_GPIO_OUT);
184 mraa_gpio_write(io0_output, 1);
185 mraa_gpio_write(io1_output, 0);
187 mraa_gpio_close(io0_output);
188 mraa_gpio_close(io1_output);
193 mraa_intel_galileo_g2_mmap_unsetup()
195 if (mmap_reg == NULL) {
196 syslog(LOG_ERR, "mmap: null register cant unsetup");
197 return MRAA_ERROR_INVALID_RESOURCE;
199 munmap(mmap_reg, mmap_size);
206 mraa_intel_galileo_g2_mmap_write(mraa_gpio_context dev, int value)
208 int bitpos = plat->pins[dev->phy_pin].mmap.bit_pos;
210 *((unsigned *)mmap_reg) |= (1<<bitpos);
213 *((unsigned *)mmap_reg) &= ~(1<<bitpos);
219 mraa_intel_galileo_g2_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
222 syslog(LOG_ERR, "Galileo mmap: context not valid");
223 return MRAA_ERROR_INVALID_HANDLE;
226 if (mraa_pin_mode_test(dev->phy_pin, MRAA_PIN_FAST_GPIO) == 0) {
227 syslog(LOG_ERR, "Galileo mmap: mmap not on this pin");
228 return MRAA_ERROR_NO_RESOURCES;
231 if (dev->mmap_write == NULL) {
232 syslog(LOG_ERR, "mmap: can't disable disabled mmap gpio");
233 return MRAA_ERROR_INVALID_PARAMETER;
235 dev->mmap_write = NULL;
237 if (mmap_count == 0) {
238 return mraa_intel_galileo_g2_mmap_unsetup();
243 if (dev->mmap_write != NULL) {
244 syslog(LOG_ERR, "mmap: can't enable enabled mmap gpio");
245 return MRAA_ERROR_INVALID_PARAMETER;
247 if (mmap_reg == NULL) {
248 if ((mmap_fd = open(UIO_PATH, O_RDWR)) < 0) {
249 syslog(LOG_ERR, "mmap: Unable to open UIO device");
250 return MRAA_ERROR_INVALID_RESOURCE;
252 mmap_reg = mmap(NULL, mmap_size, PROT_READ|PROT_WRITE,
253 MAP_SHARED, mmap_fd, 0);
255 if (mmap_reg == MAP_FAILED) {
256 syslog(LOG_ERR, "mmap: failed to mmap");
259 return MRAA_ERROR_NO_RESOURCES;
262 if (mraa_setup_mux_mapped(plat->pins[dev->phy_pin].mmap.gpio)
264 syslog(LOG_ERR, "mmap: unable to setup required multiplexers");
265 return MRAA_ERROR_INVALID_RESOURCE;
267 dev->mmap_write = &mraa_intel_galileo_g2_mmap_write;
272 mraa_intel_galileo_gen2()
274 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
278 b->phy_pin_count = 20;
282 b->adc_supported = 10;
283 b->pwm_default_period = 5000;
284 b->pwm_max_period = 41666;
285 b->pwm_min_period = 666;
287 advance_func->gpio_dir_pre = &mraa_intel_galileo_gen2_dir_pre;
288 advance_func->i2c_init_pre = &mraa_intel_galileo_gen2_i2c_init_pre;
289 advance_func->pwm_period_replace = &mraa_intel_galileo_gen2_pwm_period_replace;
290 advance_func->gpio_mode_replace = &mraa_intel_galileo_gen2_gpio_mode_replace;
291 advance_func->uart_init_pre = &mraa_intel_galileo_gen2_uart_init_pre;
292 advance_func->gpio_mmap_setup = &mraa_intel_galileo_g2_mmap_setup;
294 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_GALILEO_GEN_2_PINCOUNT);
296 strncpy(b->pins[0].name, "IO0", 8);
297 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,1};
298 b->pins[0].gpio.pinmap = 11;
299 b->pins[0].gpio.parent_id = 0;
300 b->pins[0].gpio.mux_total = 0;
301 b->pins[0].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
302 b->pins[0].gpio.output_enable = 32;
303 b->pins[0].gpio.pullup_enable = 33;
304 b->pins[0].mmap.gpio.pinmap = 11;
305 strncpy(b->pins[0].mmap.mem_dev, "/dev/uio0", 12);
306 b->pins[0].mmap.gpio.mux_total = 2;
307 b->pins[0].mmap.gpio.mux[0].pin = 32;
308 b->pins[0].mmap.gpio.mux[0].value = 0;
309 b->pins[0].mmap.gpio.mux[1].pin = 11;
310 b->pins[0].mmap.gpio.mux[1].value = 0;
311 b->pins[0].mmap.mem_sz = 0x1000;
312 b->pins[0].mmap.bit_pos = 3;
313 b->pins[0].uart.parent_id = 0;
314 b->pins[0].uart.mux_total = 0;
316 strncpy(b->pins[1].name, "IO1", 8);
317 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,1};
318 b->pins[1].gpio.pinmap = 12;
319 b->pins[1].gpio.parent_id = 0;
320 b->pins[1].gpio.mux_total = 1;
321 b->pins[1].gpio.mux[0].pin = 45;
322 b->pins[1].gpio.mux[0].value = 0;
323 b->pins[1].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
324 b->pins[1].gpio.output_enable = 28;
325 b->pins[1].gpio.pullup_enable = 29;
326 b->pins[1].mmap.gpio.pinmap = 12;
327 strncpy(b->pins[1].mmap.mem_dev, "/dev/uio0", 12);
328 b->pins[1].mmap.gpio.mux_total = 3;
329 b->pins[1].mmap.gpio.mux[0].pin = 45;
330 b->pins[1].mmap.gpio.mux[0].value = 0;
331 b->pins[1].mmap.gpio.mux[1].pin = 28;
332 b->pins[1].mmap.gpio.mux[1].value = 0;
333 b->pins[1].mmap.gpio.mux[2].pin = 12;
334 b->pins[1].mmap.gpio.mux[2].value = 0;
335 b->pins[1].mmap.mem_sz = 0x1000;
336 b->pins[1].mmap.bit_pos = 4;
337 b->pins[1].uart.parent_id = 0;
338 b->pins[1].uart.mux_total = 1;
339 b->pins[1].uart.mux[0].pin = 45;
340 b->pins[1].uart.mux[0].value = 1;
342 strncpy(b->pins[2].name, "IO2", 8);
343 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0};
344 b->pins[2].gpio.pinmap = 13;
345 b->pins[2].gpio.parent_id = 0;
346 b->pins[2].gpio.mux_total = 1;
347 b->pins[2].gpio.mux[0].pin = 77;
348 b->pins[2].gpio.mux[0].value = 0;
349 b->pins[2].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
350 b->pins[2].gpio.output_enable = 34;
351 b->pins[2].gpio.pullup_enable = 35;
352 b->pins[2].mmap.gpio.pinmap = 13;
353 strncpy(b->pins[2].mmap.mem_dev, "/dev/uio0", 12);
354 b->pins[2].mmap.gpio.mux_total = 3;
355 b->pins[2].mmap.gpio.mux[0].pin = 77;
356 b->pins[2].mmap.gpio.mux[0].value = 0;
357 b->pins[2].mmap.gpio.mux[1].pin = 34;
358 b->pins[2].mmap.gpio.mux[1].value = 0;
359 b->pins[2].mmap.gpio.mux[2].pin = 13;
360 b->pins[2].mmap.gpio.mux[2].value = 0;
361 b->pins[2].mmap.mem_sz = 0x1000;
362 b->pins[2].mmap.bit_pos = 5;
364 strncpy(b->pins[3].name, "IO3", 8);
365 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,1,0,0,0};
366 b->pins[3].gpio.pinmap = 14;
367 b->pins[3].gpio.parent_id = 0;
368 b->pins[3].gpio.mux_total = 2;
369 b->pins[3].gpio.mux[0].pin = 76;
370 b->pins[3].gpio.mux[0].value = 0;
371 b->pins[3].gpio.mux[1].pin = 64;
372 b->pins[3].gpio.mux[1].value = 0;
373 b->pins[3].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
374 b->pins[3].gpio.output_enable = 16;
375 b->pins[3].gpio.pullup_enable = 17;
376 b->pins[3].pwm.pinmap = 1;
377 b->pins[3].pwm.parent_id = 0;
378 b->pins[3].pwm.mux_total = 3;
379 b->pins[3].pwm.mux[0].pin = 76;
380 b->pins[3].pwm.mux[0].value = 0;
381 b->pins[3].pwm.mux[1].pin = 64;
382 b->pins[3].pwm.mux[1].value = 1;
383 b->pins[3].pwm.mux[2].pin = 16;
384 b->pins[3].pwm.mux[2].value = 0;
385 b->pins[3].mmap.gpio.pinmap = 14;
386 strncpy(b->pins[3].mmap.mem_dev, "/dev/uio0", 12);
387 b->pins[3].mmap.gpio.mux_total = 4;
388 b->pins[3].mmap.gpio.mux[0].pin = 76;
389 b->pins[3].mmap.gpio.mux[0].value = 0;
390 b->pins[3].mmap.gpio.mux[1].pin = 64;
391 b->pins[3].mmap.gpio.mux[1].value = 0;
392 b->pins[3].mmap.gpio.mux[2].pin = 16;
393 b->pins[3].mmap.gpio.mux[2].value = 0;
394 b->pins[3].mmap.gpio.mux[3].pin = 14;
395 b->pins[3].mmap.gpio.mux[3].value = 0;
396 b->pins[3].mmap.mem_sz = 0x1000;
397 b->pins[3].mmap.bit_pos = 6;
399 strncpy(b->pins[4].name, "IO4", 8);
400 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
401 b->pins[4].gpio.pinmap = 6;
402 b->pins[4].gpio.parent_id = 0;
403 b->pins[4].gpio.mux_total = 0;
404 b->pins[4].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
405 b->pins[4].gpio.output_enable = 36;
406 b->pins[4].gpio.pullup_enable = 37;
408 strncpy(b->pins[5].name, "IO5", 8);
409 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
410 b->pins[5].gpio.pinmap = 0;
411 b->pins[5].gpio.parent_id = 0;
412 b->pins[5].gpio.mux_total = 1;
413 b->pins[5].gpio.mux[0].pin = 66;
414 b->pins[5].gpio.mux[0].value = 0;
415 b->pins[5].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
416 b->pins[5].gpio.output_enable = 18;
417 b->pins[5].gpio.pullup_enable = 19;
418 b->pins[5].pwm.pinmap = 3;
419 b->pins[5].pwm.parent_id = 0;
420 b->pins[5].pwm.mux_total = 2;
421 b->pins[5].pwm.mux[0].pin = 66;
422 b->pins[5].pwm.mux[0].value = 1;
423 b->pins[5].pwm.mux[1].pin = 18;
424 b->pins[5].pwm.mux[1].value = 0;
426 strncpy(b->pins[6].name, "IO6", 8);
427 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
428 b->pins[6].gpio.pinmap = 1;
429 b->pins[6].gpio.parent_id = 0;
430 b->pins[6].gpio.mux_total = 1;
431 b->pins[6].gpio.mux[0].pin = 68;
432 b->pins[6].gpio.mux[0].value = 0;
433 b->pins[6].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
434 b->pins[6].gpio.output_enable = 20;
435 b->pins[6].gpio.pullup_enable = 21;
436 b->pins[6].pwm.pinmap = 5;
437 b->pins[6].pwm.parent_id = 0;
438 b->pins[6].pwm.mux_total = 2;
439 b->pins[6].pwm.mux[0].pin = 68;
440 b->pins[6].pwm.mux[0].value = 1;
441 b->pins[6].pwm.mux[1].pin = 20;
442 b->pins[6].pwm.mux[1].value = 0;
444 strncpy(b->pins[7].name, "IO7", 8);
445 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
446 b->pins[7].gpio.pinmap = 38;
447 b->pins[7].gpio.parent_id = 0;
448 b->pins[7].gpio.mux_total = 0;
449 b->pins[7].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
450 b->pins[7].gpio.pullup_enable = 39;
452 strncpy(b->pins[8].name, "IO8", 8);
453 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
454 b->pins[8].gpio.pinmap = 40;
455 b->pins[8].gpio.parent_id = 0;
456 b->pins[8].gpio.mux_total = 0;
457 b->pins[8].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
458 b->pins[8].gpio.pullup_enable = 41;
460 strncpy(b->pins[9].name, "IO9", 8);
461 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
462 b->pins[9].gpio.pinmap = 4;
463 b->pins[9].gpio.parent_id = 0;
464 b->pins[9].gpio.mux_total = 1;
465 b->pins[9].gpio.mux[0].pin = 70;
466 b->pins[9].gpio.mux[0].value = 0;
467 b->pins[9].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
468 b->pins[9].gpio.output_enable = 22;
469 b->pins[9].gpio.pullup_enable = 23;
470 b->pins[9].pwm.pinmap = 7;
471 b->pins[9].pwm.parent_id = 0;
472 b->pins[9].pwm.mux_total = 2;
473 b->pins[9].pwm.mux[0].pin = 70;
474 b->pins[9].pwm.mux[0].value = 1;
475 b->pins[9].pwm.mux[1].pin = 22;
476 b->pins[9].pwm.mux[1].value = 0;
478 strncpy(b->pins[10].name, "IO10", 8);
479 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,1,1,1,0,0};
480 b->pins[10].gpio.pinmap = 10;
481 b->pins[10].gpio.parent_id = 0;
482 b->pins[10].gpio.mux_total = 1;
483 b->pins[10].gpio.mux[0].pin = 74;
484 b->pins[10].gpio.mux[0].value = 0;
485 b->pins[10].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
486 b->pins[10].gpio.output_enable = 26;
487 b->pins[10].gpio.pullup_enable = 27;
488 b->pins[10].pwm.pinmap = 11;
489 b->pins[10].pwm.parent_id = 0;
490 b->pins[10].pwm.mux_total = 2;
491 b->pins[10].pwm.mux[0].pin = 74;
492 b->pins[10].pwm.mux[0].value = 1;
493 b->pins[10].pwm.mux[1].pin = 26;
494 b->pins[10].pwm.mux[1].value = 0;
495 b->pins[10].mmap.gpio.pinmap = 10;
496 strncpy(b->pins[10].mmap.mem_dev, "/dev/uio0", 12);
497 b->pins[10].mmap.gpio.mux_total = 3;
498 b->pins[10].mmap.gpio.mux[0].pin = 74;
499 b->pins[10].mmap.gpio.mux[0].value = 0;
500 b->pins[10].mmap.gpio.mux[1].pin = 26;
501 b->pins[10].mmap.gpio.mux[1].value = 0;
502 b->pins[10].mmap.gpio.mux[2].pin = 10;
503 b->pins[10].mmap.gpio.mux[2].value = 0;
504 b->pins[10].mmap.mem_sz = 0x1000;
505 b->pins[10].mmap.bit_pos = 2;
506 b->pins[10].spi.parent_id = 1;
507 b->pins[10].spi.mux_total = 1;
508 b->pins[10].spi.mux[0].pin = 74;
509 b->pins[10].spi.mux[0].value = 0;
511 strncpy(b->pins[11].name, "IO11", 8);
512 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0};
513 b->pins[11].gpio.pinmap = 5;
514 b->pins[11].gpio.parent_id = 0;
515 b->pins[11].gpio.mux_total = 2;
516 b->pins[11].gpio.mux[0].pin = 72;
517 b->pins[11].gpio.mux[0].value = 0;
518 b->pins[11].gpio.mux[1].pin = 44;
519 b->pins[11].gpio.mux[1].value = 0;
520 b->pins[11].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
521 b->pins[11].gpio.output_enable = 24;
522 b->pins[11].gpio.pullup_enable = 25;
523 b->pins[11].pwm.pinmap = 9;
524 b->pins[11].pwm.parent_id = 0;
525 b->pins[11].pwm.mux_total = 3;
526 b->pins[11].pwm.mux[0].pin = 72;
527 b->pins[11].pwm.mux[0].value = 1;
528 b->pins[11].pwm.mux[1].pin = 44;
529 b->pins[11].pwm.mux[1].value = 0;
530 b->pins[11].pwm.mux[2].pin = 24;
531 b->pins[11].pwm.mux[2].value = 0;
532 b->pins[11].spi.pinmap = 1;
533 b->pins[11].spi.mux_total = 3;
534 b->pins[11].spi.mux[0].pin = 72;
535 b->pins[11].spi.mux[0].value = 0;
536 b->pins[11].spi.mux[1].pin = 44;
537 b->pins[11].spi.mux[2].value = 1;
538 b->pins[11].pwm.mux[2].pin = 24;
539 b->pins[11].pwm.mux[2].value = 0;
541 strncpy(b->pins[12].name, "IO12", 8);
542 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,1,1,0,0};
543 b->pins[12].gpio.pinmap = 15;
544 b->pins[12].gpio.parent_id = 0;
545 b->pins[12].gpio.mux_total = 0;
546 b->pins[12].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
547 b->pins[12].gpio.output_enable = 42;
548 b->pins[12].gpio.pullup_enable = 43;
549 b->pins[12].spi.pinmap = 1;
550 b->pins[12].spi.mux_total = 1;
551 b->pins[12].spi.mux[0].pin = 42;
552 b->pins[12].spi.mux[0].value = 1;
553 b->pins[12].mmap.gpio.pinmap = 15;
554 strncpy(b->pins[12].mmap.mem_dev, "/dev/uio0", 12);
555 b->pins[12].mmap.gpio.mux_total = 2;
556 b->pins[12].mmap.gpio.mux[0].pin = 42;
557 b->pins[12].mmap.gpio.mux[0].value = 0;
558 b->pins[12].mmap.gpio.mux[1].pin = 15;
559 b->pins[12].mmap.gpio.mux[1].value = 0;
560 b->pins[12].mmap.mem_sz = 0x1000;
561 b->pins[12].mmap.bit_pos = 7;
563 strncpy(b->pins[13].name, "IO13", 8);
564 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0};
565 b->pins[13].gpio.pinmap = 7;
566 b->pins[13].gpio.parent_id = 0;
567 b->pins[13].gpio.mux_total = 1;
568 b->pins[13].gpio.mux[0].pin = 46;
569 b->pins[13].gpio.mux[0].value = 0;
570 b->pins[13].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
571 b->pins[13].gpio.output_enable = 30;
572 b->pins[13].gpio.pullup_enable = 31;
573 b->pins[13].spi.pinmap = 1;
574 b->pins[13].spi.mux_total = 2;
575 b->pins[13].spi.mux[0].pin = 46;
576 b->pins[13].spi.mux[0].value = 1;
577 b->pins[13].spi.mux[1].pin = 30;
578 b->pins[13].spi.mux[1].value = 0;
581 strncpy(b->pins[14].name, "A0", 8);
582 b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
583 b->pins[14].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
584 b->pins[14].gpio.pullup_enable = 49;
585 b->pins[14].aio.pinmap = 0;
586 b->pins[14].aio.mux_total = 1;
587 b->pins[14].aio.mux[0].pin = 49;
588 b->pins[14].aio.mux[0].value = 1;
589 b->pins[14].gpio.pinmap = 48;
590 b->pins[14].gpio.mux_total = 0;
592 strncpy(b->pins[15].name, "A1", 8);
593 b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
594 b->pins[15].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
595 b->pins[15].gpio.pullup_enable = 51;
596 b->pins[15].aio.pinmap = 1;
597 b->pins[15].aio.mux[0].pin = 51;
598 b->pins[15].aio.mux[0].value = 1;
599 b->pins[15].aio.mux_total = 0;
600 b->pins[15].gpio.pinmap = 50;
601 b->pins[15].gpio.mux_total = 0;
603 strncpy(b->pins[16].name, "A2", 8);
604 b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
605 b->pins[16].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
606 b->pins[16].gpio.pullup_enable = 53;
607 b->pins[16].aio.pinmap = 2;
608 b->pins[16].aio.mux_total = 1;
609 b->pins[16].aio.mux[0].pin = 53;
610 b->pins[16].aio.mux[0].value = 1;
611 b->pins[16].gpio.pinmap = 52;
612 b->pins[16].gpio.mux_total = 0;
614 strncpy(b->pins[17].name, "A3", 8);
615 b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
616 b->pins[17].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
617 b->pins[17].gpio.pullup_enable = 55;
618 b->pins[17].aio.pinmap = 3;
619 b->pins[17].aio.mux_total = 1;
620 b->pins[17].aio.mux[0].pin = 55;
621 b->pins[17].aio.mux[0].value = 1;
622 b->pins[17].gpio.pinmap = 54;
623 b->pins[17].gpio.mux_total = 0;
625 strncpy(b->pins[18].name, "A4", 8);
626 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1};
627 b->pins[18].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
628 b->pins[18].gpio.pullup_enable = 57;
629 b->pins[18].i2c.pinmap = 1;
630 b->pins[18].i2c.mux_total = 1;
631 b->pins[18].i2c.mux[0].pin = 60;
632 b->pins[18].i2c.mux[0].value = 0;
633 b->pins[18].aio.pinmap = 4;
634 b->pins[18].aio.mux_total = 3;
635 b->pins[18].aio.mux[0].pin = 60;
636 b->pins[18].aio.mux[0].value = 1;
637 b->pins[18].aio.mux[1].pin = 78;
638 b->pins[18].aio.mux[1].value = 0;
639 b->pins[18].aio.mux[2].pin = 57;
640 b->pins[18].aio.mux[2].value = 0;
641 b->pins[18].gpio.pinmap = 56;
642 b->pins[18].gpio.mux_total = 2;
643 b->pins[18].gpio.mux[0].pin = 60;
644 b->pins[18].gpio.mux[0].value = 1;
645 b->pins[18].gpio.mux[1].pin = 78;
646 b->pins[18].gpio.mux[1].value = 1;
648 strncpy(b->pins[19].name, "A5", 8);
649 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1};
650 b->pins[19].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
651 b->pins[19].gpio.pullup_enable = 59;
652 b->pins[19].i2c.pinmap = 1;
653 b->pins[19].i2c.mux_total = 1;
654 b->pins[19].i2c.mux[0].pin = 60;
655 b->pins[19].i2c.mux[0].value = 0;
656 b->pins[19].aio.pinmap = 5;
657 b->pins[19].aio.mux_total = 3;
658 b->pins[19].aio.mux[0].pin = 60;
659 b->pins[19].aio.mux[0].value = 1;
660 b->pins[19].aio.mux[1].pin = 79;
661 b->pins[19].aio.mux[1].value = 0;
662 b->pins[19].aio.mux[2].pin = 59;
663 b->pins[19].aio.mux[2].value = 1;
664 b->pins[19].gpio.pinmap = 58;
665 b->pins[19].gpio.mux_total = 2;
666 b->pins[19].gpio.mux[0].pin = 60;
667 b->pins[19].gpio.mux[0].value = 1;
668 b->pins[19].gpio.mux[1].pin = 79;
669 b->pins[19].gpio.mux[1].value = 1;
672 b->i2c_bus_count = 1;
674 b->i2c_bus[0].bus_id = 0;
675 b->i2c_bus[0].sda = 18;
676 b->i2c_bus[0].scl = 19;
678 b->spi_bus_count = 1;
680 b->spi_bus[0].bus_id = 1;
681 b->spi_bus[0].slave_s = 0;
682 b->spi_bus[0].cs = 10;
683 b->spi_bus[0].mosi = 11;
684 b->spi_bus[0].miso = 12;
685 b->spi_bus[0].sclk = 13;
687 b->uart_dev_count = 1;
689 b->uart_dev[0].rx = 0;
690 b->uart_dev[0].tx = 1;