2 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
3 * Copyright (c) 2014 Intel Corporation.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "intel_galileo_rev_d.h"
32 #define UIO_PATH "/dev/uio0"
34 static uint8_t *mmap_reg = NULL;
35 static int mmap_fd = 0;
36 static int mmap_size = 0x1000;
37 static unsigned int mmap_count = 0;
40 mraa_intel_galileo_g1_mmap_unsetup()
42 if (mmap_reg == NULL) {
43 syslog(LOG_ERR, "mmap: null register cant unsetup");
44 return MRAA_ERROR_INVALID_RESOURCE;
46 munmap(mmap_reg, mmap_size);
53 mraa_intel_galileo_g1_mmap_write(mraa_gpio_context dev, int value)
55 int bitpos = plat->pins[dev->phy_pin].mmap.bit_pos;
57 *((unsigned *)mmap_reg) |= (1<<bitpos);
60 *((unsigned *)mmap_reg) &= ~(1<<bitpos);
66 mraa_intel_galileo_g1_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
69 syslog(LOG_ERR, "Galileo mmap: context not valid");
70 return MRAA_ERROR_INVALID_HANDLE;
73 if (mraa_pin_mode_test(dev->phy_pin, MRAA_PIN_FAST_GPIO) == 0) {
74 syslog(LOG_ERR, "Galileo mmap: mmap not on this pin");
75 return MRAA_ERROR_NO_RESOURCES;
78 if (dev->mmap_write == NULL) {
79 syslog(LOG_ERR, "mmap: can't disable disabled mmap gpio");
80 return MRAA_ERROR_INVALID_PARAMETER;
82 dev->mmap_write = NULL;
84 if (mmap_count == 0) {
85 return mraa_intel_galileo_g1_mmap_unsetup();
90 if (dev->mmap_write != NULL) {
91 syslog(LOG_ERR, "mmap: can't enable enabled mmap gpio");
92 return MRAA_ERROR_INVALID_PARAMETER;
94 if (mmap_reg == NULL) {
95 if ((mmap_fd = open(UIO_PATH, O_RDWR)) < 0) {
96 syslog(LOG_ERR, "mmap: Unable to open UIO device");
97 return MRAA_ERROR_INVALID_RESOURCE;
99 mmap_reg = mmap(NULL, mmap_size, PROT_READ|PROT_WRITE,
100 MAP_SHARED, mmap_fd, 0);
102 if (mmap_reg == MAP_FAILED) {
103 syslog(LOG_ERR, "mmap: failed to mmap");
106 return MRAA_ERROR_NO_RESOURCES;
109 if (mraa_setup_mux_mapped(plat->pins[dev->phy_pin].mmap.gpio)
111 syslog(LOG_ERR, "mmap: unable to setup required multiplexers");
112 return MRAA_ERROR_INVALID_RESOURCE;
114 dev->mmap_write = &mraa_intel_galileo_g1_mmap_write;
120 mraa_intel_galileo_rev_d()
122 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
126 b->phy_pin_count = 20;
129 b->uart_dev_count = 2;
132 b->adc_supported = 10;
133 b->pwm_default_period = 500;
134 b->pwm_max_period = 7968;
135 b->pwm_min_period = 1;
137 advance_func->gpio_mmap_setup = &mraa_intel_galileo_g1_mmap_setup;
139 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_GALILEO_REV_D_PINCOUNT);
142 strncpy(b->pins[0].name, "IO0", 8);
143 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
144 b->pins[0].gpio.pinmap = 50;
145 b->pins[0].gpio.parent_id = 0;
146 b->pins[0].gpio.mux_total = 1;
147 b->pins[0].gpio.mux[0].pin = 40;
148 b->pins[0].gpio.mux[0].value = 1;
149 b->pins[0].uart.pinmap = 0;
150 b->pins[0].uart.parent_id = 0;
151 b->pins[0].uart.mux_total = 1;
152 b->pins[0].uart.mux[0].pin = 40;
153 b->pins[0].uart.mux[0].value = 0;
155 strncpy(b->pins[1].name, "IO1", 8);
156 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
157 b->pins[1].gpio.pinmap = 51;
158 b->pins[1].gpio.mux_total = 1;
159 b->pins[1].gpio.mux[0].pin = 41;
160 b->pins[1].gpio.mux[0].value = 1;
161 b->pins[1].uart.pinmap = 0;
162 b->pins[1].uart.parent_id = 0;
163 b->pins[1].uart.mux_total = 1;
164 b->pins[1].uart.mux[0].pin = 41;
165 b->pins[1].uart.mux[0].value = 0;
167 strncpy(b->pins[2].name, "IO2", 8);
168 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,0};
169 b->pins[2].gpio.pinmap = 32;
170 b->pins[2].gpio.mux_total = 1;
171 b->pins[2].gpio.mux[0].pin = 31;
172 b->pins[2].gpio.mux[0].value = 1;
173 b->pins[2].mmap.gpio.pinmap = 14;
174 strncpy(b->pins[2].mmap.mem_dev, "/dev/uio0", 12);
175 b->pins[2].mmap.gpio.mux_total = 2;
176 b->pins[2].mmap.gpio.mux[0].pin = 31;
177 b->pins[2].mmap.gpio.mux[0].value = 0;
178 b->pins[2].mmap.gpio.mux[1].pin = 14;
179 b->pins[2].mmap.gpio.mux[1].value = 0;
180 b->pins[2].mmap.mem_sz = 0x1000;
181 b->pins[2].mmap.bit_pos = 6;
183 strncpy(b->pins[3].name, "IO3", 8);
184 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,1,0,0,0,0};
185 b->pins[3].gpio.pinmap = 18;
186 b->pins[3].gpio.mux_total = 1;
187 b->pins[3].gpio.mux[0].pin = 30;
188 b->pins[3].gpio.mux[0].value = 1;
189 b->pins[3].mmap.gpio.pinmap = 15;
190 strncpy(b->pins[3].mmap.mem_dev, "/dev/uio0", 12);
191 b->pins[3].mmap.gpio.mux_total = 2;
192 b->pins[3].mmap.gpio.mux[0].pin = 30;
193 b->pins[3].mmap.gpio.mux[0].value = 0;
194 b->pins[3].mmap.gpio.mux[1].pin = 15;
195 b->pins[3].mmap.gpio.mux[1].value = 0;
196 b->pins[3].mmap.mem_sz = 0x1000;
197 b->pins[3].mmap.bit_pos = 7;
198 b->pins[3].pwm.pinmap = 3;
199 b->pins[3].pwm.parent_id = 0;
200 b->pins[3].pwm.mux_total = 1;
201 b->pins[3].pwm.mux[0].pin = 30;
202 b->pins[3].pwm.mux[0].value = 1;
205 strncpy(b->pins[4].name, "IO4", 8);
206 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
207 b->pins[4].gpio.pinmap = 28;
208 b->pins[4].gpio.mux_total = 0;
210 strncpy(b->pins[5].name, "IO5", 8);
211 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
212 b->pins[5].gpio.pinmap = 17;
213 b->pins[5].gpio.mux_total = 0;
214 b->pins[5].pwm.pinmap = 5;
215 b->pins[5].pwm.parent_id = 0;
216 b->pins[5].pwm.mux_total = 0;
218 strncpy(b->pins[6].name, "IO6", 8);
219 b->pins[6].gpio.pinmap = 24;
220 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
221 b->pins[6].gpio.mux_total = 0;
222 b->pins[6].pwm.pinmap = 6;
223 b->pins[6].pwm.parent_id = 0;
224 b->pins[6].pwm.mux_total = 0;
226 strncpy(b->pins[7].name, "IO7", 8);
227 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
228 b->pins[7].gpio.pinmap = 27;
229 b->pins[7].gpio.mux_total = 0;
231 strncpy(b->pins[8].name, "IO8", 8);
232 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
233 b->pins[8].gpio.pinmap = 26;
234 b->pins[8].gpio.mux_total = 0;
236 strncpy(b->pins[9].name, "IO9", 8);
237 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
238 b->pins[9].gpio.pinmap = 19;
239 b->pins[9].gpio.mux_total = 0;
240 b->pins[9].pwm.pinmap = 1;
241 b->pins[9].pwm.parent_id = 0;
242 b->pins[9].pwm.mux_total = 0;
244 strncpy(b->pins[10].name, "IO10", 8);
245 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0,0};
246 b->pins[10].gpio.pinmap = 16;
247 b->pins[10].gpio.mux_total = 1;
248 b->pins[10].gpio.mux[0].pin = 42;
249 b->pins[10].gpio.mux[0].value = 1;
250 b->pins[10].pwm.pinmap = 7;
251 b->pins[10].pwm.parent_id = 0;
252 b->pins[10].pwm.mux_total = 1;
253 b->pins[10].pwm.mux[0].pin = 42;
254 b->pins[10].pwm.mux[0].value = 1;
255 b->pins[10].spi.pinmap = 1;
256 b->pins[10].spi.mux_total = 1;
257 b->pins[10].spi.mux[0].pin = 42;
258 b->pins[10].spi.mux[0].value = 0;
260 strncpy(b->pins[11].name, "IO11", 8);
261 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0,0};
262 b->pins[11].gpio.pinmap = 25;
263 b->pins[11].gpio.mux_total = 1;
264 b->pins[11].gpio.mux[0].pin = 43;
265 b->pins[11].gpio.mux[0].value = 1;
266 b->pins[11].pwm.pinmap = 4;
267 b->pins[11].pwm.parent_id = 0;
268 b->pins[11].pwm.mux_total = 1;
269 b->pins[11].pwm.mux[0].pin = 43;
270 b->pins[11].pwm.mux[0].value = 1;
271 b->pins[11].spi.pinmap = 1;
272 b->pins[11].spi.mux_total = 1;
273 b->pins[11].spi.mux[0].pin = 43;
274 b->pins[11].spi.mux[0].value = 0;
276 strncpy(b->pins[12].name, "IO12", 8);
277 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
278 b->pins[12].gpio.pinmap = 38;
279 b->pins[12].gpio.mux_total = 1;
280 b->pins[12].gpio.mux[0].pin = 54;
281 b->pins[12].gpio.mux[0].value = 1;
282 b->pins[12].spi.pinmap = 1;
283 b->pins[12].spi.mux_total = 1;
284 b->pins[12].spi.mux[0].pin = 54;
285 b->pins[12].spi.mux[0].value = 0;
287 strncpy(b->pins[13].name, "IO13", 8);
288 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
289 b->pins[13].gpio.pinmap = 39;
290 b->pins[13].gpio.mux_total = 1;
291 b->pins[13].gpio.mux[0].pin = 55;
292 b->pins[13].gpio.mux[0].value = 1;
293 b->pins[13].spi.pinmap = 1;
294 b->pins[13].spi.mux_total = 1;
295 b->pins[13].spi.mux[0].pin = 55;
296 b->pins[13].spi.mux[0].value = 0;
298 strncpy(b->pins[14].name, "A0", 8);
299 b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
300 b->pins[14].gpio.pinmap = 44;
301 b->pins[14].gpio.mux_total = 1;
302 b->pins[14].gpio.mux[0].pin = 37;
303 b->pins[14].gpio.mux[0].value = 1;
304 b->pins[14].aio.pinmap = 0;
305 b->pins[14].aio.mux_total = 1;
306 b->pins[14].aio.mux[0].pin = 37;
307 b->pins[14].aio.mux[0].value = 0;
309 strncpy(b->pins[15].name, "A1", 8);
310 b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
311 b->pins[15].gpio.pinmap = 45;
312 b->pins[15].gpio.mux_total = 1;
313 b->pins[15].gpio.mux[0].pin = 36;
314 b->pins[15].gpio.mux[0].value = 1;
315 b->pins[15].aio.pinmap = 1;
316 b->pins[15].aio.mux_total = 1;
317 b->pins[15].aio.mux[0].pin = 36;
318 b->pins[15].aio.mux[0].value = 0;
320 strncpy(b->pins[16].name, "A2", 8);
321 b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
322 b->pins[16].gpio.pinmap = 46;
323 b->pins[16].gpio.mux_total = 1;
324 b->pins[16].gpio.mux[0].pin = 23;
325 b->pins[16].gpio.mux[0].value = 1;
326 b->pins[16].aio.pinmap = 2;
327 b->pins[16].aio.mux_total = 1;
328 b->pins[16].aio.mux[0].pin = 23;
329 b->pins[16].aio.mux[0].value = 0;
331 strncpy(b->pins[17].name, "A3", 8);
332 b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
333 b->pins[17].gpio.pinmap = 47;
334 b->pins[17].gpio.mux_total = 1;
335 b->pins[17].gpio.mux[0].pin = 22;
336 b->pins[17].gpio.mux[0].value = 1;
337 b->pins[17].aio.pinmap = 3;
338 b->pins[17].aio.mux_total = 1;
339 b->pins[17].aio.mux[0].pin = 22;
340 b->pins[17].aio.mux[0].value = 0;
342 strncpy(b->pins[18].name, "A4", 8);
343 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
344 b->pins[18].gpio.pinmap = 48;
345 b->pins[18].gpio.mux_total = 2;
346 b->pins[18].gpio.mux[0].pin = 29;
347 b->pins[18].gpio.mux[0].value = 1;
348 b->pins[18].gpio.mux[1].pin = 21;
349 b->pins[18].gpio.mux[1].value = 1;
350 b->pins[18].i2c.pinmap = 1;
351 b->pins[18].i2c.mux_total = 1;
352 b->pins[18].i2c.mux[0].pin = 29;
353 b->pins[18].i2c.mux[0].value = 0;
354 b->pins[18].aio.pinmap = 4;
355 b->pins[18].aio.mux_total = 2;
356 b->pins[18].aio.mux[0].pin = 29;
357 b->pins[18].aio.mux[0].value = 1;
358 b->pins[18].aio.mux[1].pin = 21;
359 b->pins[18].aio.mux[1].value = 0;
361 strncpy(b->pins[19].name, "A5", 8);
362 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
363 b->pins[19].gpio.pinmap = 49;
364 b->pins[19].gpio.mux_total = 2;
365 b->pins[19].gpio.mux[0].pin = 29;
366 b->pins[19].gpio.mux[0].value = 1;
367 b->pins[19].gpio.mux[1].pin = 20;
368 b->pins[19].gpio.mux[1].value = 1;
369 b->pins[19].i2c.pinmap = 1;
370 b->pins[19].i2c.mux_total = 1;
371 b->pins[19].i2c.mux[0].pin = 29;
372 b->pins[19].i2c.mux[0].value = 0;
373 b->pins[19].aio.pinmap = 5;
374 b->pins[19].aio.mux_total = 2;
375 b->pins[19].aio.mux[0].pin = 29;
376 b->pins[19].aio.mux[0].value = 1;
377 b->pins[19].aio.mux[1].pin = 20;
378 b->pins[19].aio.mux[1].value = 0;
381 b->i2c_bus_count = 1;
383 b->i2c_bus[0].bus_id = 0;
384 b->i2c_bus[0].sda = 18;
385 b->i2c_bus[0].scl = 19;
387 b->spi_bus_count = 1;
389 b->spi_bus[0].bus_id = 1;
390 b->spi_bus[0].slave_s = 0;
391 b->spi_bus[0].cs = 10;
392 b->spi_bus[0].mosi = 11;
393 b->spi_bus[0].miso = 12;
394 b->spi_bus[0].sclk = 13;
397 b->uart_dev[0].rx = 0;
398 b->uart_dev[0].tx = 1;
399 b->uart_dev[1].rx = -1;
400 b->uart_dev[1].tx = -1;