2 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
3 * Copyright (c) 2014 Intel Corporation.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "intel_edison_fab_c.h"
31 #define SYSFS_PINMODE_PATH "/sys/kernel/debug/gpio_debug/gpio"
33 #define MAX_MODE_SIZE 8
38 } mraa_intel_edision_pindef_t;
41 mraa_intel_edision_pindef_t gpio;
42 mraa_intel_edision_pindef_t pwm;
43 mraa_intel_edision_pindef_t i2c;
44 mraa_intel_edision_pindef_t spi;
45 mraa_intel_edision_pindef_t uart;
46 } mraa_intel_edison_pinmodes_t;
48 static mraa_gpio_context tristate;
50 static mraa_intel_edison_pinmodes_t pinmodes[MRAA_INTEL_EDISON_PINCOUNT];
51 static unsigned int outputen[] = {248,249,250,251,252,253,254,255,256,257,258,259,260,261,232,233,234,235,236,237};
54 mraa_intel_edison_pinmode_change(int sysfs, int mode)
60 printf("//EDISON// PINMODE CHANGE - gpio%i changing to mode -%u", sysfs, mode);
62 char buffer[MAX_SIZE];
63 snprintf(buffer, MAX_SIZE, SYSFS_PINMODE_PATH "%i/current_pinmux",sysfs);
64 int modef = open(buffer, O_WRONLY);
66 fprintf(stderr, "Failed to open SoC pinmode for opening\n");
67 return MRAA_ERROR_INVALID_RESOURCE;
70 char mode_buf[MAX_MODE_SIZE];
71 int length = sprintf(mode_buf, "mode%u",mode);
72 printf("//EDISON// PIMODE = %s", mode_buf);
73 if (write(modef, mode_buf, length*sizeof(char)) == -1) {
74 return MRAA_ERROR_INVALID_RESOURCE;
82 mraa_intel_edison_gpio_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
84 mraa_gpio_write(tristate, 0);
85 if (dev->phy_pin >= 0) {
86 int pin = dev->phy_pin;
88 mraa_gpio_context output_e;
89 output_e = mraa_gpio_init_raw(outputen[pin]);
90 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
91 return MRAA_ERROR_INVALID_RESOURCE;
93 if (dir == MRAA_GPIO_OUT)
95 if (mraa_gpio_write(output_e, output_val) != MRAA_SUCCESS)
96 return MRAA_ERROR_INVALID_RESOURCE;
102 mraa_intel_edison_gpio_dir_post(mraa_gpio_context dev, gpio_dir_t dir)
104 mraa_gpio_write(tristate, 1);
109 mraa_intel_edison_gpio_init_post(mraa_gpio_context dev)
112 return MRAA_ERROR_INVALID_RESOURCE;
114 int sysfs = pinmodes[dev->phy_pin].gpio.sysfs;
115 int mode = pinmodes[dev->phy_pin].gpio.mode;
116 mraa_result_t ret = mraa_intel_edison_pinmode_change(sysfs, mode);
117 if (ret != MRAA_SUCCESS);
123 mraa_intel_edison_i2c_init_pre(unsigned int bus)
126 fprintf(stderr, "Edison: You can use that bus, ERR\n");
127 return MRAA_ERROR_INVALID_RESOURCE;
129 mraa_gpio_write(tristate, 0);
130 mraa_gpio_context io18_gpio = mraa_gpio_init_raw(14);
131 mraa_gpio_context io19_gpio = mraa_gpio_init_raw(165);
132 mraa_gpio_dir(io18_gpio, MRAA_GPIO_IN);
133 mraa_gpio_dir(io19_gpio, MRAA_GPIO_IN);
134 mraa_gpio_close(io18_gpio);
135 mraa_gpio_close(io19_gpio);
137 mraa_gpio_context io18_enable = mraa_gpio_init_raw(236);
138 mraa_gpio_context io19_enable = mraa_gpio_init_raw(237);
139 mraa_gpio_dir(io18_enable, MRAA_GPIO_OUT);
140 mraa_gpio_dir(io19_enable, MRAA_GPIO_OUT);
141 mraa_gpio_write(io18_enable, 0);
142 mraa_gpio_write(io19_enable, 0);
143 mraa_gpio_close(io18_enable);
144 mraa_gpio_close(io19_enable);
146 mraa_gpio_context io18_pullup = mraa_gpio_init_raw(212);
147 mraa_gpio_context io19_pullup = mraa_gpio_init_raw(213);
148 mraa_gpio_dir(io18_pullup, MRAA_GPIO_IN);
149 mraa_gpio_dir(io19_pullup, MRAA_GPIO_IN);
150 mraa_gpio_close(io18_pullup);
151 mraa_gpio_close(io19_pullup);
153 mraa_intel_edison_pinmode_change(28, 1);
154 mraa_intel_edison_pinmode_change(27, 1);
156 mraa_gpio_write(tristate, 1);
161 mraa_intel_edison_fab_c()
163 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
167 b->phy_pin_count = 20;
171 advance_func->gpio_dir_pre = &mraa_intel_edison_gpio_dir_pre;
172 advance_func->gpio_init_post = &mraa_intel_edison_gpio_init_post;
173 advance_func->gpio_dir_post = &mraa_intel_edison_gpio_dir_post;
174 advance_func->i2c_init_pre = &mraa_intel_edison_i2c_init_pre;
176 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_EDISON_PINCOUNT);
178 tristate = mraa_gpio_init_raw(214);
179 if (tristate == NULL) {
180 fprintf(stderr, "Intel Edison Failed to initialise Arduino board TriState,\
181 check i2c devices! FATAL\n");
184 mraa_gpio_dir(tristate, MRAA_GPIO_OUT);
186 strncpy(b->pins[0].name, "IO0", 8);
187 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
188 b->pins[0].gpio.pinmap = 130;
189 b->pins[0].gpio.parent_id = 0;
190 b->pins[0].gpio.mux_total = 0;
192 strncpy(b->pins[1].name, "IO1", 8);
193 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
194 b->pins[1].gpio.pinmap = 131;
195 b->pins[1].gpio.parent_id = 0;
196 b->pins[1].gpio.mux_total = 0;
198 strncpy(b->pins[2].name, "IO2", 8);
199 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
200 b->pins[2].gpio.pinmap = 128;
201 b->pins[2].gpio.parent_id = 0;
202 b->pins[2].gpio.mux_total = 0;
204 strncpy(b->pins[3].name, "IO3", 8);
205 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
206 b->pins[3].gpio.pinmap = 12;
207 b->pins[3].gpio.parent_id = 0;
208 b->pins[3].gpio.mux_total = 0;
210 strncpy(b->pins[4].name, "IO4", 8);
211 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
212 b->pins[4].gpio.pinmap = 129;
213 b->pins[4].gpio.parent_id = 0;
214 b->pins[4].gpio.mux_total = 0;
216 strncpy(b->pins[5].name, "IO5", 8);
217 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
218 b->pins[5].gpio.pinmap = 13;
219 b->pins[5].gpio.parent_id = 0;
220 b->pins[5].gpio.mux_total = 0;
222 strncpy(b->pins[6].name, "IO6", 8);
223 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
224 b->pins[6].gpio.pinmap = 182;
225 b->pins[6].gpio.parent_id = 0;
226 b->pins[6].gpio.mux_total = 0;
228 strncpy(b->pins[7].name, "IO7", 8);
229 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
230 b->pins[7].gpio.pinmap = 48;
231 b->pins[7].gpio.parent_id = 0;
232 b->pins[7].gpio.mux_total = 0;
234 strncpy(b->pins[8].name, "IO8", 8);
235 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
236 b->pins[8].gpio.pinmap = 49;
237 b->pins[8].gpio.parent_id = 0;
238 b->pins[8].gpio.mux_total = 0;
240 strncpy(b->pins[9].name, "IO9", 8);
241 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
242 b->pins[9].gpio.pinmap = 183;
243 b->pins[9].gpio.parent_id = 0;
244 b->pins[9].gpio.mux_total = 0;
246 strncpy(b->pins[10].name, "IO10", 8);
247 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
248 b->pins[10].gpio.pinmap = 41;
249 b->pins[10].gpio.parent_id = 0;
250 b->pins[10].gpio.mux_total = 2;
251 b->pins[10].gpio.mux[0].pin = 263;
252 b->pins[10].gpio.mux[0].value = 1;
253 b->pins[10].gpio.mux[1].pin = 240;
254 b->pins[10].gpio.mux[1].value = 0;
256 strncpy(b->pins[11].name, "IO11", 8);
257 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
258 b->pins[11].gpio.pinmap = 43;
259 b->pins[11].gpio.parent_id = 0;
260 b->pins[11].gpio.mux_total = 2;
261 b->pins[11].gpio.mux[0].pin = 262;
262 b->pins[11].gpio.mux[0].value = 1;
263 b->pins[11].gpio.mux[1].pin = 241;
264 b->pins[11].gpio.mux[1].value = 0;
266 strncpy(b->pins[12].name, "IO12", 8);
267 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
268 b->pins[12].gpio.pinmap = 42;
269 b->pins[12].gpio.parent_id = 0;
270 b->pins[12].gpio.mux_total = 1;
271 b->pins[12].gpio.mux[0].pin = 242;
272 b->pins[12].gpio.mux[0].value = 0;
274 strncpy(b->pins[13].name, "IO13", 8);
275 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
276 b->pins[13].gpio.pinmap = 40;
277 b->pins[13].gpio.parent_id = 0;
278 b->pins[13].gpio.mux_total = 1;
279 b->pins[13].gpio.mux[0].pin = 243;
280 b->pins[13].gpio.mux[0].value = 0;
282 strncpy(b->pins[18].name, "A4", 8);
283 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,1,0};
284 b->pins[18].i2c.pinmap = 1;
285 b->pins[18].i2c.mux_total = 1;
286 b->pins[18].i2c.mux[0].pin = 204;
287 b->pins[18].i2c.mux[0].value = 0;
289 strncpy(b->pins[19].name, "A5", 8);
290 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,1,0};
291 b->pins[19].i2c.pinmap = 1;
292 b->pins[19].i2c.mux_total = 1;
293 b->pins[19].i2c.mux[0].pin = 205;
294 b->pins[19].i2c.mux[0].value = 0;
297 b->i2c_bus_count = 9;
300 for (ici = 0; ici < 9; ici++) {
301 b->i2c_bus[ici].bus_id = -1;
303 b->i2c_bus[6].bus_id = 6;
304 b->i2c_bus[6].sda = 18;
305 b->i2c_bus[6].scl = 19;
307 b->spi_bus_count = 1;
309 b->spi_bus[0].bus_id = 1;
310 b->spi_bus[0].slave_s = 0;
311 b->spi_bus[0].cs = 10;
312 b->spi_bus[0].mosi = 11;
313 b->spi_bus[0].miso = 12;
314 b->spi_bus[0].sclk = 13;
318 for(il =0; il < MRAA_INTEL_EDISON_PINCOUNT; il++) {
319 pinmodes[il].gpio.sysfs = -1;
320 pinmodes[il].gpio.mode = -1;
321 pinmodes[il].pwm.sysfs = -1;
322 pinmodes[il].pwm.mode = -1;
323 pinmodes[il].i2c.sysfs = -1;
324 pinmodes[il].i2c.mode = -1;
325 pinmodes[il].spi.sysfs = -1;
326 pinmodes[il].spi.mode = -1;
327 pinmodes[il].uart.sysfs = -1;
328 pinmodes[il].uart.mode = -1;
330 pinmodes[0].gpio.sysfs = 130;
331 pinmodes[0].gpio.mode = 0;
332 pinmodes[0].uart.sysfs = 130;
333 pinmodes[0].uart.mode = 1;
334 pinmodes[1].gpio.sysfs = 131;
335 pinmodes[1].gpio.mode = 0;
336 pinmodes[1].uart.sysfs = 131;
337 pinmodes[1].uart.mode = 1;
338 pinmodes[2].gpio.sysfs = 128;
339 pinmodes[2].gpio.mode = 0;
340 pinmodes[2].uart.sysfs = 128;
341 pinmodes[2].uart.mode = 1;
342 pinmodes[3].gpio.sysfs = 12;
343 pinmodes[3].gpio.mode = 0;
344 pinmodes[3].pwm.sysfs = 12;
345 pinmodes[3].pwm.mode = 1;
347 pinmodes[4].gpio.sysfs = 129;
348 pinmodes[4].gpio.mode = 0;
349 pinmodes[4].uart.sysfs = 129;
350 pinmodes[4].uart.mode = 1;
351 pinmodes[5].gpio.sysfs = 13;
352 pinmodes[5].gpio.mode = 0;
353 pinmodes[5].pwm.sysfs = 13;
354 pinmodes[5].pwm.mode = 1;
355 pinmodes[6].gpio.sysfs = 182;
356 pinmodes[6].gpio.mode = 0;
357 pinmodes[6].pwm.sysfs = 182;
358 pinmodes[6].pwm.mode = 1;
360 //7 and 8 are provided by something on i2c, very simplepinmodes[3].gpio.sysfs = 12;
361 pinmodes[9].gpio.sysfs = 183;
362 pinmodes[9].gpio.mode = 0;
363 pinmodes[9].pwm.sysfs = 183;
364 pinmodes[9].pwm.mode = 1;
366 pinmodes[10].gpio.sysfs = 41;
367 pinmodes[10].gpio.mode = 0;
368 pinmodes[10].spi.sysfs = 111; // Different pin provides, switched at mux level.
369 pinmodes[10].spi.mode = 1;
371 pinmodes[11].gpio.sysfs = 43;
372 pinmodes[11].gpio.mode = 0;
373 pinmodes[11].spi.sysfs = 115; // Different pin provides, switched at mux level.
374 pinmodes[11].spi.mode = 1;
376 pinmodes[12].gpio.sysfs = 42;
377 pinmodes[12].gpio.mode = 0;
378 pinmodes[12].spi.sysfs = 114; // Different pin provides, switched at mux level.
379 pinmodes[12].spi.mode = 1;
381 pinmodes[13].gpio.sysfs = 40;
382 pinmodes[13].gpio.mode = 0;
383 pinmodes[13].spi.sysfs = 109; // Different pin provides, switched at mux level.
384 pinmodes[13].spi.mode = 1;
385 //Everything else but A4 A5 LEAVE
386 pinmodes[18].gpio.sysfs = 14;
387 pinmodes[18].gpio.mode = 0;
388 pinmodes[18].i2c.sysfs = 28;
389 pinmodes[18].i2c.mode = 1;
391 pinmodes[19].gpio.sysfs = 165;
392 pinmodes[19].gpio.mode = 0;
393 pinmodes[19].i2c.sysfs = 27;
394 pinmodes[19].i2c.mode = 1;