2 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
3 * Copyright (c) 2014 Intel Corporation.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "intel_edison_fab_c.h"
31 #define SYSFS_CLASS_GPIO "/sys/class/gpio"
32 #define SYSFS_PINMODE_PATH "/sys/kernel/debug/gpio_debug/gpio"
34 #define MAX_MODE_SIZE 8
39 } mraa_intel_edision_pindef_t;
42 mraa_intel_edision_pindef_t gpio;
43 mraa_intel_edision_pindef_t pwm;
44 mraa_intel_edision_pindef_t i2c;
45 mraa_intel_edision_pindef_t spi;
46 mraa_intel_edision_pindef_t uart;
47 } mraa_intel_edison_pinmodes_t;
49 static mraa_gpio_context tristate;
51 static mraa_intel_edison_pinmodes_t pinmodes[MRAA_INTEL_EDISON_PINCOUNT];
52 static unsigned int outputen[] = {248,249,250,251,252,253,254,255,256,257,258,259,260,261,232,233,234,235,236,237};
53 static unsigned int pullup_map[] = {216,217,218,219,220,221,222,223,224,225,226,227,228,229,208,209,210,211,212,213};
56 mraa_intel_edison_pinmode_change(int sysfs, int mode)
61 char buffer[MAX_SIZE];
62 snprintf(buffer, MAX_SIZE, SYSFS_PINMODE_PATH "%i/current_pinmux",sysfs);
63 int modef = open(buffer, O_WRONLY);
65 syslog(LOG_ERR, "Failed to open SoC pinmode for opening");
66 return MRAA_ERROR_INVALID_RESOURCE;
69 char mode_buf[MAX_MODE_SIZE];
70 int length = sprintf(mode_buf, "mode%u",mode);
71 if (write(modef, mode_buf, length*sizeof(char)) == -1) {
73 return MRAA_ERROR_INVALID_RESOURCE;
81 mraa_intel_edison_gpio_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
83 mraa_gpio_write(tristate, 0);
84 if (dev->phy_pin >= 0) {
85 int pin = dev->phy_pin;
87 mraa_gpio_context output_e;
88 output_e = mraa_gpio_init_raw(outputen[pin]);
89 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
90 return MRAA_ERROR_INVALID_RESOURCE;
92 if (dir == MRAA_GPIO_OUT)
94 if (mraa_gpio_write(output_e, output_val) != MRAA_SUCCESS)
95 return MRAA_ERROR_INVALID_RESOURCE;
101 mraa_intel_edison_gpio_dir_post(mraa_gpio_context dev, gpio_dir_t dir)
103 mraa_gpio_write(tristate, 1);
108 mraa_intel_edison_gpio_init_post(mraa_gpio_context dev)
111 return MRAA_ERROR_INVALID_RESOURCE;
113 int sysfs = pinmodes[dev->phy_pin].gpio.sysfs;
114 int mode = pinmodes[dev->phy_pin].gpio.mode;
115 mraa_result_t ret = mraa_intel_edison_pinmode_change(sysfs, mode);
121 mraa_intel_edison_i2c_init_pre(unsigned int bus)
124 syslog(LOG_ERR, "Edison: You can't use that bus :/");
125 return MRAA_ERROR_INVALID_RESOURCE;
127 mraa_gpio_write(tristate, 0);
128 mraa_gpio_context io18_gpio = mraa_gpio_init_raw(14);
129 mraa_gpio_context io19_gpio = mraa_gpio_init_raw(165);
130 mraa_gpio_dir(io18_gpio, MRAA_GPIO_IN);
131 mraa_gpio_dir(io19_gpio, MRAA_GPIO_IN);
132 mraa_gpio_close(io18_gpio);
133 mraa_gpio_close(io19_gpio);
135 mraa_gpio_context io18_enable = mraa_gpio_init_raw(236);
136 mraa_gpio_context io19_enable = mraa_gpio_init_raw(237);
137 mraa_gpio_dir(io18_enable, MRAA_GPIO_OUT);
138 mraa_gpio_dir(io19_enable, MRAA_GPIO_OUT);
139 mraa_gpio_write(io18_enable, 0);
140 mraa_gpio_write(io19_enable, 0);
141 mraa_gpio_close(io18_enable);
142 mraa_gpio_close(io19_enable);
144 mraa_gpio_context io18_pullup = mraa_gpio_init_raw(212);
145 mraa_gpio_context io19_pullup = mraa_gpio_init_raw(213);
146 mraa_gpio_dir(io18_pullup, MRAA_GPIO_IN);
147 mraa_gpio_dir(io19_pullup, MRAA_GPIO_IN);
148 mraa_gpio_close(io18_pullup);
149 mraa_gpio_close(io19_pullup);
151 mraa_intel_edison_pinmode_change(28, 1);
152 mraa_intel_edison_pinmode_change(27, 1);
154 mraa_gpio_write(tristate, 1);
159 mraa_intel_edison_misc_spi()
161 mraa_gpio_write(tristate, 0);
163 mraa_gpio_context io10_p1 = mraa_gpio_init_raw(263);
164 mraa_gpio_context io10_p2 = mraa_gpio_init_raw(240);
165 mraa_gpio_context io11_p1 = mraa_gpio_init_raw(262);
166 mraa_gpio_context io11_p2 = mraa_gpio_init_raw(241);
167 mraa_gpio_context io12_p1 = mraa_gpio_init_raw(242);
168 mraa_gpio_context io13_p1 = mraa_gpio_init_raw(243);
169 mraa_gpio_dir(io10_p1, MRAA_GPIO_OUT);
170 mraa_gpio_dir(io10_p2, MRAA_GPIO_OUT);
171 mraa_gpio_dir(io11_p1, MRAA_GPIO_OUT);
172 mraa_gpio_dir(io11_p2, MRAA_GPIO_OUT);
173 mraa_gpio_dir(io12_p1, MRAA_GPIO_OUT);
174 mraa_gpio_dir(io13_p1, MRAA_GPIO_OUT);
176 mraa_gpio_write(io10_p1, 1);
177 mraa_gpio_write(io10_p2, 0);
178 mraa_gpio_write(io11_p1, 1);
179 mraa_gpio_write(io11_p2, 0);
180 mraa_gpio_write(io12_p1, 0);
181 mraa_gpio_write(io13_p1, 0);
183 mraa_gpio_close(io10_p1);
184 mraa_gpio_close(io10_p2);
185 mraa_gpio_close(io11_p1);
186 mraa_gpio_close(io11_p2);
187 mraa_gpio_close(io12_p1);
188 mraa_gpio_close(io13_p1);
190 mraa_intel_edison_pinmode_change(111, 1);
191 mraa_intel_edison_pinmode_change(115, 1);
192 mraa_intel_edison_pinmode_change(114, 1);
193 mraa_intel_edison_pinmode_change(109, 1);
194 mraa_gpio_write(tristate, 1);
200 mraa_intel_edison_aio_get_fp(mraa_aio_context dev)
202 char file_path[64]= "";
204 snprintf(file_path, 64, "/sys/bus/iio/devices/iio:device1/in_voltage%d_raw",
207 dev->adc_in_fp = open(file_path, O_RDONLY);
208 if (dev->adc_in_fp == -1) {
209 syslog(LOG_ERR, "Failed to open Analog input raw file %s for "
210 "reading!", file_path);
211 return MRAA_ERROR_INVALID_RESOURCE;
218 mraa_intel_edison_aio_init_pre(unsigned int aio)
220 if (aio > plat->aio_count) {
221 syslog(LOG_ERR, "Invalid analog input channel");
222 return MRAA_ERROR_INVALID_RESOURCE;
226 mraa_gpio_context output_e;
227 output_e = mraa_gpio_init_raw(outputen[pin]);
228 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
229 return MRAA_ERROR_INVALID_RESOURCE;
230 if (mraa_gpio_write(output_e, 0) != MRAA_SUCCESS)
231 return MRAA_ERROR_INVALID_RESOURCE;
232 mraa_gpio_close(output_e);
234 mraa_gpio_context pullup_pin;
235 pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
236 if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS)
237 return MRAA_ERROR_INVALID_RESOURCE;
238 mraa_gpio_close(pullup_pin);
244 mraa_intel_edison_aio_init_post(mraa_aio_context dev)
246 mraa_gpio_write(tristate, 1);
251 mraa_intel_edison_pwm_init_pre(int pin)
253 if (pin < 0 || pin > 19)
254 return MRAA_ERROR_INVALID_RESOURCE;
256 if (!plat->pins[pin].capabilites.pwm)
257 return MRAA_ERROR_INVALID_RESOURCE;
259 mraa_gpio_context output_e;
260 output_e = mraa_gpio_init_raw(outputen[pin]);
261 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
262 return MRAA_ERROR_INVALID_RESOURCE;
263 if (mraa_gpio_write(output_e, 1) != MRAA_SUCCESS)
264 return MRAA_ERROR_INVALID_RESOURCE;
265 mraa_gpio_close(output_e);
267 mraa_gpio_context pullup_pin;
268 pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
269 if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS)
270 return MRAA_ERROR_INVALID_RESOURCE;
271 mraa_gpio_close(pullup_pin);
272 mraa_intel_edison_pinmode_change(plat->pins[pin].gpio.pinmap, 1);
278 mraa_intel_edison_pwm_init_post(mraa_pwm_context pwm)
280 mraa_gpio_write(tristate, 1);
285 mraa_intel_edison_spi_init_pre(int bus)
287 mraa_gpio_write(tristate, 0);
289 mraa_gpio_context io10_out = mraa_gpio_init_raw(258);
290 mraa_gpio_context io11_out = mraa_gpio_init_raw(259);
291 mraa_gpio_context io12_out = mraa_gpio_init_raw(260);
292 mraa_gpio_context io13_out = mraa_gpio_init_raw(261);
293 mraa_gpio_dir(io10_out, MRAA_GPIO_OUT);
294 mraa_gpio_dir(io11_out, MRAA_GPIO_OUT);
295 mraa_gpio_dir(io12_out, MRAA_GPIO_OUT);
296 mraa_gpio_dir(io13_out, MRAA_GPIO_OUT);
298 mraa_gpio_write(io10_out, 1);
299 mraa_gpio_write(io11_out, 1);
300 mraa_gpio_write(io12_out, 0);
301 mraa_gpio_write(io13_out, 1);
303 mraa_gpio_close(io10_out);
304 mraa_gpio_close(io11_out);
305 mraa_gpio_close(io12_out);
306 mraa_gpio_close(io13_out);
308 mraa_gpio_context io10_pull = mraa_gpio_init_raw(226);
309 mraa_gpio_context io11_pull = mraa_gpio_init_raw(227);
310 mraa_gpio_context io12_pull = mraa_gpio_init_raw(228);
311 mraa_gpio_context io13_pull = mraa_gpio_init_raw(229);
313 mraa_gpio_dir(io10_pull, MRAA_GPIO_IN);
314 mraa_gpio_dir(io11_pull, MRAA_GPIO_IN);
315 mraa_gpio_dir(io12_pull, MRAA_GPIO_IN);
316 mraa_gpio_dir(io13_pull, MRAA_GPIO_IN);
318 mraa_gpio_close(io10_pull);
319 mraa_gpio_close(io11_pull);
320 mraa_gpio_close(io12_pull);
321 mraa_gpio_close(io13_pull);
327 mraa_intel_edison_spi_init_post(mraa_spi_context spi)
329 mraa_gpio_write(tristate, 1);
334 mraa_intel_edison_gpio_mode_replace(mraa_gpio_context dev, gpio_mode_t mode)
336 if (dev->value_fp != -1) {
337 close(dev->value_fp);
341 mraa_gpio_context pullup_e;
342 pullup_e = mraa_gpio_init_raw(pullup_map[dev->phy_pin]);
343 mraa_result_t sta = mraa_gpio_dir(pullup_e, MRAA_GPIO_IN);
344 if(sta != MRAA_SUCCESS) {
345 syslog(LOG_ERR, "Edison: Failed to set gpio mode-pullup");
346 return MRAA_ERROR_INVALID_RESOURCE;
351 case MRAA_GPIO_STRONG:
353 case MRAA_GPIO_PULLUP:
356 case MRAA_GPIO_PULLDOWN:
363 return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
366 sta = mraa_gpio_dir(pullup_e, MRAA_GPIO_OUT);
367 sta = mraa_gpio_write(pullup_e, value);
368 if (sta != MRAA_SUCCESS) {
369 syslog(LOG_ERR, "Edison: Error Setting pullup");
379 mraa_intel_edison_fab_c()
381 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
385 b->phy_pin_count = 20;
389 advance_func->gpio_dir_pre = &mraa_intel_edison_gpio_dir_pre;
390 advance_func->gpio_init_post = &mraa_intel_edison_gpio_init_post;
391 advance_func->gpio_dir_post = &mraa_intel_edison_gpio_dir_post;
392 advance_func->i2c_init_pre = &mraa_intel_edison_i2c_init_pre;
393 advance_func->aio_get_valid_fp = &mraa_intel_edison_aio_get_fp;
394 advance_func->aio_init_pre = &mraa_intel_edison_aio_init_pre;
395 advance_func->aio_init_post = &mraa_intel_edison_aio_init_post;
396 advance_func->pwm_init_pre = &mraa_intel_edison_pwm_init_pre;
397 advance_func->pwm_init_post = &mraa_intel_edison_pwm_init_post;
398 advance_func->spi_init_pre = &mraa_intel_edison_spi_init_pre;
399 advance_func->spi_init_post = &mraa_intel_edison_spi_init_post;
400 advance_func->gpio_mode_replace = &mraa_intel_edison_gpio_mode_replace;
402 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_EDISON_PINCOUNT);
404 tristate = mraa_gpio_init_raw(214);
405 if (tristate == NULL) {
406 syslog(LOG_CRIT, "Intel Edison Failed to initialise Arduino board TriState,\
407 check i2c devices! FATAL\n");
411 mraa_gpio_dir(tristate, MRAA_GPIO_OUT);
412 mraa_intel_edison_misc_spi();
415 b->adc_supported = 10;
417 strncpy(b->pins[0].name, "IO0", 8);
418 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
419 b->pins[0].gpio.pinmap = 130;
420 b->pins[0].gpio.parent_id = 0;
421 b->pins[0].gpio.mux_total = 0;
423 strncpy(b->pins[1].name, "IO1", 8);
424 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
425 b->pins[1].gpio.pinmap = 131;
426 b->pins[1].gpio.parent_id = 0;
427 b->pins[1].gpio.mux_total = 0;
429 strncpy(b->pins[2].name, "IO2", 8);
430 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
431 b->pins[2].gpio.pinmap = 128;
432 b->pins[2].gpio.parent_id = 0;
433 b->pins[2].gpio.mux_total = 0;
435 strncpy(b->pins[3].name, "IO3", 8);
436 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
437 b->pins[3].gpio.pinmap = 12;
438 b->pins[3].gpio.parent_id = 0;
439 b->pins[3].gpio.mux_total = 0;
440 b->pins[3].pwm.pinmap = 0;
441 b->pins[3].pwm.parent_id = 0;
442 b->pins[3].pwm.mux_total = 0;
444 strncpy(b->pins[4].name, "IO4", 8);
445 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
446 b->pins[4].gpio.pinmap = 129;
447 b->pins[4].gpio.parent_id = 0;
448 b->pins[4].gpio.mux_total = 0;
450 strncpy(b->pins[5].name, "IO5", 8);
451 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
452 b->pins[5].gpio.pinmap = 13;
453 b->pins[5].gpio.parent_id = 0;
454 b->pins[5].gpio.mux_total = 0;
455 b->pins[5].pwm.pinmap = 1;
456 b->pins[5].pwm.parent_id = 0;
457 b->pins[5].pwm.mux_total = 0;
459 strncpy(b->pins[6].name, "IO6", 8);
460 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
461 b->pins[6].gpio.pinmap = 182;
462 b->pins[6].gpio.parent_id = 0;
463 b->pins[6].gpio.mux_total = 0;
464 b->pins[6].pwm.pinmap = 2;
465 b->pins[6].pwm.parent_id = 0;
466 b->pins[6].pwm.mux_total = 0;
468 strncpy(b->pins[7].name, "IO7", 8);
469 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
470 b->pins[7].gpio.pinmap = 48;
471 b->pins[7].gpio.parent_id = 0;
472 b->pins[7].gpio.mux_total = 0;
474 strncpy(b->pins[8].name, "IO8", 8);
475 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
476 b->pins[8].gpio.pinmap = 49;
477 b->pins[8].gpio.parent_id = 0;
478 b->pins[8].gpio.mux_total = 0;
480 strncpy(b->pins[9].name, "IO9", 8);
481 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
482 b->pins[9].gpio.pinmap = 183;
483 b->pins[9].gpio.parent_id = 0;
484 b->pins[9].gpio.mux_total = 0;
485 b->pins[9].pwm.pinmap = 3;
486 b->pins[9].pwm.parent_id = 0;
487 b->pins[9].pwm.mux_total = 0;
489 strncpy(b->pins[10].name, "IO10", 8);
490 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
491 b->pins[10].gpio.pinmap = 41;
492 b->pins[10].gpio.parent_id = 0;
493 b->pins[10].gpio.mux_total = 2;
494 b->pins[10].gpio.mux[0].pin = 263;
495 b->pins[10].gpio.mux[0].value = 1;
496 b->pins[10].gpio.mux[1].pin = 240;
497 b->pins[10].gpio.mux[1].value = 0;
498 b->pins[10].spi.pinmap = 5;
499 b->pins[10].spi.mux_total = 2;
500 b->pins[10].spi.mux[0].pin = 263;
501 b->pins[10].spi.mux[0].value = 1;
502 b->pins[10].spi.mux[1].pin = 240;
503 b->pins[10].spi.mux[1].value = 1;
505 strncpy(b->pins[11].name, "IO11", 8);
506 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
507 b->pins[11].gpio.pinmap = 43;
508 b->pins[11].gpio.parent_id = 0;
509 b->pins[11].gpio.mux_total = 2;
510 b->pins[11].gpio.mux[0].pin = 262;
511 b->pins[11].gpio.mux[0].value = 1;
512 b->pins[11].gpio.mux[1].pin = 241;
513 b->pins[11].gpio.mux[1].value = 0;
514 b->pins[11].spi.pinmap = 5;
515 b->pins[11].spi.mux_total = 2;
516 b->pins[11].spi.mux[0].pin = 262;
517 b->pins[11].spi.mux[0].value = 1;
518 b->pins[11].spi.mux[1].pin = 241;
519 b->pins[11].spi.mux[1].value = 1;
521 strncpy(b->pins[12].name, "IO12", 8);
522 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
523 b->pins[12].gpio.pinmap = 42;
524 b->pins[12].gpio.parent_id = 0;
525 b->pins[12].gpio.mux_total = 1;
526 b->pins[12].gpio.mux[0].pin = 242;
527 b->pins[12].gpio.mux[0].value = 0;
528 b->pins[12].spi.pinmap = 5;
529 b->pins[12].spi.mux_total = 1;
530 b->pins[12].spi.mux[0].pin = 242;
531 b->pins[12].spi.mux[0].value = 1;
533 strncpy(b->pins[13].name, "IO13", 8);
534 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
535 b->pins[13].gpio.pinmap = 40;
536 b->pins[13].gpio.parent_id = 0;
537 b->pins[13].gpio.mux_total = 1;
538 b->pins[13].gpio.mux[0].pin = 243;
539 b->pins[13].gpio.mux[0].value = 0;
540 b->pins[13].spi.pinmap = 5;
541 b->pins[13].spi.mux_total = 1;
542 b->pins[13].spi.mux[0].pin = 243;
543 b->pins[13].spi.mux[0].value = 1;
545 strncpy(b->pins[14].name, "A0", 8);
546 b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
547 b->pins[14].aio.pinmap = 0;
548 b->pins[14].aio.mux_total = 1;
549 b->pins[14].aio.mux[0].pin = 200;
550 b->pins[14].aio.mux[0].value = 1;
551 b->pins[14].gpio.pinmap = 44;
552 b->pins[14].gpio.mux_total = 1;
553 b->pins[14].gpio.mux[0].pin = 200;
554 b->pins[14].gpio.mux[0].value = 0;
556 strncpy(b->pins[15].name, "A1", 8);
557 b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
558 b->pins[15].aio.pinmap = 1;
559 b->pins[15].aio.mux_total = 1;
560 b->pins[15].aio.mux[0].pin = 201;
561 b->pins[15].aio.mux[0].value = 1;
562 b->pins[15].gpio.pinmap = 45;
563 b->pins[15].gpio.mux_total = 1;
564 b->pins[15].gpio.mux[0].pin = 201;
565 b->pins[15].gpio.mux[0].value = 0;
567 strncpy(b->pins[16].name, "A2", 8);
568 b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
569 b->pins[16].aio.pinmap = 2;
570 b->pins[16].aio.mux_total = 1;
571 b->pins[16].aio.mux[0].pin = 202;
572 b->pins[16].aio.mux[0].value = 1;
573 b->pins[16].gpio.pinmap = 46;
574 b->pins[16].gpio.mux_total = 1;
575 b->pins[16].gpio.mux[0].pin = 202;
576 b->pins[16].gpio.mux[0].value = 0;
578 strncpy(b->pins[17].name, "A3", 8);
579 b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
580 b->pins[17].aio.pinmap = 3;
581 b->pins[17].aio.mux_total = 1;
582 b->pins[17].aio.mux[0].pin = 203;
583 b->pins[17].aio.mux[0].value = 1;
584 b->pins[17].gpio.pinmap = 47;
585 b->pins[17].gpio.mux_total = 1;
586 b->pins[17].gpio.mux[0].pin = 203;
587 b->pins[17].gpio.mux[0].value = 0;
589 strncpy(b->pins[18].name, "A4", 8);
590 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
591 b->pins[18].i2c.pinmap = 1;
592 b->pins[18].i2c.mux_total = 1;
593 b->pins[18].i2c.mux[0].pin = 204;
594 b->pins[18].i2c.mux[0].value = 0;
595 b->pins[18].aio.pinmap = 4;
596 b->pins[18].aio.mux_total = 1;
597 b->pins[18].aio.mux[0].pin = 204;
598 b->pins[18].aio.mux[0].value = 1;
599 b->pins[18].gpio.pinmap = 14;
600 b->pins[18].gpio.mux_total = 1;
601 b->pins[18].gpio.mux[0].pin = 204;
602 b->pins[18].gpio.mux[0].value = 0;
604 strncpy(b->pins[19].name, "A5", 8);
605 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
606 b->pins[19].i2c.pinmap = 1;
607 b->pins[19].i2c.mux_total = 1;
608 b->pins[19].i2c.mux[0].pin = 205;
609 b->pins[19].i2c.mux[0].value = 0;
610 b->pins[19].aio.pinmap = 5;
611 b->pins[19].aio.mux_total = 1;
612 b->pins[19].aio.mux[0].pin = 205;
613 b->pins[19].aio.mux[0].value = 1;
614 b->pins[19].gpio.pinmap = 165;
615 b->pins[19].gpio.mux_total = 1;
616 b->pins[19].gpio.mux[0].pin = 205;
617 b->pins[19].gpio.mux[0].value = 0;
620 b->i2c_bus_count = 9;
623 for (ici = 0; ici < 9; ici++) {
624 b->i2c_bus[ici].bus_id = -1;
626 b->i2c_bus[6].bus_id = 6;
627 b->i2c_bus[6].sda = 18;
628 b->i2c_bus[6].scl = 19;
630 b->spi_bus_count = 1;
632 b->spi_bus[0].bus_id = 5;
633 b->spi_bus[0].slave_s = 1;
634 b->spi_bus[0].cs = 10;
635 b->spi_bus[0].mosi = 11;
636 b->spi_bus[0].miso = 12;
637 b->spi_bus[0].sclk = 13;
640 for (il =0; il < MRAA_INTEL_EDISON_PINCOUNT; il++) {
641 pinmodes[il].gpio.sysfs = -1;
642 pinmodes[il].gpio.mode = -1;
643 pinmodes[il].pwm.sysfs = -1;
644 pinmodes[il].pwm.mode = -1;
645 pinmodes[il].i2c.sysfs = -1;
646 pinmodes[il].i2c.mode = -1;
647 pinmodes[il].spi.sysfs = -1;
648 pinmodes[il].spi.mode = -1;
649 pinmodes[il].uart.sysfs = -1;
650 pinmodes[il].uart.mode = -1;
652 pinmodes[0].gpio.sysfs = 130;
653 pinmodes[0].gpio.mode = 0;
654 pinmodes[0].uart.sysfs = 130;
655 pinmodes[0].uart.mode = 1;
656 pinmodes[1].gpio.sysfs = 131;
657 pinmodes[1].gpio.mode = 0;
658 pinmodes[1].uart.sysfs = 131;
659 pinmodes[1].uart.mode = 1;
660 pinmodes[2].gpio.sysfs = 128;
661 pinmodes[2].gpio.mode = 0;
662 pinmodes[2].uart.sysfs = 128;
663 pinmodes[2].uart.mode = 1;
664 pinmodes[3].gpio.sysfs = 12;
665 pinmodes[3].gpio.mode = 0;
666 pinmodes[3].pwm.sysfs = 12;
667 pinmodes[3].pwm.mode = 1;
669 pinmodes[4].gpio.sysfs = 129;
670 pinmodes[4].gpio.mode = 0;
671 pinmodes[4].uart.sysfs = 129;
672 pinmodes[4].uart.mode = 1;
673 pinmodes[5].gpio.sysfs = 13;
674 pinmodes[5].gpio.mode = 0;
675 pinmodes[5].pwm.sysfs = 13;
676 pinmodes[5].pwm.mode = 1;
677 pinmodes[6].gpio.sysfs = 182;
678 pinmodes[6].gpio.mode = 0;
679 pinmodes[6].pwm.sysfs = 182;
680 pinmodes[6].pwm.mode = 1;
682 //7 and 8 are provided by something on i2c, very simplepinmodes[3].gpio.sysfs = 12;
683 pinmodes[9].gpio.sysfs = 183;
684 pinmodes[9].gpio.mode = 0;
685 pinmodes[9].pwm.sysfs = 183;
686 pinmodes[9].pwm.mode = 1;
688 pinmodes[10].gpio.sysfs = 41;
689 pinmodes[10].gpio.mode = 0;
690 pinmodes[10].spi.sysfs = 111; // Different pin provides, switched at mux level.
691 pinmodes[10].spi.mode = 1;
693 pinmodes[11].gpio.sysfs = 43;
694 pinmodes[11].gpio.mode = 0;
695 pinmodes[11].spi.sysfs = 115; // Different pin provides, switched at mux level.
696 pinmodes[11].spi.mode = 1;
698 pinmodes[12].gpio.sysfs = 42;
699 pinmodes[12].gpio.mode = 0;
700 pinmodes[12].spi.sysfs = 114; // Different pin provides, switched at mux level.
701 pinmodes[12].spi.mode = 1;
703 pinmodes[13].gpio.sysfs = 40;
704 pinmodes[13].gpio.mode = 0;
705 pinmodes[13].spi.sysfs = 109; // Different pin provides, switched at mux level.
706 pinmodes[13].spi.mode = 1;
707 //Everything else but A4 A5 LEAVE
708 pinmodes[18].gpio.sysfs = 14;
709 pinmodes[18].gpio.mode = 0;
710 pinmodes[18].i2c.sysfs = 28;
711 pinmodes[18].i2c.mode = 1;
713 pinmodes[19].gpio.sysfs = 165;
714 pinmodes[19].gpio.mode = 0;
715 pinmodes[19].i2c.sysfs = 27;
716 pinmodes[19].i2c.mode = 1;