2 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
3 * Copyright (c) 2014 Intel Corporation.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "intel_edison_fab_c.h"
31 #define SYSFS_PINMODE_PATH "/sys/kernel/debug/gpio_debug/gpio"
33 #define MAX_MODE_SIZE 8
38 } mraa_intel_edision_pindef_t;
41 mraa_intel_edision_pindef_t gpio;
42 mraa_intel_edision_pindef_t pwm;
43 mraa_intel_edision_pindef_t i2c;
44 mraa_intel_edision_pindef_t spi;
45 mraa_intel_edision_pindef_t uart;
46 } mraa_intel_edison_pinmodes_t;
48 static mraa_gpio_context tristate;
50 static mraa_intel_edison_pinmodes_t pinmodes[MRAA_INTEL_EDISON_PINCOUNT];
51 static unsigned int outputen[] = {248,249,250,251,252,253,254,255,256,257,258,259,260,261,232,233,234,235,236,237};
52 static unsigned int pullup_map[] = {216,217,218,219,220,221,222,223,224,225,226,227,228,229,208,209,210,211,212,213};
55 mraa_intel_edison_pinmode_change(int sysfs, int mode)
60 char buffer[MAX_SIZE];
61 snprintf(buffer, MAX_SIZE, SYSFS_PINMODE_PATH "%i/current_pinmux",sysfs);
62 int modef = open(buffer, O_WRONLY);
64 fprintf(stderr, "Failed to open SoC pinmode for opening\n");
65 return MRAA_ERROR_INVALID_RESOURCE;
68 char mode_buf[MAX_MODE_SIZE];
69 int length = sprintf(mode_buf, "mode%u",mode);
70 if (write(modef, mode_buf, length*sizeof(char)) == -1) {
71 return MRAA_ERROR_INVALID_RESOURCE;
79 mraa_intel_edison_gpio_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
81 mraa_gpio_write(tristate, 0);
82 if (dev->phy_pin >= 0) {
83 int pin = dev->phy_pin;
85 mraa_gpio_context output_e;
86 output_e = mraa_gpio_init_raw(outputen[pin]);
87 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
88 return MRAA_ERROR_INVALID_RESOURCE;
90 if (dir == MRAA_GPIO_OUT)
92 if (mraa_gpio_write(output_e, output_val) != MRAA_SUCCESS)
93 return MRAA_ERROR_INVALID_RESOURCE;
99 mraa_intel_edison_gpio_dir_post(mraa_gpio_context dev, gpio_dir_t dir)
101 mraa_gpio_write(tristate, 1);
106 mraa_intel_edison_gpio_init_post(mraa_gpio_context dev)
109 return MRAA_ERROR_INVALID_RESOURCE;
111 int sysfs = pinmodes[dev->phy_pin].gpio.sysfs;
112 int mode = pinmodes[dev->phy_pin].gpio.mode;
113 mraa_result_t ret = mraa_intel_edison_pinmode_change(sysfs, mode);
119 mraa_intel_edison_i2c_init_pre(unsigned int bus)
122 fprintf(stderr, "Edison: You can use that bus, ERR\n");
123 return MRAA_ERROR_INVALID_RESOURCE;
125 mraa_gpio_write(tristate, 0);
126 mraa_gpio_context io18_gpio = mraa_gpio_init_raw(14);
127 mraa_gpio_context io19_gpio = mraa_gpio_init_raw(165);
128 mraa_gpio_dir(io18_gpio, MRAA_GPIO_IN);
129 mraa_gpio_dir(io19_gpio, MRAA_GPIO_IN);
130 mraa_gpio_close(io18_gpio);
131 mraa_gpio_close(io19_gpio);
133 mraa_gpio_context io18_enable = mraa_gpio_init_raw(236);
134 mraa_gpio_context io19_enable = mraa_gpio_init_raw(237);
135 mraa_gpio_dir(io18_enable, MRAA_GPIO_OUT);
136 mraa_gpio_dir(io19_enable, MRAA_GPIO_OUT);
137 mraa_gpio_write(io18_enable, 0);
138 mraa_gpio_write(io19_enable, 0);
139 mraa_gpio_close(io18_enable);
140 mraa_gpio_close(io19_enable);
142 mraa_gpio_context io18_pullup = mraa_gpio_init_raw(212);
143 mraa_gpio_context io19_pullup = mraa_gpio_init_raw(213);
144 mraa_gpio_dir(io18_pullup, MRAA_GPIO_IN);
145 mraa_gpio_dir(io19_pullup, MRAA_GPIO_IN);
146 mraa_gpio_close(io18_pullup);
147 mraa_gpio_close(io19_pullup);
149 mraa_intel_edison_pinmode_change(28, 1);
150 mraa_intel_edison_pinmode_change(27, 1);
152 mraa_gpio_write(tristate, 1);
157 mraa_intel_edison_misc_spi()
159 mraa_gpio_write(tristate, 0);
161 mraa_gpio_context io10_p1 = mraa_gpio_init_raw(263);
162 mraa_gpio_context io10_p2 = mraa_gpio_init_raw(240);
163 mraa_gpio_context io11_p1 = mraa_gpio_init_raw(262);
164 mraa_gpio_context io11_p2 = mraa_gpio_init_raw(241);
165 mraa_gpio_context io12_p1 = mraa_gpio_init_raw(242);
166 mraa_gpio_context io13_p1 = mraa_gpio_init_raw(243);
167 mraa_gpio_dir(io10_p1, MRAA_GPIO_OUT);
168 mraa_gpio_dir(io10_p2, MRAA_GPIO_OUT);
169 mraa_gpio_dir(io11_p1, MRAA_GPIO_OUT);
170 mraa_gpio_dir(io11_p2, MRAA_GPIO_OUT);
171 mraa_gpio_dir(io12_p1, MRAA_GPIO_OUT);
172 mraa_gpio_dir(io13_p1, MRAA_GPIO_OUT);
174 mraa_gpio_write(io10_p1, 1);
175 mraa_gpio_write(io10_p2, 0);
176 mraa_gpio_write(io11_p1, 1);
177 mraa_gpio_write(io11_p2, 0);
178 mraa_gpio_write(io12_p1, 0);
179 mraa_gpio_write(io13_p1, 0);
181 mraa_gpio_close(io10_p1);
182 mraa_gpio_close(io10_p2);
183 mraa_gpio_close(io11_p1);
184 mraa_gpio_close(io11_p2);
185 mraa_gpio_close(io12_p1);
186 mraa_gpio_close(io13_p1);
188 mraa_intel_edison_pinmode_change(111, 1);
189 mraa_intel_edison_pinmode_change(115, 1);
190 mraa_intel_edison_pinmode_change(114, 1);
191 mraa_intel_edison_pinmode_change(109, 1);
192 mraa_gpio_write(tristate, 1);
198 mraa_intel_edison_aio_get_fp(mraa_aio_context dev)
200 char file_path[64]= "";
202 snprintf(file_path, 64, "/sys/bus/iio/devices/iio:device1/in_voltage%d_raw",
205 dev->adc_in_fp = open(file_path, O_RDONLY);
206 if (dev->adc_in_fp == -1) {
207 fprintf(stderr, "Failed to open Analog input raw file %s for "
208 "reading!\n", file_path); return( MRAA_ERROR_INVALID_RESOURCE);
215 mraa_intel_edison_aio_init_pre(unsigned int aio)
217 if (aio > plat->aio_count) {
218 fprintf(stderr, "Invalid analog input channel\n");
219 return MRAA_ERROR_INVALID_RESOURCE;
223 mraa_gpio_context output_e;
224 output_e = mraa_gpio_init_raw(outputen[pin]);
225 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
226 return MRAA_ERROR_INVALID_RESOURCE;
227 if (mraa_gpio_write(output_e, 0) != MRAA_SUCCESS)
228 return MRAA_ERROR_INVALID_RESOURCE;
229 mraa_gpio_close(output_e);
231 mraa_gpio_context pullup_pin;
232 pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
233 if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS)
234 return MRAA_ERROR_INVALID_RESOURCE;
235 mraa_gpio_close(pullup_pin);
241 mraa_intel_edison_aio_init_post(mraa_aio_context dev)
243 mraa_gpio_write(tristate, 1);
248 mraa_intel_edison_pwm_init_pre(int pin)
250 if (pin < 0 || pin > 19)
251 return MRAA_ERROR_INVALID_RESOURCE;
253 if (!plat->pins[pin].capabilites.pwm)
254 return MRAA_ERROR_INVALID_RESOURCE;
256 mraa_gpio_context output_e;
257 output_e = mraa_gpio_init_raw(outputen[pin]);
258 if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
259 return MRAA_ERROR_INVALID_RESOURCE;
260 if (mraa_gpio_write(output_e, 1) != MRAA_SUCCESS)
261 return MRAA_ERROR_INVALID_RESOURCE;
262 mraa_gpio_close(output_e);
264 mraa_gpio_context pullup_pin;
265 pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
266 if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS)
267 return MRAA_ERROR_INVALID_RESOURCE;
268 mraa_gpio_close(pullup_pin);
269 mraa_intel_edison_pinmode_change(plat->pins[pin].gpio.pinmap, 1);
275 mraa_intel_edison_pwm_init_post(mraa_pwm_context pwm)
277 mraa_gpio_write(tristate, 1);
282 mraa_intel_edison_fab_c()
284 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
288 b->phy_pin_count = 20;
292 advance_func->gpio_dir_pre = &mraa_intel_edison_gpio_dir_pre;
293 advance_func->gpio_init_post = &mraa_intel_edison_gpio_init_post;
294 advance_func->gpio_dir_post = &mraa_intel_edison_gpio_dir_post;
295 advance_func->i2c_init_pre = &mraa_intel_edison_i2c_init_pre;
296 advance_func->aio_get_valid_fp = &mraa_intel_edison_aio_get_fp;
297 advance_func->aio_init_pre = &mraa_intel_edison_aio_init_pre;
298 advance_func->aio_init_post = &mraa_intel_edison_aio_init_post;
299 advance_func->pwm_init_pre = &mraa_intel_edison_pwm_init_pre;
300 advance_func->pwm_init_post = &mraa_intel_edison_pwm_init_post;
302 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_EDISON_PINCOUNT);
304 tristate = mraa_gpio_init_raw(214);
305 if (tristate == NULL) {
306 fprintf(stderr, "Intel Edison Failed to initialise Arduino board TriState,\
307 check i2c devices! FATAL\n");
310 mraa_gpio_dir(tristate, MRAA_GPIO_OUT);
311 mraa_intel_edison_misc_spi();
313 strncpy(b->pins[0].name, "IO0", 8);
314 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
315 b->pins[0].gpio.pinmap = 130;
316 b->pins[0].gpio.parent_id = 0;
317 b->pins[0].gpio.mux_total = 0;
319 strncpy(b->pins[1].name, "IO1", 8);
320 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
321 b->pins[1].gpio.pinmap = 131;
322 b->pins[1].gpio.parent_id = 0;
323 b->pins[1].gpio.mux_total = 0;
325 strncpy(b->pins[2].name, "IO2", 8);
326 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
327 b->pins[2].gpio.pinmap = 128;
328 b->pins[2].gpio.parent_id = 0;
329 b->pins[2].gpio.mux_total = 0;
331 strncpy(b->pins[3].name, "IO3", 8);
332 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
333 b->pins[3].gpio.pinmap = 12;
334 b->pins[3].gpio.parent_id = 0;
335 b->pins[3].gpio.mux_total = 0;
336 b->pins[3].pwm.pinmap = 0;
337 b->pins[3].pwm.parent_id = 0;
338 b->pins[3].pwm.mux_total = 0;
340 strncpy(b->pins[4].name, "IO4", 8);
341 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
342 b->pins[4].gpio.pinmap = 129;
343 b->pins[4].gpio.parent_id = 0;
344 b->pins[4].gpio.mux_total = 0;
346 strncpy(b->pins[5].name, "IO5", 8);
347 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
348 b->pins[5].gpio.pinmap = 13;
349 b->pins[5].gpio.parent_id = 0;
350 b->pins[5].gpio.mux_total = 0;
351 b->pins[5].pwm.pinmap = 1;
352 b->pins[5].pwm.parent_id = 0;
353 b->pins[5].pwm.mux_total = 0;
355 strncpy(b->pins[6].name, "IO6", 8);
356 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
357 b->pins[6].gpio.pinmap = 182;
358 b->pins[6].gpio.parent_id = 0;
359 b->pins[6].gpio.mux_total = 0;
360 b->pins[6].pwm.pinmap = 2;
361 b->pins[6].pwm.parent_id = 0;
362 b->pins[6].pwm.mux_total = 0;
364 strncpy(b->pins[7].name, "IO7", 8);
365 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
366 b->pins[7].gpio.pinmap = 48;
367 b->pins[7].gpio.parent_id = 0;
368 b->pins[7].gpio.mux_total = 0;
370 strncpy(b->pins[8].name, "IO8", 8);
371 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
372 b->pins[8].gpio.pinmap = 49;
373 b->pins[8].gpio.parent_id = 0;
374 b->pins[8].gpio.mux_total = 0;
376 strncpy(b->pins[9].name, "IO9", 8);
377 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
378 b->pins[9].gpio.pinmap = 183;
379 b->pins[9].gpio.parent_id = 0;
380 b->pins[9].gpio.mux_total = 0;
381 b->pins[9].pwm.pinmap = 3;
382 b->pins[9].pwm.parent_id = 0;
383 b->pins[9].pwm.mux_total = 0;
385 strncpy(b->pins[10].name, "IO10", 8);
386 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
387 b->pins[10].gpio.pinmap = 41;
388 b->pins[10].gpio.parent_id = 0;
389 b->pins[10].gpio.mux_total = 2;
390 b->pins[10].gpio.mux[0].pin = 263;
391 b->pins[10].gpio.mux[0].value = 1;
392 b->pins[10].gpio.mux[1].pin = 240;
393 b->pins[10].gpio.mux[1].value = 0;
394 b->pins[11].spi.pinmap = 5;
395 b->pins[11].spi.mux_total = 2;
396 b->pins[11].spi.mux[0].pin = 263;
397 b->pins[11].spi.mux[0].value = 1;
398 b->pins[11].spi.mux[1].pin = 240;
399 b->pins[11].spi.mux[2].value = 1;
401 strncpy(b->pins[11].name, "IO11", 8);
402 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
403 b->pins[11].gpio.pinmap = 43;
404 b->pins[11].gpio.parent_id = 0;
405 b->pins[11].gpio.mux_total = 2;
406 b->pins[11].gpio.mux[0].pin = 262;
407 b->pins[11].gpio.mux[0].value = 1;
408 b->pins[11].gpio.mux[1].pin = 241;
409 b->pins[11].gpio.mux[1].value = 0;
410 b->pins[11].spi.pinmap = 5;
411 b->pins[11].spi.mux_total = 2;
412 b->pins[11].spi.mux[0].pin = 262;
413 b->pins[11].spi.mux[0].value = 1;
414 b->pins[11].spi.mux[1].pin = 241;
415 b->pins[11].spi.mux[2].value = 1;
417 strncpy(b->pins[12].name, "IO12", 8);
418 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
419 b->pins[12].gpio.pinmap = 42;
420 b->pins[12].gpio.parent_id = 0;
421 b->pins[12].gpio.mux_total = 1;
422 b->pins[12].gpio.mux[0].pin = 242;
423 b->pins[12].gpio.mux[0].value = 0;
424 b->pins[12].spi.pinmap = 5;
425 b->pins[12].spi.mux_total = 1;
426 b->pins[12].spi.mux[0].pin = 242;
427 b->pins[12].spi.mux[0].value = 1;
429 strncpy(b->pins[13].name, "IO13", 8);
430 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
431 b->pins[13].gpio.pinmap = 40;
432 b->pins[13].gpio.parent_id = 0;
433 b->pins[13].gpio.mux_total = 1;
434 b->pins[13].gpio.mux[0].pin = 243;
435 b->pins[13].gpio.mux[0].value = 0;
436 b->pins[12].spi.pinmap = 5;
437 b->pins[12].spi.mux_total = 1;
438 b->pins[12].spi.mux[0].pin = 243;
439 b->pins[12].spi.mux[0].value = 1;
441 strncpy(b->pins[14].name, "A0", 8);
442 b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
443 b->pins[14].aio.pinmap = 0;
444 b->pins[14].aio.mux_total = 1;
445 b->pins[14].aio.mux[0].pin = 200;
446 b->pins[14].aio.mux[0].value = 1;
447 b->pins[14].gpio.pinmap = 44;
448 b->pins[14].gpio.mux_total = 1;
449 b->pins[14].gpio.mux[0].pin = 200;
450 b->pins[14].gpio.mux[0].value = 0;
452 strncpy(b->pins[15].name, "A1", 8);
453 b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
454 b->pins[15].aio.pinmap = 1;
455 b->pins[15].aio.mux_total = 1;
456 b->pins[15].aio.mux[0].pin = 201;
457 b->pins[15].aio.mux[0].value = 1;
458 b->pins[15].gpio.pinmap = 45;
459 b->pins[15].gpio.mux_total = 1;
460 b->pins[15].gpio.mux[0].pin = 201;
461 b->pins[15].gpio.mux[0].value = 0;
463 strncpy(b->pins[16].name, "A2", 8);
464 b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
465 b->pins[16].aio.pinmap = 2;
466 b->pins[16].aio.mux_total = 1;
467 b->pins[16].aio.mux[0].pin = 202;
468 b->pins[16].aio.mux[0].value = 1;
469 b->pins[16].gpio.pinmap = 46;
470 b->pins[16].gpio.mux_total = 1;
471 b->pins[16].gpio.mux[0].pin = 202;
472 b->pins[16].gpio.mux[0].value = 0;
474 strncpy(b->pins[17].name, "A3", 8);
475 b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
476 b->pins[17].aio.pinmap = 3;
477 b->pins[17].aio.mux_total = 1;
478 b->pins[17].aio.mux[0].pin = 203;
479 b->pins[17].aio.mux[0].value = 1;
480 b->pins[17].gpio.pinmap = 47;
481 b->pins[17].gpio.mux_total = 1;
482 b->pins[17].gpio.mux[0].pin = 203;
483 b->pins[17].gpio.mux[0].value = 0;
485 strncpy(b->pins[18].name, "A4", 8);
486 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
487 b->pins[18].i2c.pinmap = 1;
488 b->pins[18].i2c.mux_total = 1;
489 b->pins[18].i2c.mux[0].pin = 204;
490 b->pins[18].i2c.mux[0].value = 0;
491 b->pins[18].aio.pinmap = 4;
492 b->pins[18].aio.mux_total = 1;
493 b->pins[18].aio.mux[0].pin = 204;
494 b->pins[18].aio.mux[0].value = 1;
495 b->pins[18].gpio.pinmap = 14;
496 b->pins[18].gpio.mux_total = 1;
497 b->pins[18].gpio.mux[0].pin = 204;
498 b->pins[18].gpio.mux[0].value = 0;
500 strncpy(b->pins[19].name, "A5", 8);
501 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
502 b->pins[19].i2c.pinmap = 1;
503 b->pins[19].i2c.mux_total = 1;
504 b->pins[19].i2c.mux[0].pin = 205;
505 b->pins[19].i2c.mux[0].value = 0;
506 b->pins[19].aio.pinmap = 5;
507 b->pins[19].aio.mux_total = 1;
508 b->pins[19].aio.mux[0].pin = 205;
509 b->pins[19].aio.mux[0].value = 1;
510 b->pins[19].gpio.pinmap = 165;
511 b->pins[19].gpio.mux_total = 1;
512 b->pins[19].gpio.mux[0].pin = 205;
513 b->pins[19].gpio.mux[0].value = 0;
516 b->i2c_bus_count = 9;
519 for (ici = 0; ici < 9; ici++) {
520 b->i2c_bus[ici].bus_id = -1;
522 b->i2c_bus[6].bus_id = 6;
523 b->i2c_bus[6].sda = 18;
524 b->i2c_bus[6].scl = 19;
526 b->spi_bus_count = 1;
528 b->spi_bus[0].bus_id = 5;
529 b->spi_bus[0].slave_s = 1;
530 b->spi_bus[0].cs = 10;
531 b->spi_bus[0].mosi = 11;
532 b->spi_bus[0].miso = 12;
533 b->spi_bus[0].sclk = 13;
537 for(il =0; il < MRAA_INTEL_EDISON_PINCOUNT; il++) {
538 pinmodes[il].gpio.sysfs = -1;
539 pinmodes[il].gpio.mode = -1;
540 pinmodes[il].pwm.sysfs = -1;
541 pinmodes[il].pwm.mode = -1;
542 pinmodes[il].i2c.sysfs = -1;
543 pinmodes[il].i2c.mode = -1;
544 pinmodes[il].spi.sysfs = -1;
545 pinmodes[il].spi.mode = -1;
546 pinmodes[il].uart.sysfs = -1;
547 pinmodes[il].uart.mode = -1;
549 pinmodes[0].gpio.sysfs = 130;
550 pinmodes[0].gpio.mode = 0;
551 pinmodes[0].uart.sysfs = 130;
552 pinmodes[0].uart.mode = 1;
553 pinmodes[1].gpio.sysfs = 131;
554 pinmodes[1].gpio.mode = 0;
555 pinmodes[1].uart.sysfs = 131;
556 pinmodes[1].uart.mode = 1;
557 pinmodes[2].gpio.sysfs = 128;
558 pinmodes[2].gpio.mode = 0;
559 pinmodes[2].uart.sysfs = 128;
560 pinmodes[2].uart.mode = 1;
561 pinmodes[3].gpio.sysfs = 12;
562 pinmodes[3].gpio.mode = 0;
563 pinmodes[3].pwm.sysfs = 12;
564 pinmodes[3].pwm.mode = 1;
566 pinmodes[4].gpio.sysfs = 129;
567 pinmodes[4].gpio.mode = 0;
568 pinmodes[4].uart.sysfs = 129;
569 pinmodes[4].uart.mode = 1;
570 pinmodes[5].gpio.sysfs = 13;
571 pinmodes[5].gpio.mode = 0;
572 pinmodes[5].pwm.sysfs = 13;
573 pinmodes[5].pwm.mode = 1;
574 pinmodes[6].gpio.sysfs = 182;
575 pinmodes[6].gpio.mode = 0;
576 pinmodes[6].pwm.sysfs = 182;
577 pinmodes[6].pwm.mode = 1;
579 //7 and 8 are provided by something on i2c, very simplepinmodes[3].gpio.sysfs = 12;
580 pinmodes[9].gpio.sysfs = 183;
581 pinmodes[9].gpio.mode = 0;
582 pinmodes[9].pwm.sysfs = 183;
583 pinmodes[9].pwm.mode = 1;
585 pinmodes[10].gpio.sysfs = 41;
586 pinmodes[10].gpio.mode = 0;
587 pinmodes[10].spi.sysfs = 111; // Different pin provides, switched at mux level.
588 pinmodes[10].spi.mode = 1;
590 pinmodes[11].gpio.sysfs = 43;
591 pinmodes[11].gpio.mode = 0;
592 pinmodes[11].spi.sysfs = 115; // Different pin provides, switched at mux level.
593 pinmodes[11].spi.mode = 1;
595 pinmodes[12].gpio.sysfs = 42;
596 pinmodes[12].gpio.mode = 0;
597 pinmodes[12].spi.sysfs = 114; // Different pin provides, switched at mux level.
598 pinmodes[12].spi.mode = 1;
600 pinmodes[13].gpio.sysfs = 40;
601 pinmodes[13].gpio.mode = 0;
602 pinmodes[13].spi.sysfs = 109; // Different pin provides, switched at mux level.
603 pinmodes[13].spi.mode = 1;
604 //Everything else but A4 A5 LEAVE
605 pinmodes[18].gpio.sysfs = 14;
606 pinmodes[18].gpio.mode = 0;
607 pinmodes[18].i2c.sysfs = 28;
608 pinmodes[18].i2c.mode = 1;
610 pinmodes[19].gpio.sysfs = 165;
611 pinmodes[19].gpio.mode = 0;
612 pinmodes[19].i2c.sysfs = 27;
613 pinmodes[19].i2c.mode = 1;